> On 08-Sep-2023, at 7:48 PM, Athira Rajeev wrote:
>
>
>
>> On 08-Sep-2023, at 11:04 AM, Sachin Sant wrote:
>>
>>
>>
>>> On 07-Sep-2023, at 10:29 PM, Athira Rajeev
>>> wrote:
>>>
>>> Testcase "Parsing of all PMU events from sysfs" parse events for
>>> all PMUs, and not just cpu. In
> On 08-Sep-2023, at 7:47 PM, Athira Rajeev wrote:
>
>
>
>> On 08-Sep-2023, at 5:20 AM, Ian Rogers wrote:
>>
>> On Thu, Sep 7, 2023 at 10:17 AM Athira Rajeev
>> wrote:
>>>
>>> From: root
>>>
>>> shellcheck was run on perf tool shell scripts s a pre-requisite
>>> to include a build
Le 12/09/2023 à 22:09, Erhard Furtner a écrit :
> On Tue, 12 Sep 2023 17:39:10 +
> Christophe Leroy wrote:
>
>> Ah ok, maybe your CPU only has 4 BATs and they are all used, following
>> change would tell us.
>>
>> diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
allnoconfig gcc
csky allyesconfig gcc
cskydefconfig gcc
csky randconfig-r006-20230913 gcc
csky randconfig-r013-20230912 gcc
csky randconfig-r025-20230913
On Tue, Sep 12, 2023 at 2:34 PM Chancel Liu wrote:
>
> i.MX rpmsg sound cards work on codec slave mode. MCLK will be disabled
> by CPU DAI driver in hw_free(). Some codec requires MCLK present at
> power up/down sequence. So need to set ignore_pmdown_time to power down
> codec immediately before
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
topic/ppc-kvm
head: 5af8497e01ed97410b2f19ca8320a3bcdcfe267b
commit: da467d188ec7dd17770d813226cd92329e9b5b3b [10/11] KVM: PPC: Add support
for nestedv2 guests
config: powerpc-ppc64_defconfig
On Tue, Sep 12, 2023 at 4:17 PM Puranjay Mohan wrote:
>
> On Wed, Sep 13, 2023 at 1:04 AM Russell King (Oracle)
> wrote:
> >
> > On Tue, Sep 12, 2023 at 10:46:53PM +, Puranjay Mohan wrote:
> > > The JITs should not depend on the verifier for zero extending the upper
> > > 32 bits of the
On Wed, Sep 13, 2023 at 1:04 AM Russell King (Oracle)
wrote:
>
> On Tue, Sep 12, 2023 at 10:46:53PM +, Puranjay Mohan wrote:
> > The JITs should not depend on the verifier for zero extending the upper
> > 32 bits of the destination register when loading a byte, half-word, or
> > word.
> >
> >
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
topic/ppc-kvm
head: 5af8497e01ed97410b2f19ca8320a3bcdcfe267b
commit: c531e958f40241e921456e7b77574a25f713a2e5 [8/11] KVM: PPC: Add helper
library for Guest State Buffers
config: powerpc-ppc64_defconfig
On Tue, Sep 12, 2023 at 10:46:53PM +, Puranjay Mohan wrote:
> The JITs should not depend on the verifier for zero extending the upper
> 32 bits of the destination register when loading a byte, half-word, or
> word.
>
> A following patch will make the verifier stop patching zext instructions
>
Aboorva Devarajan writes:
> From: Pratik R. Sampat
>
> Introduce a mechanism to fire directed IPIs from a source CPU to a
> specified target CPU and measure the time incurred on waking up the
> target CPU in response.
>
> Also, introduce a mechanism to queue a hrtimer on a specified CPU and
>
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
arch/arm/net/bpf_jit_32.c |
All 64-bit JITs utilize a single instruction to load + zero-extend a
byte, word, or a half-word. The optimisation of emitting zext for LDX is
not useful for most of the JITs.
All the JITs that relied on the verifier for zero extension of LDX
desitination registers have been modified to always
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
All 64-bit architectures that support the BPF JIT do LDX + zero extension
with a single CPU instruction. Some 64-bit architectures like riscv64,
s390, mips64, etc. have bpf_jit_needs_zext() -> true. This means although
these architectures do LDX + zero extension with a single CPU instruction,
the
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
Update the documentation for trusted and encrypted KEYS with DCP as new
trust source:
- Describe security properties of DCP trust source
- Describe key usage
- Document blob format
Co-developed-by: Richard Weinberger
Signed-off-by: Richard Weinberger
Co-developed-by: David Oberhollenzer
DCP (Data Co-Processor) is the little brother of NXP's CAAM IP.
Beside of accelerated crypto operations, it also offers support for
hardware-bound keys. Using this feature it is possible to implement a blob
mechanism just like CAAM offers. Unlike on CAAM, constructing and
parsing the blob has to
DCP is capable to performing AES with hardware-bound keys.
These keys are not stored in main memory and are therefore not directly
accessible by the operating system.
So instead of feeding the key into DCP, we need to place a
reference to such a key before initiating the crypto operation.
Keys
This is a revival of the previous patch set submitted by Richard Weinberger:
https://lore.kernel.org/linux-integrity/20210614201620.30451-1-rich...@nod.at/
v1 -> v2:
- Revive and rebase to latest version
- Include review comments from Ahmad Fatoum
The Data CoProcessor (DCP) is an IP core built
On Mon, 2023-09-11 at 18:02 +, Sohil Mehta wrote:
> diff --git a/arch/powerpc/kernel/syscalls/syscall.tbl
> b/arch/powerpc/kernel/syscalls/syscall.tbl
> index 20e50586e8a2..2767b8a42636 100644
> --- a/arch/powerpc/kernel/syscalls/syscall.tbl
> +++ b/arch/powerpc/kernel/syscalls/syscall.tbl
>
Support for map_shadow_stack() was recently added but it is an x86
only system call for now. There is a possibility that other
architectures (namely, arm64 and Risc-V) that are implementing support
for shadow stacks, might need to add support for it.
Independent of that, reserving arch-specific
The syscall table entries in the core kernel and perf are expected to be
in sync. This would fix perf build warnings and also add support for
fchmodat2 in 'perf trace'.
Signed-off-by: Sohil Mehta
---
tools/include/uapi/asm-generic/unistd.h | 5 -
6.6-rc1 has added support for 2 new system calls:
[1] fchmodat2()
[2] x86-specific map_shadow_stack()
This series mainly synchronizes the syscall tables arcoss the core kernel and
tools to reflect the recent updates.
For fchmodat2(), it fixes the missing entries in the tools directory.
For
On Tue, Sep 12, 2023 at 4:31 PM Mark Brown wrote:
> On Tue, Sep 12, 2023 at 01:04:56PM +0200, Linus Walleij wrote:
> > On Tue, Sep 12, 2023 at 12:15 PM Herve Codina
> > wrote:
>
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
>
> > I think SPDX mandates that you start the tag with C99
On Tue, 12 Sep 2023 17:39:10 +
Christophe Leroy wrote:
> Ah ok, maybe your CPU only has 4 BATs and they are all used, following
> change would tell us.
>
> diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
> index 850783cfa9c7..bd26767edce7 100644
> ---
On Sep 12 2023, Liam R. Howlett wrote:
> * Andreas Schwab [230912 14:15]:
>> Any news? This is still broken.
>
> I have a proposed fix. I seem to have caused a pre-existing problem to
> show up. Please see if the attached works for you, and I'll send it
> to a lot of people.
Thanks, it fixes
On Tue, 2023-09-12 at 22:32 +0300, Jarkko Sakkinen wrote:
> On Tue Sep 12, 2023 at 10:22 PM EEST, Mimi Zohar wrote:
> > On Tue, 2023-09-12 at 12:49 +0300, Jarkko Sakkinen wrote:
> > > On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> > > > On Mon, Sep 11, 2023 at 11:39:38PM -0400,
Em Tue, Sep 12, 2023 at 07:00:00AM -0700, Ian Rogers escreveu:
> On Mon, Sep 11, 2023 at 11:38 PM Athira Rajeev
> wrote:
> >
> > Makefile.perf uses "CONFIG_*" checks in the code. Example the config
> > for libtraceevent is used to set PYTHON_EXT_SRCS
> >
> > ifeq
On Tue Sep 12, 2023 at 10:22 PM EEST, Mimi Zohar wrote:
> On Tue, 2023-09-12 at 12:49 +0300, Jarkko Sakkinen wrote:
> > On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> > > On Mon, Sep 11, 2023 at 11:39:38PM -0400, Nayna wrote:
> > > >
> > > > On 9/7/23 13:32, Michal Suchánek wrote:
* Andreas Schwab [230912 14:15]:
> Any news? This is still broken.
I have a proposed fix. I seem to have caused a pre-existing problem to
show up. Please see if the attached works for you, and I'll send it
to a lot of people.
Thanks,
Liam
>From 9ef8f834bb0342dc26464b9dd0165929d3e6a7e5 Mon
On Tue, 2023-09-12 at 12:49 +0300, Jarkko Sakkinen wrote:
> On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> > On Mon, Sep 11, 2023 at 11:39:38PM -0400, Nayna wrote:
> > >
> > > On 9/7/23 13:32, Michal Suchánek wrote:
> > > > Adding more CC's from the original patch, looks like
On Tue, Sep 12, 2023 at 07:13:32PM +0100, Conor Dooley wrote:
> Yo,
>
> I'm not au fait enough with this to leave particularly meaningful
> comments, so just some minor ones for you.
>
> On Tue, Sep 12, 2023 at 12:14:44PM +0200, Herve Codina wrote:
> > The Lantiq PEF2256 is a framer and line
Hi Pingfan,
kernel test robot noticed the following build errors:
[auto build test ERROR on powerpc/fixes]
[also build test ERROR on linus/master v6.6-rc1 next-20230912]
[cannot apply to powerpc/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting
Le 12/09/2023 à 20:13, Conor Dooley a écrit :
> Yo,
>
> I'm not au fait enough with this to leave particularly meaningful
> comments, so just some minor ones for you.
>
> On Tue, Sep 12, 2023 at 12:14:44PM +0200, Herve Codina wrote:
>> The Lantiq PEF2256 is a framer and line interface
On Tue, 12 Sep 2023 10:14:58 +0200, Herve Codina wrote:
> Additional properties in child node should not be allowed.
>
> Prevent them adding 'additionalProperties: false'
>
> Signed-off-by: Herve Codina
> ---
> .../devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 1 +
> 1 file
On Tue, Sep 12, 2023 at 12:58:32PM -0500, Rob Herring wrote:
> On Tue, Sep 12, 2023 at 10:14:57AM +0200, Herve Codina wrote:
> > The given example mentions the 'fsl,mode' property whereas the
> > correct property name, the one described, is 'fsl,operational-mode'.
> >
> > Fix the example to use
Any news? This is still broken.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
Yo,
I'm not au fait enough with this to leave particularly meaningful
comments, so just some minor ones for you.
On Tue, Sep 12, 2023 at 12:14:44PM +0200, Herve Codina wrote:
> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an
On Tue, Sep 12, 2023 at 10:14:57AM +0200, Herve Codina wrote:
> The given example mentions the 'fsl,mode' property whereas the
> correct property name, the one described, is 'fsl,operational-mode'.
>
> Fix the example to use the correct property name.
>
> Fixes: a9b121327c93 ("dt-bindings: soc:
Le 12/09/2023 à 17:59, Erhard Furtner a écrit :
>
> printk: bootconsole [udbg0] enabled
> Total memory = 2048MB; using 4096kB for hash table
> mapin_ram:125
> mmu_mapin_ram:169 0 3000 140 200
> __mmu_mapin_ram:146 0 140
> __mmu_mapin_ram:155 140
> __mmu_mapin_ram:146 140
On Tue Sep 12, 2023 at 2:11 PM EEST, David Gstir wrote:
> DCP (Data Co-Processor) is the little brother of NXP's CAAM IP.
>
> Beside of accelerated crypto operations, it also offers support for
> hardware-bound keys. Using this feature it is possible to implement a blob
> mechanism just like CAAM
On Tue Sep 12, 2023 at 2:11 PM EEST, David Gstir wrote:
> @@ -101,6 +102,7 @@ struct dcp_async_ctx {
> struct crypto_skcipher *fallback;
> unsigned intkey_len;
> uint8_t key[AES_KEYSIZE_128];
> + bool
On Tue Sep 12, 2023 at 2:11 PM EEST, David Gstir wrote:
> DCP is capable to performing AES with hardware-bound keys.
> These keys are not stored in main memory and are therefore not directly
> accessible by the operating system.
>
> So instead of feeding the key into DCP, we need to place a
>
On Tue, Sep 12, 2023 at 12:10:18PM +0200, Herve Codina wrote:
> The QMC (QUICC mutichannel controller) is a controller present in some
> PowerQUICC SoC such as MPC885.
> The QMC HDLC uses the QMC controller to transfer HDLC data.
>
> Additionally, a framer can be connected to the QMC HDLC.
> If
On Tue Sep 12, 2023 at 6:39 AM EEST, Nayna wrote:
>
> On 9/7/23 13:32, Michal Suchánek wrote:
> > Adding more CC's from the original patch, looks like get_maintainers is
> > not that great for this file.
> >
> > On Thu, Sep 07, 2023 at 06:52:19PM +0200, Michal Suchanek wrote:
> >> No other
On Tue, Sep 12, 2023 at 10:14:58AM +0200, Herve Codina wrote:
> Additional properties in child node should not be allowed.
>
> Prevent them adding 'additionalProperties: false'
>
> Signed-off-by: Herve Codina
Acked-by: Conor Dooley
Thanks,
Conor.
> ---
>
On Tue, Sep 12, 2023 at 10:14:57AM +0200, Herve Codina wrote:
> The given example mentions the 'fsl,mode' property whereas the
> correct property name, the one described, is 'fsl,operational-mode'.
>
> Fix the example to use the correct property name.
>
> Fixes: a9b121327c93 ("dt-bindings: soc:
On Tue, 12 Sep 2023 07:47:50 +
Christophe Leroy wrote:
> I suspect something wrong when we set the BATs.
>
> Can you try with the following additional traces:
>
> diff --git a/arch/powerpc/mm/kasan/book3s_32.c
> b/arch/powerpc/mm/kasan/book3s_32.c
> index 450a67ef0bbe..9954b7a3b7ae 100644
On Tue, Sep 12, 2023 at 01:04:56PM +0200, Linus Walleij wrote:
> On Tue, Sep 12, 2023 at 12:15 PM Herve Codina
> wrote:
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> I think SPDX mandates that you start the tag with C99 comments
> // SPDX-License-Identifier: GPL-2.0-only
Not for
On Mon, Sep 11, 2023 at 11:38 PM Athira Rajeev
wrote:
>
> Makefile.perf uses "CONFIG_*" checks in the code. Example the config
> for libtraceevent is used to set PYTHON_EXT_SRCS
>
> ifeq ($(CONFIG_LIBTRACEEVENT),y)
> PYTHON_EXT_SRCS := $(shell grep -v ^\#
* Christophe Leroy [230912 06:56]:
> Hi,
>
> With pmac32_defconfig on QEMU I get the following WARN with 6.6-rc1
>
> Bisected to cfeb6ae8bcb9 ("maple_tree: disable mas_wr_append() when
> other readers are possible")
>
> I have absolutely no idea what it can be, do you ?
Please see the
Remove 'file' parameter from struct machdep_calls.phys_mem_access_prot
and its implementation in pci_phys_mem_access_prot(). The file is not
used on PowerPC. By removing it, a later patch can simplify fbdev's
mmap code, which uses phys_mem_access_prot() on PowerPC.
Signed-off-by: Thomas
Call __phys_mem_access_prot() from the fbdev mmap helper
pgprot_framebuffer(). Allows to avoid the file argument of NULL.
Signed-off-by: Thomas Zimmermann
---
arch/powerpc/include/asm/fb.h | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/fb.h
Clean up and rename fb_pgprotect() to work without struct file. Then
refactor the implementation for PowerPC. This change has been discussed
at [1] in the context of refactoring fbdev's mmap code.
The first two patches update fbdev and replace fbdev's fb_pgprotect()
with pgprot_framebuffer() on
Only PowerPC's fb_pgprotect() needs the file argument, although
the implementation does not use it. Pass NULL to the internal
helper in preparation of further updates. A later patch will remove
the file parameter from fb_pgprotect().
While at it, replace the shift operation with PHYS_PFN().
Rename the fbdev mmap helper fb_pgprotect() to pgprot_framebuffer().
The helper sets VMA page-access flags for framebuffers in device I/O
memory.
Also clean up the helper's parameters and return value. Instead of
the VMA instance, pass the individial parameters separately: existing
page-access
Fix coding style. No functional changes.
Signed-off-by: Thomas Zimmermann
---
arch/powerpc/include/asm/machdep.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/powerpc/include/asm/machdep.h
index
On 2023-09-11 21:23:42 Mon, Pingfan Liu wrote:
> Hi Mahesh,
>
> I am not quite sure about fdt, so I skip that part, and leave some
> comments from the kexec view.
>
> On Thu, Sep 7, 2023 at 1:59 AM Mahesh Salgaonkar wrote:
> >
> > The kernel boot parameter 'nr_cpus=' allows one to specify
On Tue, Sep 12, 2023 at 12:15 PM Herve Codina wrote:
> After contributing the driver, add myself as the maintainer for the
> Lantiq PEF2256 driver.
>
> Signed-off-by: Herve Codina
> Reviewed-by: Christophe Leroy
> Signed-off-by: Christophe Leroy
> ---
> MAINTAINERS | 9 +
> 1 file
Hi Herve,
thanks for your patch!
On Tue, Sep 12, 2023 at 12:15 PM Herve Codina wrote:
> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
>
> This kind of
Hi,
With pmac32_defconfig on QEMU I get the following WARN with 6.6-rc1
Bisected to cfeb6ae8bcb9 ("maple_tree: disable mas_wr_append() when
other readers are possible")
I have absolutely no idea what it can be, do you ?
[ cut here ]
Interrupts were enabled early
On Tue, Sep 12, 2023 at 12:15 PM Herve Codina wrote:
> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
>
> Signed-off-by: Herve Codina
> Reviewed-by:
Add framer support in the fsl_qmc_hdlc driver in order to be able to
signal carrier changes to the network stack based on the framer status
Also use this framer to provide information related to the E1/T1 line
interface on IF_GET_IFACE and configure the line interface according to
IF_IFACE_{E1,T1}
The framer codec interacts with a framer.
It allows to use some of the framer timeslots as audio channels to
transport audio data over the framer E1/T1/J1 lines.
It also reports line carrier detection events through the ALSA jack
detection feature.
Signed-off-by: Herve Codina
Reviewed-by:
After contributing the driver, add myself as the maintainer for the
Lantiq PEF2256 driver.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.
This kind of component can be found in old telecommunication system.
It was used to digital transmission of many
The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
The loop searching for a matching device based on its compatible
string is aborted when a matching disabled device is found.
This abort prevents to add devices as soon as one disabled device
is found.
Continue searching for an other device instead of aborting on the
first disabled one fixes the
The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.
Signed-off-by: Herve Codina
Signed-off-by: Christophe Leroy
---
.../bindings/net/lantiq,pef2256.yaml |
A framer is a component in charge of an E1/T1 line interface.
Connected usually to a TDM bus, it converts TDM frames to/from E1/T1
frames. It also provides information related to the E1/T1 line.
The framer framework provides a set of APIs for the framer drivers
(framer provider) to create/destroy
QMC channels support runtime timeslots changes but nothing is done at
the QMC HDLC driver to handle these changes.
Use existing IFACE ioctl in order to configure the timeslots to use.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
Introduce qmc_chan_{get,set}_ts_info() function to allow timeslots
modification at runtime.
The modification is provided using qmc_chan_set_ts_info() and will be
applied on next qmc_chan_start().
qmc_chan_set_ts_info() must be called with the channel rx and/or tx
stopped.
Signed-off-by: Herve
Timeslots setting is done at channel start() and stop().
There is no more need to do that during setup_chan().
Simply remove timeslot setting from setup_chan().
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 28
In order to support runtime timeslot route changes, enable the
channel timeslot entries at channel start() and disable them at
channel stop().
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 175
In order to support runtime timeslot route changes, some operations will
be different according the routing table used (common Rx and Tx table or
one table for Rx and one for Tx).
The is_tsa_64rxtx flag is introduced to avoid extra computation to
determine the table format each time we need it.
The Tx and Rx entries for a given channel are set in one function.
In order to modify Rx entries and Tx entries independently of one other,
split this function in one for the Rx part and one for the Tx part.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe
In order to allow runtime timeslot route changes, disabling channel TSA
entries needs to be supported.
Add support for this new feature.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 20 +++-
1 file
The timeslots checked in qmc_check_chans() are the timeslots used.
With the introduction of the available timeslots, the used timeslots
are a subset of the available timeslots. The timeslots checked during
the qmc_check_chans() call should be the available ones.
Simply update and check the
The newly introduced qmc_chan_setup_tsa* functions check that the
channel entries are not already used.
These checks are also performed by qmc_check_chans() and are no more
needed.
Remove them from qmc_check_chans().
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by:
Introduce the qmc_chan_setup_tsa* functions to setup entries related
to the given channel.
Use them during QMC channels setup.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 161 ++-
qmc_setup_tsa* are called once at initialisation.
They initialize the QMC TSA table.
In order to introduce setup function later on for dynamic timeslots
management, rename the function to avoid later confusion.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe
Available timeslots masks define timeslots available for the related
channel. These timeslots are defined by the QMC binding.
Timeslots used are initialized to available timeslots but can be a
subset of available timeslots.
This prepares the dynamic timeslots management (ie. changing timeslots
at
After contributing the driver, add myself as the maintainer for the
Freescale QMC HDLC driver.
Signed-off-by: Herve Codina
Signed-off-by: Christophe Leroy
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..8b987f2c8633
The QMC HDLC driver provides support for HDLC using the QMC (QUICC
Multichannel Controller) to transfer the HDLC data.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
Signed-off-by: Christophe Leroy
---
drivers/net/wan/Kconfig| 12 +
drivers/net/wan/Makefile | 1 +
QMC child devices support is needed to avoid orphan DT nodes that use a
simple DT phandle to reference a QMC channel.
Allow to instantiate child devices and also extend the API to get the
qmc_chan using a child device.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 91
The QMC (QUICC mutichannel controller) is a controller present in some
PowerQUICC SoC such as MPC885.
The QMC HDLC uses the QMC controller to transfer HDLC data.
Additionally, a framer can be connected to the QMC HDLC.
If present, this framer is the interface between the TDM bus used by the
QMC
Additional properties in child node should not be allowed.
Prevent them adding 'additionalProperties: false'
Signed-off-by: Herve Codina
---
.../devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> On Mon, Sep 11, 2023 at 11:39:38PM -0400, Nayna wrote:
> >
> > On 9/7/23 13:32, Michal Suchánek wrote:
> > > Adding more CC's from the original patch, looks like get_maintainers is
> > > not that great for this file.
> > >
> > > On
The given example mentions the 'fsl,mode' property whereas the
correct property name, the one described, is 'fsl,operational-mode'.
Fix the example to use the correct property name.
Fixes: a9b121327c93 ("dt-bindings: soc: fsl: cpm_qe: Add QMC controller")
Signed-off-by: Herve Codina
---
The inline function specifier is present on some functions but it is
better to let the compiler decide inlining or not these functions.
Remove inline specifiers.
Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC")
Signed-off-by: Herve Codina
Suggested-by: Andrew Lunn
Reviewed-by:
In HDLC mode, some status flags related to the data read transfer can be
set by the hardware and need to be known by a QMC consumer for further
analysis.
Extend the API in order to provide these transfer status flags at the
read complete() call.
In TRANSPARENT mode, these flags have no meaning.
On 11/09/23 4:01 pm, Baoquan He wrote:
On 09/11/23 at 05:13pm, Michael Ellerman wrote:
Hari Bathini writes:
Currently, is_kdump_kernel() returns true when elfcorehdr_addr is set.
While elfcorehdr_addr is set for kexec based kernel dump mechanism,
alternate dump capturing methods like
The qmc_chan_reset_rx() set the is_rx_stopped flag. This leads to an
inconsistent state in the following sequence.
qmc_chan_stop()
qmc_chan_reset()
Indeed, after the qmc_chan_reset() call, the channel must still be
stopped. Only a qmc_chan_start() call can move the channel from stopped
Running sparse (make C=1) on qmc.c raises a lot of warning such as:
...
warning: incorrect type in assignment (different address spaces)
expected struct cpm_buf_desc [usertype] *[noderef] __iomem bd
got struct cpm_buf_desc [noderef] [usertype] __iomem *txbd_free
...
Indeed, some
Running sparse (make C=1) on tsa.c raises a lot of warning such as:
--- 8< ---
warning: incorrect type in assignment (different address spaces)
expected void *[noderef] si_regs
got void [noderef] __iomem *
--- 8< ---
Indeed, some variable were declared 'type *__iomem var' instead
Currently, is_kdump_kernel() returns true in crash dump capture kernel
for both kdump and fadump crash dump capturing methods, as both these
methods set elfcorehdr_addr. Some restrictions enforced for crash dump
capture kernel, based on is_kdump_kernel(), are specifically meant for
kdump case and
Currently, is_kdump_kernel() returns true when elfcorehdr_addr is set.
While elfcorehdr_addr is set for kexec based kernel dump mechanism,
alternate dump capturing methods like fadump [1] also set it to export
the vmcore. Since, is_kdump_kernel() is used to restrict resources in
crash dump capture
1 - 100 of 106 matches
Mail list logo
