-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/xmon/xmon.c | 62
1 file changed, 58 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 3fd1d9a..f74ec83 100644
--- a/arch/powerpc
On 06/01/2014 11:48 AM, Michael Neuling wrote:
On Fri, 2014-05-30 at 17:40 +0530, Anshuman Khandual wrote:
This patch enables support for hardware instruction breakpoints on POWER8
with
the help of a new register called CIABR (Completed Instruction Address
Breakpoint
Register
On 06/02/2014 06:29 PM, Stephane Eranian wrote:
On Wed, May 28, 2014 at 10:04 AM, Anshuman Khandual
khand...@linux.vnet.ibm.com wrote:
On 05/27/2014 05:39 PM, Stephane Eranian wrote:
I have been looking at those patches and ran some tests.
And I found a few issues so far.
I am running
On 05/30/2014 07:12 PM, Aneesh Kumar K.V wrote:
Anshuman Khandual khand...@linux.vnet.ibm.com writes:
This patch enables support for hardware instruction breakpoints on POWER8
with
the help of a new register called CIABR (Completed Instruction Address
Breakpoint
Register
On 06/02/2014 02:18 PM, Anshuman Khandual wrote:
On 06/01/2014 11:48 AM, Michael Neuling wrote:
On Fri, 2014-05-30 at 17:40 +0530, Anshuman Khandual wrote:
This patch enables support for hardware instruction breakpoints on
POWER8 with
the help of a new register called CIABR (Completed
On 06/03/2014 11:33 AM, Anshuman Khandual wrote:
On 05/30/2014 07:12 PM, Aneesh Kumar K.V wrote:
Anshuman Khandual khand...@linux.vnet.ibm.com writes:
This patch enables support for hardware instruction breakpoints on
POWER8 with
the help of a new register called CIABR (Completed
On 06/05/2014 08:51 PM, Shreyas B. Prabhu wrote:
Build throws following errors when CONFIG_SMP=n
arch/powerpc/platforms/powernv/setup.c: In function
‘pnv_kexec_wait_secondaries_down’:
arch/powerpc/platforms/powernv/setup.c:179:4: error: implicit declaration of
function
On 06/05/2014 08:54 PM, Shreyas B. Prabhu wrote:
Build throws following errors when CONFIG_SMP=n
arch/powerpc/platforms/powernv/subcore.c: In function ‘cpu_update_split_mode’:
arch/powerpc/platforms/powernv/subcore.c:274:15: error: ‘setup_max_cpus’
undeclared (first use in this function)
On 06/04/2014 02:18 PM, Anshuman Khandual wrote:
On 06/03/2014 11:33 AM, Anshuman Khandual wrote:
On 05/30/2014 07:12 PM, Aneesh Kumar K.V wrote:
Anshuman Khandual khand...@linux.vnet.ibm.com writes:
This patch enables support for hardware instruction breakpoints on
POWER8 with
the help
On 05/23/2014 08:45 PM, Anshuman Khandual wrote:
This patch series adds five new ELF core note sections which can be
used with existing ptrace request PTRACE_GETREGSET/SETREGSET for accessing
various transactional memory and miscellaneous register sets on PowerPC
platform. Please find
On 06/12/2014 02:39 PM, Anshuman Khandual wrote:
On 05/23/2014 08:45 PM, Anshuman Khandual wrote:
This patch series adds five new ELF core note sections which can be
used with existing ptrace request PTRACE_GETREGSET/SETREGSET for accessing
various transactional memory and miscellaneous
On 07/18/2014 04:53 AM, Sam Bobroff wrote:
On 17/07/14 21:14, Michael Neuling wrote:
On Jul 17, 2014 9:11 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org mailto:b...@kernel.crashing.org wrote:
Outstanding Issues
==
(1) Running DSCR register value inside a transaction
On 09/26/2013 12:01 PM, Michael Ellerman wrote:
+int powernv_hwrng_present(void)
+{
+ return __raw_get_cpu_var(powernv_rng) != NULL;
+}
+
static unsigned long rng_whiten(struct powernv_rng *rng, unsigned long val)
{
unsigned long parity;
@@ -42,6 +48,17 @@ static unsigned long
the requested
-- HW BHRB branch filter enabled in MMCRA.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/core-book3s.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core
On 10/08/2013 09:51 AM, Michael Ellerman wrote:
On Mon, Oct 07, 2013 at 10:00:26AM +0530, Anshuman Khandual wrote:
Right now the `config_bhrb` PMU specific call happens after write_mmcr0
which actually enables the PMU for event counting and interrupt. So
there is a small window of time where
On 10/09/2013 06:51 AM, Michael Ellerman wrote:
On Tue, Oct 08, 2013 at 12:51:18PM +0530, Anshuman Khandual wrote:
On 10/08/2013 09:51 AM, Michael Ellerman wrote:
On Mon, Oct 07, 2013 at 10:00:26AM +0530, Anshuman Khandual wrote:
Right now the `config_bhrb` PMU specific call happens after
On 09/26/2013 04:44 PM, Stephane Eranian wrote:
So you are saying that the HW filter is exclusive. That seems odd. But
I think it is
because of the choices is ANY. ANY covers all the types of branches. Therefore
it does not make a difference whether you add COND or not. And
vice-versa, if you
On 10/09/2013 11:33 AM, Michael Ellerman wrote:
On Wed, Oct 09, 2013 at 10:16:32AM +0530, Anshuman Khandual wrote:
On 10/09/2013 06:51 AM, Michael Ellerman wrote:
On Tue, Oct 08, 2013 at 12:51:18PM +0530, Anshuman Khandual wrote:
On 10/08/2013 09:51 AM, Michael Ellerman wrote:
On Mon, Oct 07
On 10/11/2013 07:41 AM, Michael Ellerman wrote:
On Thu, Oct 10, 2013 at 02:20:22PM +0530, Anshuman Khandual wrote:
On 10/09/2013 11:33 AM, Michael Ellerman wrote:
On Wed, Oct 09, 2013 at 10:16:32AM +0530, Anshuman Khandual wrote:
On 10/09/2013 06:51 AM, Michael Ellerman wrote:
On Tue, Oct 08
On 10/14/2013 11:49 AM, Michael Ellerman wrote:
On Fri, Oct 11, 2013 at 10:02:28AM +0530, Anshuman Khandual wrote:
On 10/11/2013 07:41 AM, Michael Ellerman wrote:
On Thu, Oct 10, 2013 at 02:20:22PM +0530, Anshuman Khandual wrote:
Even I think this is not right. Instruction sampling should
/
0.003600713 seconds time elapsed
=
Anshuman Khandual (2):
power7, perf: Make some new raw event codes available in sysfs
power8, perf: Export raw event codes through sysfs interface
arch/powerpc/perf/power7-events
This patch exports a set of POWER8 PMU raw event codes through
sysfs interface. Right now the raw event set matches the entire
set of POWER8 events found in libpfm4 library.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-events-list.h | 146
This patch adds some more raw event codes into the existing list
of event codes present in power7-events-list.h file. This tries
to complete the list of events supported in Power7 and matches
the raw event list with libpfm4 library.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
This patch adds enumeration for all available SW branch filters
in powerpc book3s code and also streamlines the look for the
SW branch filter entries while trying to figure out which all
branch filters can be supported in SW.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch
This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
Enables conditional branch filter support for POWER8
utilizing MMCRA register based filter and also invalidates
a BHRB branch filter combination involving conditional
branches.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 10 ++
1 file
Adding documentation support for conditional branch filter.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
tools/perf/Documentation/perf-record.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf
This patch simply changes the name of the variable from bhrb_filter to
bhrb_hw_filter in order to add one more variable which will track SW
filters in generic powerpc book3s code which will be implemented in the
subsequent patch.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
all. Its the PMU code's responsibility to uphold this protocol to be
able to
conform to the overall OR semantic of perf branch stack sampling
framework.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h | 6 +-
arch/powerpc
Adding perf record support for new branch stack filter criteria
PERF_SAMPLE_BRANCH_COND.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
tools/perf/builtin-record.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf
where.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/code-patching.h | 30 ++
arch/powerpc/lib/code-patching.c | 54 ++--
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include
combinations PMU will pass it on to the SW.
Also the combination of PERF_SAMPLE_BRANCH_ANY_CALL and PERF_SAMPLE_BRANCH_COND
can now be handled in SW, hence we dont error them out anymore.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 73
This patchset is the re-spin of the original branch stack
sampling
patchset which introduced new PERF_SAMPLE_BRANCH_COND branch filter. This
patchset
also enables SW based branch filtering support for book3s powerpc platforms
which
have PMU HW backed branch stack sampling
of instructions.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
include/uapi/linux/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index
On 10/16/2013 01:55 PM, David Laight wrote:
Implement instr_is_load_store_2_06() to detect whether a given instruction
is one of the fixed-point or floating-point load/store instructions in the
POWER Instruction Set Architecture v2.06.
...
The op code encoding is dependent on the ISA version
On 11/26/2013 11:36 AM, m...@ellerman.id.au wrote:
Ideally your commit subject would contain a verb, preferably in the present
tense.
I think simply perf: Add PERF_SAMPLE_BRANCH_COND would be clearer.
Sure, will change it.
On Wed, 2013-16-10 at 06:56:48 UTC, Anshuman Khandual wrote
On 11/26/2013 11:36 AM, m...@ellerman.id.au wrote:
On Wed, 2013-16-10 at 06:56:49 UTC, Anshuman Khandual wrote:
Enables conditional branch filter support for POWER8
utilizing MMCRA register based filter and also invalidates
a BHRB branch filter combination involving conditional
branches
On 11/26/2013 03:45 PM, Anshuman Khandual wrote:
On 11/26/2013 11:36 AM, m...@ellerman.id.au wrote:
Ideally your commit subject would contain a verb, preferably in the present
tense.
I think simply perf: Add PERF_SAMPLE_BRANCH_COND would be clearer.
Sure, will change it.
On Wed, 2013
Enables conditional branch filter support for POWER8
utilizing MMCRA register based filter and also invalidates
any BHRB branch filter combination.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 10 ++
1 file changed, 10 insertions
all. Its the PMU code's responsibility to uphold this protocol to be
able to
conform to the overall OR semantic of perf branch stack sampling
framework.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h | 6 +-
arch/powerpc
Adding documentation support for conditional branch filter.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
tools/perf/Documentation/perf-record.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf
of instructions.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
include/uapi/linux/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index
This patchset is the re-spin of the original branch stack
sampling
patchset which introduced new PERF_SAMPLE_BRANCH_COND branch filter. This
patchset
also enables SW based branch filtering support for book3s powerpc platforms
which
have PMU HW backed branch stack sampling
Adding perf record support for new branch stack filter criteria
PERF_SAMPLE_BRANCH_COND.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
tools/perf/builtin-record.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf
where.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/code-patching.h | 30 ++
arch/powerpc/lib/code-patching.c | 54 ++--
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include
This patch adds enumeration for all available SW branch filters
in powerpc book3s code and also streamlines the look for the
SW branch filter entries while trying to figure out which all
branch filters can be supported in SW.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch
This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
combinations PMU will pass it on to the SW.
Also the combination of PERF_SAMPLE_BRANCH_ANY_CALL and PERF_SAMPLE_BRANCH_COND
can now be handled in SW, hence we dont error them out anymore.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 73
This patch simply changes the name of the variable from bhrb_filter to
bhrb_hw_filter in order to add one more variable which will track SW
filters in generic powerpc book3s code which will be implemented in the
subsequent patch.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Michael,
I believe this patch should be able to take care of this.
commit d66d729715cabe0cfd8e34861a6afa8ad639ddf3
Author: Anshuman Khandual khand...@linux.vnet.ibm.com
Date: Tue Dec 10 11:10:06 2013 +0530
power, perf: Clean up BHRB processing
This patch cleans up some indentation
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
On Wed, 2013-04-12 at 10:32:39 UTC, Anshuman Khandual wrote:
Generic powerpc branch instruction analysis support added in the code
patching library which will help the subsequent patch on SW based
filtering of branch records in perf. This patch
On 12/10/2013 11:27 AM, Anshuman Khandual wrote:
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
This code was already in need of some unindentation, and now it's just
ridiculous.
To start with at the beginning of this routine we have:
while (..) {
if (!val)
break
On 12/13/2013 08:20 AM, Michael Ellerman wrote:
On Wed, 2013-10-16 at 11:22 +0530, Anshuman Khandual wrote:
This patch adds some more raw event codes into the existing list
of event codes present in power7-events-list.h file. This tries
to complete the list of events supported in Power7
On 10/16/2013 10:00 AM, Anshuman Khandual wrote:
On 10/14/2013 11:49 AM, Michael Ellerman wrote:
On Fri, Oct 11, 2013 at 10:02:28AM +0530, Anshuman Khandual wrote:
On 10/11/2013 07:41 AM, Michael Ellerman wrote:
On Thu, Oct 10, 2013 at 02:20:22PM +0530, Anshuman Khandual wrote:
Even I think
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
As I said in my comments on version 3 which you ignored:
I think it would be clearer if we actually checked for the possibilities
we
allow and let everything else fall through, eg:
        /* Ignore user/kernel/hv bits */
On 12/18/2013 07:44 AM, Michael Ellerman wrote:
From: Anshuman Khandual khand...@linux.vnet.ibm.com
Right now the config_bhrb() PMU specific call happens after
write_mmcr0(), which actually enables the PMU for event counting and
interrupts. So there is a small window of time where the PMU
On 12/18/2013 05:38 AM, Michael Ellerman wrote:
On Fri, 2013-12-13 at 13:50 +0530, Anshuman Khandual wrote:
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
As I said in my comments on version 3 which you ignored:
I think it would be clearer if we actually checked for the
possibilities
On 12/10/2013 11:39 AM, Anshuman Khandual wrote:
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
On Wed, 2013-04-12 at 10:32:39 UTC, Anshuman Khandual wrote:
Generic powerpc branch instruction analysis support added in the code
patching library which will help the subsequent patch on SW based
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
On Wed, 2013-04-12 at 10:32:40 UTC, Anshuman Khandual wrote:
This patch enables SW based post processing of BHRB captured branches
to be able to meet more user defined branch filtration criteria in perf
branch stack sampling framework
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
On Wed, 2013-04-12 at 10:32:42 UTC, Anshuman Khandual wrote:
This patch adds enumeration for all available SW branch filters
in powerpc book3s code and also streamlines the look for the
SW branch filter entries while trying to figure out which
On 12/24/2013 08:59 AM, Michael Ellerman wrote:
On Fri, 2013-12-20 at 16:31 +0530, Anshuman Khandual wrote:
On 12/09/2013 11:51 AM, Michael Ellerman wrote:
On Wed, 2013-04-12 at 10:32:40 UTC, Anshuman Khandual wrote:
+
+ if (bhrb_sw_filter PERF_SAMPLE_BRANCH_IND_CALL) {
+ /* XL
This patchset adds some missing event list for POWER7 PMU raw
events which are exported through sysfs interface. Also updates
the ABI documentation to add all the sysfs exported raw events.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
.../testing/sysfs-bus-event_source
On 12/18/2013 07:29 AM, Michael Ellerman wrote:
On Fri, 2013-12-13 at 10:00 +0530, Anshuman Khandual wrote:
On 12/13/2013 08:20 AM, Michael Ellerman wrote:
On Wed, 2013-10-16 at 11:22 +0530, Anshuman Khandual wrote:
This patch adds some more raw event codes into the existing list
of event
:
CPU#5 SDAR:
CPU#5 SIER:
CPU#5 MMCR2: EBBHR:
CPU#5 EBBRR: BESCR:
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/core-book3s.c | 54
On 01/22/2014 07:02 AM, Michael Ellerman wrote:
On Thu, 2014-01-16 at 15:53 -0800, Cody P Schafer wrote:
These patches add basic pmus for 2 powerpc hypervisor interfaces to obtain
performance counters: gpci (get performance counter info) and 24x7.
The counters supplied by these interfaces are
This patch cleans up some existing indentation problem and
re-organizes the BHRB processing code with an helper function
named `update_branch_entry` making it more readable. This patch
does not change any functionality.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch
This patch introduces new branch filter PERF_SAMPLE_BRANCH_COND which
will extend the existing perf ABI. Various architectures can provide
this functionality with either with HW filtering support (if present)
or with SW filtering of captured branch instructions.
Signed-off-by: Anshuman Khandual
This patch does some code re-arrangements to make it clear that
it ignores any separate privilege level branch filter request
and does not support any combinations of HW PMU branch filters.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 21
%cprog [unknown] [.] ld-2.11.2.so
[.] malloc
Please refer to the V4 version of the patchset to learn about the sample test
case and it's makefile.
Anshuman Khandual (11):
powerpc, perf: Re-arrange BHRB processing
perf: Add
Adding perf record support for new branch stack filter criteria
PERF_SAMPLE_BRANCH_COND.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
tools/perf/builtin-record.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf
Adding documentation support for conditional branch filter.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
tools/perf/Documentation/perf-record.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf
This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/core-book3s.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 8a44dc1..468f58c 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b
Generic powerpc branch analysis support added in the code patching
library which will help the subsequent patch on SW based filtering
of branch records in perf.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/code-patching.h | 16 +++
arch/powerpc
the SW to handle
them
all. Its the PMU code's responsibility to uphold this protocol to be
able to
conform to the overall OR semantic of perf branch stack sampling
framework.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm
to meet those protocols.
POWER8 PMU can only handle one HW based branch filter request at any point of
time.
For all other combinations PMU will pass it on to the SW.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 50
the privilege mode branch filters itself.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/core-book3s.c | 53 +++--
arch/powerpc/perf/power8-pmu.c | 13 --
2 files changed, 52 insertions(+), 14 deletions(-)
diff --git a/arch
On 01/02/2014 10:32 AM, Anshuman Khandual wrote:
This patchset adds some missing event list for POWER7 PMU raw
events which are exported through sysfs interface. Also updates
the ABI documentation to add all the sysfs exported raw events.
Signed-off-by: Anshuman Khandual khand
On 10/12/2012 06:58 AM, Sukadev Bhattiprolu wrote:
From 89cb6a25b9f714e55a379467a832ee015014ed11 Mon Sep 17 00:00:00 2001
From: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Date: Tue, 18 Sep 2012 10:59:01 -0700
Subject: [PATCH] perf: Add a few generic stalled-cycles events
The existing
On 11/06/2012 07:23 AM, Michael Neuling wrote:
+ if (!found pvr_version_is(PVR_POWER7)) {
+ /* check active counters for special buggy p7 overflow */
+ for (i = 0; i cpuhw-n_events; ++i) {
+ event = cpuhw-event[i];
+ if
On 11/06/2012 03:49 PM, Michael Neuling wrote:
I have couple of questions.
Can the buggy overflow happen on any of the available counters PMC1-PMC4 ?
No. It's limited to certain events and I believe it can only happen on
PMC2 and 4. This code doesn't bother trying to make this
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
Change the representation of the PMU flags from decimal to hex since they
are bitfields which are easier to read in hex.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h | 20 +++-
1 file changed, 15 insertions(+), 5
On 11/16/2012 05:12 PM, Paul Mackerras wrote:
On Fri, Nov 16, 2012 at 02:29:04PM +0530, Anshuman Khandual wrote:
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
That's not a sufficient description of why you are making this
change. In particular, what is the motivation
Change the representation of the PMU flags from decimal to hex since they
are bitfields which are easier to read in hex.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
Changed the 64 bit constants into 32 bit constants as it would apply to
32 bit variable power_pmu.flags
On 12/02/2014 11:53 PM, Shuah Khan wrote:
On 12/02/2014 12:56 AM, Anshuman Khandual wrote:
This patch includes all of the powerpc test binaries into the
.gitignore file listing in their respective directories. This
will make sure that GIT ignores all of these test binaries while
On 12/03/2014 10:52 AM, Michael Ellerman wrote:
On Tue, 2014-02-12 at 07:56:45 UTC, Anshuman Khandual wrote:
This patch adds four new ELF core note sections for powerpc
transactional memory and one new ELF core note section for
powerpc general miscellaneous debug registers. These addition
. In case of mfspr instruction,
just emulate the instruction. In case of mtspr instruction, set the
thread based dscr_inherit bit and also enable the facility through FSCR.
All user SPR based mfspr instruction will be emulated till one user SPR
based mtspr has been executed.
Signed-off-by: Anshuman
.
efcac658: powerpc: Per process DSCR + some fixes (try#4)
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/kernel/process.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 923cd2d..73925a9
This patch adds some in-code documentation to the DSCR related
code to make it more readable without having any functional
change to it.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/processor.h | 8
arch/powerpc/kernel/sysfs.c | 13
PACA_DSCR offset macro tracks dscr_default element in the paca
structure. Better change the name of this macro to match that
of the data element it tracks. Makes the code more readable.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/kernel/asm-offsets.c | 2
.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
Documentation/powerpc/00-INDEX | 2 +
Documentation/powerpc/dscr.txt | 83 ++
2 files changed, 85 insertions(+)
create mode 100644 Documentation/powerpc/dscr.txt
diff --git a/Documentation
On 12/03/2014 12:18 PM, Anshuman Khandual wrote:
On 12/03/2014 10:52 AM, Michael Ellerman wrote:
On Tue, 2014-02-12 at 07:56:45 UTC, Anshuman Khandual wrote:
This patch adds four new ELF core note sections for powerpc
transactional memory and one new ELF core note section for
powerpc general
On 12/09/2014 03:33 PM, Michael Ellerman wrote:
On Mon, 2014-08-12 at 06:30:11 UTC, Anshuman Khandual wrote:
This patch adds some in-code documentation to the DSCR related
code to make it more readable without having any functional
change to it.
Adding documentation is always good
On 12/09/2014 03:41 PM, Michael Ellerman wrote:
On Mon, 2014-08-12 at 06:30:08 UTC, Anshuman Khandual wrote:
Currently DSCR (Data Stream Control Register) can be accessed with
mfspr or mtspr instructions inside a thread via two different SPR
numbers. One being the user accessible problem state
On 12/20/2014 12:58 AM, Edjunior Barbosa Machado wrote:
On 12/08/2014 08:08 AM, Anshuman Khandual wrote:
On 12/03/2014 12:18 PM, Anshuman Khandual wrote:
On 12/03/2014 10:52 AM, Michael Ellerman wrote:
On Tue, 2014-02-12 at 07:56:45 UTC, Anshuman Khandual wrote:
This patch adds four new ELF
On 01/13/2015 03:52 PM, Anshuman Khandual wrote:
This patch series has patches for POWER DSCR fixes, improvements,
in code documentaion, kernel support user documentation and selftest based
test cases. It has got five test cases which are derived from Anton's DSCR
test bucket which can
On 02/04/2015 01:51 PM, Anshuman Khandual wrote:
On 01/13/2015 03:52 PM, Anshuman Khandual wrote:
This patch series has patches for POWER DSCR fixes, improvements,
in code documentaion, kernel support user documentation and selftest based
test cases. It has got five test cases which
On 01/14/2015 07:45 AM, Michael Ellerman wrote:
On Tue, 2015-01-13 at 17:16 -0700, Shuah Khan wrote:
Please add a commit log.
What does it need to say?
On 01/13/2015 04:49 PM, Michael Ellerman wrote:
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
On 01/01/2015 01:38 PM, Anshuman Khandual wrote:
Also, we've noticed that the 'misc' regset contains registers from
different ISA
versions (dscr and ppr appear in ISA 2.05, tar is from 2.07). I'm not sure
if
there is a way to detect presence/validity of such registers, but perhaps
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