xisting "no_handler_test" test itself.
As per mpe's suggestion, moved that to a separate test
and removed the second call to "dump_ebb_state" since
that is actually not needed.
Athira Rajeev (2):
selftests/powerpc: Fix "no_handler" EBB selft
attempting to read PMU registers via helper function
"dump_ebb_state" for ISA v3.1.
Signed-off-by: Athira Rajeev
---
tools/testing/selftests/powerpc/pmu/ebb/Makefile | 2 +-
.../powerpc/pmu/ebb/regs_access_pmccext_test.c | 63 ++
2 files changed, 64 insertions(+),
as to dump the state of registers at the end of
the test when the counters are frozen. But this will be achieved
with the first call itself since sample period is set to low value
and PMU will be frozen by then. Hence patch removes the
dump which was done before closing of the event.
Signed-off-by: Ath
As per mpe's suggestion, moved that to a separate test
and removed the second call to "dump_ebb_state" since
that is actually not needed.
Athira Rajeev (2):
selftests/powerpc: Fix "no_handler" EBB selftest
selftests/powerpc: EBB selftest for MMC
ed rather
>> than replaying PMI before resetting overflown PMC. Patch also documents
>> core-book3s on a race condition which can trigger these PMC messages during
>> idle path in PowerNV.
>>
>> Fixes: f442d004806e ("powerpc/64s: Add support to
es the selftest to handle
the sigill for ISA v3.1.
Signed-off-by: Athira Rajeev
Reported-by: Shirisha Ganta
---
tools/testing/selftests/powerpc/pmu/ebb/no_handler_test.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/powerpc/pmu/ebb/no_handl
messages during
idle path in PowerNV.
Fixes: f442d004806e ("powerpc/64s: Add support to mask perf interrupts and
replay them")
Reported-by: Nageswara R Sastry
Suggested-by: Nicholas Piggin
Suggested-by: Madhavan Srinivasan
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/hw_irq.
review comments from Nicholas Piggin
- Moved the PMI pending check and clearing function
to arch/powerpc/include/asm/hw_irq.h and renamed
function to "get_clear_pmi_irq_pending"
- Along with checking for pending PMI bit in Paca,
look for PMAO bit in MMCR0 register to decide on
On 12-Apr-2021, at 12:49 PM, Athira Rajeev wrote:On 12-Apr-2021, at 8:38 AM, Nicholas Piggin wrote:Excerpts from Athira Rajeev's message of April 9, 2021 10:53 pm:On 09-Apr-2021, at 6:38 AM, Nicholas Piggin wrote:Hi Nick,Thanks for checking the patch and sharing review comments.I was going
han replaying PMI before resetting overflown PMC. Patch also documentscore-book3s on a race condition which can trigger these PMC messages duringidle path in PowerNV.Fixes: f442d004806e ("powerpc/64s: Add support to mask perf interrupts and replay them")Reported-by: Nageswara R Sastry Sugges
ase of power_pmu_del, also clear the MMCR0 PMAO bit which
>> otherwise could lead to spurious interrupts in some corner cases. Example,
>> a timer after power_pmu_del which will re-enable interrupts since PMI is
>> cleared and triggers a PMI again since PMAO bit is still set.
>>
&
> On 05-Mar-2021, at 11:20 AM, Athira Rajeev
> wrote:
>
>
>
>> On 24-Feb-2021, at 5:51 PM, Thadeu Lima de Souza Cascardo
>> wrote:
>>
>> EBB events must be under exclusive groups, so there is no mix of EBB and
>> non-EBB events on the same P
RUN_INST_CMPL: result 9872 running/enabled 37930432
success: cpu_event_pinned_vs_ebb
Fixes: 4df489991182 ("powerpc/perf: Add power8 EBB support")
Reported-by: Thadeu Lima de Souza Cascardo
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 4 ++--
1 file changed, 2 inse
so documents
core-book3s on a race condition which can trigger these PMC messages during
idle path in PowerNV.
Fixes: f442d004806e ("powerpc/64s: Add support to mask perf interrupts and
replay them")
Reported-by: Nageswara R Sastry
Suggested-by: Nicholas Piggin
Suggested-by: Madhavan Srinivasa
uot;Can't find PMC" messages.
This patch documents this race condition in powerpc core-book3s.
Patch fixes the ppmu callbacks to disable pending interrupt before clearing
the overflown PMC and documents the race condition in idle path.
Athira Rajeev (1):
powerpc/perf: Fix PMU callbacks to c
Hi,
Cover letter is missing in this patch. I will resent the patch along with cover
letter.
Sorry for the noise.
Thanks,
Athira
> On 06-Apr-2021, at 7:44 PM, Athira Rajeev wrote:
>
> Running perf fuzzer showed below in dmesg logs:
> "Can't find PMC that caused IRQ"
so documents
core-book3s on a race condition which can trigger these PMC messages during
idle path in PowerNV.
Fixes: f442d004806e ("powerpc/64s: Add support to mask perf interrupts and
replay them")
Reported-by: Nageswara R Sastry
Suggested-by: Nicholas Piggin
Suggested-by: Madhavan Srinivasa
g v2:
> -Fixed commit message
>
> Changelog v1:
> -Fixed commit message and in-code comments
Changes looks fine to me.
Reviewed-by: Athira Rajeev
Thanks,
Athira
>
> arch/powerpc/include/asm/perf_event_server.h | 6 ++
> arch/powerpc/perf/core-book3s.c | 14
On 25-Mar-2021, at 1:13 AM, Jiri Olsa wrote:On Mon, Mar 22, 2021 at 10:57:25AM -0400, Athira Rajeev wrote:Add arch specific arch_evsel__set_sample_weight() to set the newsample type for powerpc.Add arch specific arch_perf_parse_sample_weight() to store thesample->weight values depend
key incase it is not applicable for the particular arch.
Signed-off-by: Athira Rajeev
---
tools/perf/arch/powerpc/util/event.c | 7 +++
tools/perf/util/event.h | 1 +
tools/perf/util/sort.c | 19 +++
3 files changed, 27 insertions(+)
diff --git a/tools
4
Changelog:
Changes from v1 -> v2
Addressed Jiri's review comments:
- Display the new sort dimension 'p_stage_cyc' only
on supported architecture.
- Check for arch specific header string for matching
sort order in patch2.
Athira Rajeev (5):
powerpc/p
new sort function 'Pipeline Stage Cycle' and include this in
default_mem_sort_order[]. This new sort function may be used to denote
some other pipeline stage in another architecture. So add this to
list of sort entries that can have dynamic header string.
Signed-off-by: Athira Rajeev
---
tools
field.
if the sample type is PERF_SAMPLE_WEIGHT_STRUCT, memory subsystem
latency is stored in the low 32bits of perf_sample_weight structure.
Also for CPU_FTR_ARCH_31, capture the two cycle counter information in
two 16 bit fields of perf_sample_weight structure.
Signed-off-by: Athira Rajeev
not have this function, fall back to the
default header string value.
Signed-off-by: Athira Rajeev
---
tools/perf/util/event.h | 1 +
tools/perf/util/sort.c | 19 ++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h
wer 32 bits to sample->weight. If sample type
is 'PERF_SAMPLE_WEIGHT', store the full 64-bit to sample->weight.
Signed-off-by: Athira Rajeev
---
tools/perf/arch/powerpc/util/Build | 2 ++
tools/perf/arch/powerpc/util/event.c | 32
tools/perf/arch/pow
On 16-Mar-2021, at 4:48 AM, Jiri Olsa wrote:On Mon, Mar 15, 2021 at 01:22:09PM +0530, Athira Rajeev wrote:SNIP++static char *setup_dynamic_sort_keys(char *str)+{+ unsigned int j;++ if (sort__mode == SORT_MODE__MEMORY)+ for (j = 0; j < ARRAY_SIZE(dynamic_sort_keys_mem)
> On 12-Mar-2021, at 6:26 PM, Jiri Olsa wrote:
>
> On Tue, Mar 09, 2021 at 09:04:00AM -0500, Athira Rajeev wrote:
>> The pipeline stage cycles details can be recorded on powerpc from
>> the contents of Performance Monitor Unit (PMU) registers. On
>> ISA v3.1 p
> On 12-Mar-2021, at 6:27 PM, Jiri Olsa wrote:
>
> On Tue, Mar 09, 2021 at 09:03:58AM -0500, Athira Rajeev wrote:
>> Currently the header string for different columns in perf report
>> is fixed. Some fields of perf sample could have different meaning
>> for d
new sort function 'Pipeline Stage Cycle' and include this in
default_mem_sort_order[]. This new sort function may be used to denote
some other pipeline stage in another architecture. So add this to
list of sort entries that can have dynamic header string.
Signed-off-by: Athira Rajeev
---
tools
wer 32 bits to sample->weight. If sample type
is 'PERF_SAMPLE_WEIGHT', store the full 64-bit to sample->weight.
Signed-off-by: Athira Rajeev
---
tools/perf/arch/powerpc/util/Build | 2 ++
tools/perf/arch/powerpc/util/event.c | 32
tools/perf/arch/pow
do not have this function, fall back to the
default header string value.
Signed-off-by: Athira Rajeev
---
tools/perf/util/event.h | 1 +
tools/perf/util/sort.c | 19 ++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/event.h b/tools/perf/util
field.
if the sample type is PERF_SAMPLE_WEIGHT_STRUCT, memory subsystem
latency is stored in the low 32bits of perf_sample_weight structure.
Also for CPU_FTR_ARCH_31, capture the two cycle counter information in
two 16 bit fields of perf_sample_weight structure.
Signed-off-by: Athira Rajeev
hit[k]
perf_event_exec [kernel.vmlinux] [k] 0xc007ffdd3288
[unknown] N/A N/A
No N/A7 4
Athira Rajeev (4):
powerpc/perf: Expose processor pipeline
> On 24-Feb-2021, at 5:51 PM, Thadeu Lima de Souza Cascardo
> wrote:
>
> EBB events must be under exclusive groups, so there is no mix of EBB and
> non-EBB events on the same PMU. This requirement worked fine as perf core
> would not allow other pinned events to be scheduled together with
for
CPU_FTR_ARCH_31.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 30 +++---
arch/powerpc/perf/isa207-common.h | 1 +
2 files changed, 28 insertions(+), 3 deletion
: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-events-list.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/power10-events-list.h
b/arch/powerpc/perf/power10-eve
the PVR directly.
>
> Suggested-by: Michael Ellerman
> Signed-off-by: Rashmica Gupta
> Reviewed-by: Madhavan Srinivasan
> [chleroy: Added power10 and fixed checkpatch issues]
> Signed-off-by: Christophe Leroy
Reviewed-and-tested-by: Athira Rajeev mailto:atraj...@linux.vnet.ibm.c
On 26-Feb-2021, at 2:28 PM, Srikar Dronamraju wrote:* Athira Rajeev [2021-02-25 11:50:02]:In systems having higher node numbers available like node255, perf numa bench will fail with SIGABORT.<<>>perf: bench/numa.c:1416: init: Assertion `!(g->p.nr_nodes > 64 || g->p.nr_nodes
> On 26-Feb-2021, at 3:05 PM, Peter Zijlstra wrote:
>
> On Thu, Feb 25, 2021 at 05:10:39AM -0500, Athira Rajeev wrote:
>> diff --git a/arch/powerpc/perf/core-book3s.c
>> b/arch/powerpc/perf/core-book3s.c
>> index 4b4319d8..c8be44c 100644
>> --- a/arch/powerpc
s a fix to dynamically allocate size for the
two arrays and bitmask value based on the node numbers available in the
system. With the fix, perf numa benchmark will work with node configuration
on any system and thus removes the static MAX_NR_NODES value.
Signed-off-by: Athira Rajee
l address leak to
userspace via BHRB buffer")
We only allow creation of events that has already passed the privilege
checks in perf_event_open. So these paranoid checks are not needed at
event time. As a fix, patch uses 'event->attr.exclude_kernel' check
to prevent exposing kernel address for us
> On 23-Feb-2021, at 6:24 PM, Michael Ellerman wrote:
>
> Peter Zijlstra writes:
>> On Tue, Feb 23, 2021 at 01:31:49AM -0500, Athira Rajeev wrote:
>>> Running "perf mem record" in powerpc platforms with selinux enabled
>>> resulted in soft lock
025 ("powerpc/perf: Prevent kernel address leak to
userspace via BHRB buffer")
As a fix, patch caches 'perf_allow_kernel' value in event_init in
'pmu_private' field of perf_event. The cached value is used in the
PMI code path.
Suggested-by: Michael Ellerman
Signed-off-by: Athira Rajeev
> On 09-Feb-2021, at 6:17 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Wed, Feb 03, 2021 at 12:31:48PM -0300, Arnaldo Carvalho de Melo escreveu:
>> Em Tue, Feb 02, 2021 at 04:02:36PM +0530, Athira Rajeev escreveu:
>>>
>>>
>>>On
-by: Athira Rajeev
---
Changes in v2:
-- Changed the approach to include PERF_SAMPLE_IP
condition while checking siar_valid as Suggested by
Michael Ellerman.
arch/powerpc/perf/core-book3s.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf
> On 04-Feb-2021, at 8:25 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> While sampling for marked events, currently we record the sample only
>> if the SIAR valid bit of Sampled Instruction Event Register (SIER) is
>> set. SIAR_VALID bit is used f
> On 03-Feb-2021, at 9:55 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Wed, Feb 03, 2021 at 01:55:37AM -0500, Athira Rajeev escreveu:
>> To enable presenting of Performance Monitor Counter Registers
>> (PMC1 to PMC6) as part of extended regsiters, patch adds these
> On 03-Feb-2021, at 9:01 PM, Arnaldo Carvalho de Melo wrote:
>
> Thanks, collected the Tested-by from Kajol and the Acked-by from Jiri
> and applied to my local tree for testing, then up to my perf/core
> branch.
>
> - Arnaldo
Thanks Arnaldo for taking this fix.
sample_period.
Perf event attribute will not have PERF_SAMPLE_IP set in the
sample_type if exact IP of the overflow event is not requested. So
while profiling if SAMPLE_IP is not set, just record the counter overflow
irrespective of SIAR_VALID check.
Signed-off-by: Athira Rajeev
---
arch/powerpc
extended mask value for
CPU_FTR_ARCH_300.
Signed-off-by: Athira Rajeev
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 28 +++--
tools/perf/arch/powerpc/include/perf_regs.h | 6 ++
tools/perf/arch/powerpc/util/perf_regs.c| 6 ++
3 files changed, 34
.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event.h | 2 ++
arch/powerpc/include/uapi/asm/perf_regs.h | 28 ++--
arch/powerpc/perf/core-book3s.c | 11 +++
arch/powerpc/perf/perf_regs.c | 13 -
4 files changed, 39
' will be capturing the modified value.
To solve this, add a per-cpu array as part of structure cpu_hw_events
and use this array to capture PMC values in the perf interrupt handler.
Patch also re-factor's the interrupt handler code to use this per-cpu
array instead of current local array.
Signed-off-by: Athira
to PMC6 to sample_reg_mask to use with -I? option.
Athira Rajeev (3):
powerpc/perf: Include PMCs as part of per-cpu cpuhw_events struct
powerpc/perf: Expose Performance Monitor Counter SPR's as part of
extended regs
tools/perf: Add perf tools support to expose Performance Monitor
Counter
On 18-Jan-2021, at 3:51 PM, kajoljain wrote:On 1/12/21 3:08 PM, Jiri Olsa wrote:On Mon, Dec 28, 2020 at 09:14:14PM -0500, Athira Rajeev wrote:SNIPc2799370 b backtrace_flagc2799378 B radix_tree_node_cachepc2799380 B __bss_stopc27a B _endc0080389 t
and if there is no permission
to monitor qemu threads, we return permission denied ( EACCES ).
Fix this by returning EACCES only if there is no CAP_SYS_ADMIN and the
event doesn’t have inheritance.
Fixes: 012ae244845f ("powerpc/perf: Trace imc PMU functions")
Signed-off-by: Ath
ace logs:<<>>replay_soft_interrupts <-arch_local_irq_restoreirq_enter <-performance_monitor_exception_asyncirq_enter_rcu <-performance_monitor_exception_asyncdummy_perf <-performance_monitor_exception_asyncirq_exit <-performance_monitor_exception_async<<>>Reviewe
On 20-Jan-2021, at 8:39 AM, Nicholas Piggin wrote:Excerpts from Athira Rajeev's message of January 19, 2021 8:24 pm:On 15-Jan-2021, at 10:19 PM, Nicholas Piggin wrote:This is required in order to allow more significant differences betweenNMI type interrupt handlers and regular asynchronous
sy_wait(delay); trace_printk("IN IRQ TEST DONE\n"); local_irq_restore(flags); mtspr(SPRN_MMCR0, 0x8000); mtspr(SPRN_PMC6, 0);}<<>>With the patch, there is no soft lockup’s.Tested-by: Athira Rajeev ---arch/powerpc/kernel/irq.c | 14 ++1 file changed, 14 insertio
> On 15-Jan-2021, at 10:19 PM, Nicholas Piggin wrote:
>
> This is required in order to allow more significant differences between
> NMI type interrupt handlers and regular asynchronous handlers.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/kernel/traps.c | 31
> On 12-Jan-2021, at 3:08 PM, Jiri Olsa wrote:
>
> On Mon, Dec 28, 2020 at 09:14:14PM -0500, Athira Rajeev wrote:
>
> SNIP
>
>> c2799370 b backtrace_flag
>> c2799378 B radix_tree_node_cachep
>> c2799380 B __bss_stop
>> c00
g calloc fails.
Fix this by detecting the kernel's last symbol and limiting
the range of last kernel symbol to pagesize.
Signed-off-by: Athira Rajeev
---
tools/perf/arch/powerpc/util/Build | 1 +
tools/perf/arch/powerpc/util/machine.c | 24
2 files changed, 25
On 28-Nov-2020, at 8:10 PM, Nicholas Piggin wrote:This is required in order to allow more significant differences betweenNMI type interrupt handlers and regular asynchronous handlers.Signed-off-by: Nicholas Piggin Reviewed this patch and the changes looks good to me.Reviewed-by: Athira Rajeev
Srinivasan
Signed-off-by: Athira Rajeev
---
Changelog v2 -> v3:
- Since in POWER10 it's actually 8 bits which will hopefully be
fixed in ISA3.1 update, bring back the cpu feature check which
is the appropriate one.
Changelog v1 -> v2:
- Fixed the commit message
- Fixed the condition check to u
and checking the backtrace when timer_interrupt
was hit.
Reported-by: Sebastian Andrzej Siewior
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core
updates to event codes
can be made in the original list, ie, power10_events_attr. Update the
power10 pmu init code to pick the dd1 list while registering
the power PMU, based on the pvr (Processor Version Register) value.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-pmu.c | 152
boot and during the PMU event enable/disable callback
functions.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/reg.h| 1 +
arch/powerpc/kernel/cpu_setup_power.c | 1 +
arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
arch/powerpc/perf/core-book3s.c | 4
arch/powerpc
Export l2l3 events (PM_L2_ST_MISS and PM_L2_ST) and LLC-prefetches
(PM_L3_PF_MISS_L3) via sysfs, and also add these to list of
cache_events.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-events-list.h | 6 ++
arch/powerpc/perf/power10-pmu.c | 12 +---
2 files
Fix the event code for events: branch-instructions (to PM_BR_FIN),
branch-misses (to PM_MPRED_BR_FIN) and cache-misses (to
PM_LD_DEMAND_MISS_L1_FIN) for power10 PMU. Update the
list of generic events with this modified event code.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10
/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 7 ++-
arch/powerpc/perf/isa207-common.h | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/isa207-common.c
b/arch/powerpc/perf/isa20
lit Patch 3 also to address event code updates
separately for generic and cache events.
Fixed commit messages and also PMCCEXT bit setting
during event enable.
Athira Rajeev (7):
powerpc/perf: Fix to update radix_scope_qual in power10
powerpc/perf: Update the PMU group constraints for l
patch handles
group constrints checks for l2/l3 bits in MMCR2.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/p
the radix_scope_qual bit.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 12
arch/powerpc/perf/isa207-common.h | 13 ++---
arch/powerpc/perf/power10-pmu.c | 11 +++
3 files c
) locks on to kernel address even when
freeze on supervisor is set. Patch here adds a check to
drop those samples.
Signed-off-by: Athira Rajeev
---
Changes in v2:
- Initial patch was sent along with series:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=209195
Moving this patch
b7a ("powerpc/perf: Update perf_regs structure to include SIER")
Reported-by: Sachin Sant
Signed-off-by: Athira Rajeev
---
Changes in v2:
- Corrected the commit message as suggested by
Michael Ellerman.
arch/powerpc/perf/core-book3s.c | 3 +++
1 file changed, 3 insertions(+)
diff --
> On 11-Nov-2020, at 3:13 PM, Nicholas Piggin wrote:
>
> This is required in order to allow more significant differences between
> NMI type interrupt handlers and regular asynchronous handlers.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/kernel/traps.c | 31
> On 23-Nov-2020, at 4:49 PM, Michael Ellerman wrote:
>
> Hi Athira,
>
> Athira Rajeev writes:
>> On systems without any platform specific PMU driver support registered or
>> Generic Compat PMU support registered,
>
> The compat PMU is registered just like
turning false in
'is_sier_available()' if 'ppmu' is not set.
Fixes: 333804dc3b7a ("powerpc/perf: Update perf_regs structure to include SIER")
Reported-by: Sachin Sant
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/power
> On 18-Nov-2020, at 10:06 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> Fix the event code for events: branch-instructions (to PM_BR_FIN),
>> branch-misses (to PM_BR_MPRED_FIN) and cache-misses (to
>> PM_LD_DEMAND_MISS_L1_FIN) for power10 PMU. Update th
> On 18-Nov-2020, at 10:02 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> In Power9, L2/L3 bus events are always available as a
>> "bank" of 4 events. To obtain the counts for any of the
>> l2/l3 bus events in a given bank, the user will have
patch handles
group constrints checks for l2/l3 bits in MMCR2.
Patch also updates constraints for threshold events in power10.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 15 +++
, based on the pvr
(Processor Version Register) value.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-events-list.h | 9 ++
arch/powerpc/perf/power10-pmu.c | 166 +++-
2 files changed, 173 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf
the radix_scope_qual bit.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 12
arch/powerpc/perf/isa207-common.h | 13 ++---
arch/powerpc/perf/power10-pmu.c | 11 +++
3 files c
=0b00
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/reg.h| 1 +
arch/powerpc/kernel/cpu_setup_power.S | 2 ++
arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
arch/powerpc/perf/core-book3s.c | 16
4 files changed, 20 insertions(+)
diff --git a/arch
and
some of the generic events.
Patch4 adds fixes for PMCCEXT bit in power10.
Athira Rajeev (4):
powerpc/perf: Fix to update radix_scope_qual in power10
powerpc/perf: Update the PMU group constraints for l2l3 and threshold
events in power10
powerpc/perf: Fix to update l2l3 events
). Patch adds a check to drop
these samples at such conditions.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index c018004..10a2d1f 100644
--- a/arch
is set.
So add a condition check for power10 DD1 to use SIER[CMPL] bit
instead.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index
. Hence add a check to use the address in Sampled Instruction Address
Register (SIAR) to identify the privilege level.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc
Add a new power PMU flag "PPMU_P10_DD1" which can be
used to conditionally add any code path for power10 DD1 processor
version. Also modify power10 PMU driver code to set this
flag only for DD1, based on the Processor Version Register (PVR)
value.
Signed-off-by: Athira Rajeev
---
ar
userspace profiling.
Athira Rajeev (4):
powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1
powerpc/perf: Using SIER[CMPL] instead of SIER[SIAR_VALID]
powerpc/perf: Use the address from SIAR register to set cpumode flags
powerpc/perf: Exclude kernel samples whil
bol 'p9_dd21_bl_ev'
> was not declared. Should it be static?
> arch/powerpc/perf/power9-pmu.c:115:5: warning: symbol 'p9_dd22_bl_ev'
> was not declared. Should it be static?
>
> Those symbols are used only in the files that define them so we declare
> them as static to fix the warnings.
Hi,
Loo
> On 22-Sep-2020, at 4:16 PM, Paul A. Clarke wrote:
>
> Just one nit in a comment below...
> (and this is not worthy of tags like "reviewed-by" ;-)
>
> On Mon, Sep 21, 2020 at 03:10:04AM -0400, Athira Rajeev wrote:
>> PMU counter support functions en
> On 21-Sep-2020, at 4:55 PM, Wang Wensheng wrote:
>
> Build kernel with `C=2`:
> arch/powerpc/perf/isa207-common.c:24:18: warning: symbol
> 'isa207_pmu_format_attr' was not declared. Should it be static?
> arch/powerpc/perf/power9-pmu.c:101:5: warning: symbol 'p9_dd21_bl_ev'
> was not
: 7ffd948 ("powerpc/perf: factor out power8 pmu functions")
Signed-off-by: Athira Rajeev
---
Changes in v2:
- Added a block comment in the fix path explaining
why the change is needed.
arch/powerpc/perf/isa207-common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/ar
> On 17-Sep-2020, at 5:43 PM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> PMU counter support functions enforces event constraints for group of
>> events to check if all events in a group can be monitored. Incase of
>> event codes using PMC5 and PMC6 ( 5
ent_init(struct perf_event
> *event)
> mutex_unlock(_global_refc.lock);
>
> event->hw.idx = -1;
> - target = event->hw.target;
Reviewed-by: Athira Rajeev
Thanks
Athira
>
> event->pmu->task_ctx_nr = perf_hw_context;
> event->destroy = reset_global_refc;
> --
> 2.25.4
>
: 7ffd948 ('powerpc/perf: factor out power8 pmu functions')
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/perf/isa207-common.c
b/arch/powerpc/perf/isa207-common.c
index 964437a..186fad8 100644
--- a/arch
;)
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/imc-pmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
index a45d694..62d0b54 100644
--- a/arch/powerpc/perf/imc-pmu.c
+++ b/arch/powerpc/perf/imc-pmu.c
@@ -1
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
Reviewed
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
Reviewed-by: Kajol Jain
Reviewed-and-tested-by: Ravi Bangoria
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools
from Ravi Bangoria to initialize
`perf_reg_extended_max`
and define it in lowercase since it is local variable.
Anju T Sudhakar (1):
tools/perf: Add perf tools support for extended register capability in
powerpc
Athira Rajeev (1):
tools/perf: Add perf tools support for extended regs i
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