mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
[Fix build issue using
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
d support for outputting extended regs in perf
intr_regs
Athira Rajeev (1):
powerpc/perf: Add extended regs support for power10 platform
arch/powerpc/include/asm/perf_event.h| 3 ++
arch/powerpc/include/asm/perf_event_server.h | 5
arch/powerpc/include/uapi/asm/perf_regs.
> On 06-Aug-2020, at 5:50 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Fri, Jul 31, 2020 at 11:04:14PM +0530, Athira Rajeev escreveu:
>>
>>
>>> On 31-Jul-2020, at 1:20 AM, Jiri Olsa wrote:
>>>
>>> On Thu, Jul 30, 2020 at 01:24:40PM +0530,
is more than max_samples_per_tick. This leads to soft lockup.
Fix this by adding perf_event_account_interrupt in the invalid siar
code path for a sampling event. ie if siar is invalid, just do interrupt
check and don't record the sample information.
Signed-off-by: Athira Rajeev
Reported-by: Alexey
> On 31-Jul-2020, at 1:20 AM, Jiri Olsa wrote:
>
> On Thu, Jul 30, 2020 at 01:24:40PM +0530, Athira Rajeev wrote:
>>
>>
>>> On 27-Jul-2020, at 10:46 PM, Athira Rajeev
>>> wrote:
>>>
>>> Patch set to add support for perf extende
> On 27-Jul-2020, at 10:46 PM, Athira Rajeev
> wrote:
>
> Patch set to add support for perf extended register capability in
> powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to
> indicate the PMU which support extended registers. The generic code
> On 28-Jul-2020, at 6:14 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>>> On 27-Jul-2020, at 6:05 PM, Michael Ellerman wrote:
>>>
>>> Athira Rajeev writes:
>>>>> On 27-Jul-2020, at 11:39 AM, Nicholas Piggin wrote:
>>&g
DT CPU features")
Signed-off-by: Athira Rajeev
Suggested-by: Michael Ellerman
---
arch/powerpc/include/asm/reg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index ae71027..41419f1 100644
--- a/arch/power
> On 27-Jul-2020, at 6:05 PM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>>> On 27-Jul-2020, at 11:39 AM, Nicholas Piggin wrote:
>>>
>>> Commit 2f92447f9f96 ("powerpc/book3s64/hash: Use the pte_t address from the
>>> caller
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
Reviewed
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
Reviewed-by: Kajol Jain
Reviewed-and-tested-by: Ravi Bangoria
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
[Fix build issue using
r_regs
tools/perf: Add perf tools support for extended register capability in
powerpc
Athira Rajeev (2):
powerpc/perf: Add extended regs support for power10 platform
tools/perf: Add perf tools support for extended regs in power10
arch/powerpc/include/asm/perf_event.h | 3 ++
037f024 wp_page_copy+0x364/0xce0
> [c0002ac1cc69bc20] c038272c do_wp_page+0xdc/0xa60
> [c0002ac1cc69bc70] c03857bc handle_mm_fault+0xb9c/0x1b60
> [c0002ac1cc69bd50] c006c434 __do_page_fault+0x314/0xc90
> [c0002ac1cc69be20] c000c5c8 handle_page_faul
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
Reviewed
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
Reviewed-by: Kajol Jain
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools/perf/arch/powerpc/util/header.c
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
[Fix build issue using
ine it in lowercase since it is local variable.
Anju T Sudhakar (2):
powerpc/perf: Add support for outputting extended regs in perf
intr_regs
tools/perf: Add perf tools support for extended register capability in
powerpc
Athira Rajeev (2):
powerpc/perf: Add extended regs support for power10 platf
ain random value which
> will
> allow user to pass this if condition unintentionally.
>
> Neat: PERF_REG_EXTENDED_MAX is a local variable so it should be in lowercase.
> Any specific reason to define it in capital?
Hi Ravi
There is no specific reason. I will include both these changes in next version
Thanks
Athira Rajeev
>
> Ravi
> On 24-Jul-2020, at 4:32 PM, Ravi Bangoria wrote:
>
> Hi Athira,
>
> On 7/17/20 8:08 PM, Athira Rajeev wrote:
>> From: Anju T Sudhakar
>> Add extended regs to sample_reg_mask in the tool side to use
>> with `-I?` option. Perf tools side uses extende
> On 23-Jul-2020, at 8:26 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Thu, Jul 23, 2020 at 11:14:16AM +0530, kajoljain escreveu:
>>
>>
>> On 7/21/20 11:32 AM, kajoljain wrote:
>>>
>>>
>>> On 7/17/20 8:08 PM, Athira Rajeev wrote:
>&
wood/next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Athira-Rajeev/powerpc-perf-
t;> the above relies on preempt_count() already having been incremented with
>>> NMI_MASK.
>>
>> Hmm. My patch seems simpler.
>
> And your patches fix my error while Peter's do not:
>
>
> IRQs not enabled as expected
> WARNING: CPU: 0 PID: 1377 at /home/aik/p/
re at boot for power10.
Signed-off-by: Athira Rajeev
---
Dependency:
- On power10 PMU base enablement series V3:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=190462
Changes from v3 -> v4
- Addressed review comments from Jordan and Michael Ellerman.
This patch was initially part o
> On 22-Jul-2020, at 4:19 PM, Jordan Niethe wrote:
>
> On Wed, Jul 22, 2020 at 5:55 PM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>>
>>
>> On 22-Jul-2020, at 10:11 AM, Jordan Niethe wrote:
>>
>> On Sat, Jul 18, 20
> On 22-Jul-2020, at 9:48 AM, Jordan Niethe wrote:
>
> On Sat, Jul 18, 2020 at 1:02 AM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>> From: Madhavan Srinivasan
>>
>> PowerISA v3.1 includes new performance monitoring un
> On 22-Jul-2020, at 10:11 AM, Jordan Niethe wrote:
>
> On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>> From: Madhavan Srinivasan
>>
>> Add power10 feature function to dt_cpu_ftrs.c along
>>
> On 22-Jul-2020, at 10:07 AM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>>> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote:
>>> On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote:
>>>&
> On 21-Jul-2020, at 9:12 AM, Jordan Niethe wrote:
>
> On Sat, Jul 18, 2020 at 12:48 AM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>> core-book3s currently uses array to store the MMCR registers as part
>> of per-cpu `cpu_hw_events
> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote:
>
> On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote:
>> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers
>> in a flat array in order: mmcr0, mmcr1, mmcra, mmcr2, mmcrs
>> Split this
the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Athira-Rajeev/powerpc-perf-Add-support-for-power10-PM
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools/perf/arch/powerpc/util/header.c | 9 +
tools
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
---
tools
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
arch/powerpc/include/asm
ot enabled on request at runtime.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 20
arch/powerpc/perf/isa207-common.c | 12
arch/powerpc/platforms/powernv/idle.c | 22 --
3 files changed, 48 insertions(+), 6
PowerISA v3.1 introduce filtering support for
PERF_SAMPLE_BRANCH_IND_CALL/COND. The patch adds BHRB filter
support for "ind_call" and "cond" in power10_bhrb_filter_map().
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-pmu.c | 13 +++--
1 file changed,
MSR[PR]=1 address to be written to BHRB buffer.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 0ffb757d..bd125fe 100644
--- a/arch/powerpc
the support function in isa207_common.c to
include power10 pmu hardware.
[Enablement of base PMU driver code]
Signed-off-by: Madhavan Srinivasan
[Addition of ISA macros for counter support functions]
Signed-off-by: Athira Rajeev
[Fix compilation warning for missing prototype for init_power10_pmu
From: Madhavan Srinivasan
Add power10 feature function to dt_cpu_ftrs.c along
with a power10 specific init() to initialize pmu sprs,
sets the oprofile_cpu_type and cpu_features. This will
enable performance monitoring unit(PMU) for Power10
in CPU features with "performance-monitor-power10".
For
From: Madhavan Srinivasan
PowerISA v3.1 added three new perfromance
monitoring unit (PMU) speical purpose register (SPR).
They are Monitor Mode Control Register 3 (MMCR3),
Sampled Instruction Event Register 2 (SIER2),
Sampled Instruction Event Register 3 (SIER3).
Patch here adds a new dump
entering/exiting guest. Also includes
changes to support KVM_REG_PPC_MMCR3/SIER2/SIER3.
And adds new SPRs to KVM API documentation.
Signed-off-by: Athira Rajeev
---
Documentation/virt/kvm/api.rst| 3 +++
arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +-
arch/powerpc/include/asm
From: Madhavan Srinivasan
PowerISA v3.1 includes new performance monitoring unit(PMU)
special purpose registers (SPRs). They are
Monitor Mode Control Register 3 (MMCR3)
Sampled Instruction Event Register 2 (SIER2)
Sampled Instruction Event Register 3 (SIER3)
MMCR3 is added for further sampling
nts.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 2 +-
arch/powerpc/perf/generic-compat-pmu.c | 2 +-
arch/powerpc/perf/mpc7450-pmu.c | 2 +-
arch/powerpc/perf/power5+-pmu.c | 2 +-
a
.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/kvm_host.h | 4 +++-
arch/powerpc/include/uapi/asm/kvm.h | 4 ++--
arch/powerpc/kernel/asm-offsets.c | 2 ++
arch/powerpc/kvm/book3s_hv.c | 16 ++--
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 12
registers are added. Patch updates all relevant code that was
using MMCR array ( cpuhw->mmcr[x]) to use newly introduced `struct`.
This includes the PMU driver code for supported platforms (power5
to power9) and ISA macros for counter support functions.
Signed-off-by: Athira Rajeev
---
arch/powe
register capability in
powerpc
Athira Rajeev (10):
powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR
registers
KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR
powerpc/perf: Update Power PMU cache_events to u64 type
KVM: PPC: Book3S HV: Save/restore new PMU
> On 14-Jul-2020, at 11:38 AM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>>> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote:
>>>
>>> Hi Athira,
>>>
>>> Athira Rajeev writes:
&g
> On 13-Jul-2020, at 6:20 PM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>>> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote:
>>>
>>> Athira Rajeev writes:
>>> ...
>>>> diff
> On 08-Jul-2020, at 5:34 PM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>> From: Anju T Sudhakar
>>
>> Add extended regs to sample_reg_mask in the tool side to use
>> with `-I?` option. Per
> On 08-Jul-2020, at 4:45 PM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>> From: Madhavan Srinivasan
>>
>> Add power10 feature function to dt_cpu_ftrs.c along
>> with a power10 specific init()
> On 08-Jul-2020, at 5:34 PM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>> Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
>> and expose MMCR3, SIER2, SIER3 registers as part of ex
> On 08-Jul-2020, at 5:34 PM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>> From: Anju T Sudhakar
>>
>> Add extended regs to sample_reg_mask in the tool side to use
>> with `-I?` option. Per
> On 08-Jul-2020, at 5:12 PM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>
>> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB).
> ^
> a
>> Fi
> On 08-Jul-2020, at 1:13 PM, Gautham R Shenoy wrote:
>
> On Tue, Jul 07, 2020 at 05:17:55PM +1000, Michael Neuling wrote:
>> On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote:
>>> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB).
>>&
> On 08-Jul-2020, at 4:34 PM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>> From: Madhavan Srinivasan
>>
>> PowerISA v3.1 added three new perfromance
>> monitoring unit (PMU) speical purpose regist
> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
> ...
>> diff --git a/arch/powerpc/perf/core-book3s.c
>> b/arch/powerpc/perf/core-book3s.c
>> index cd6a742..5c64bd3 100644
>> --- a/arch/powerpc/perf/core-book3s.c
>
> On 07-Jul-2020, at 12:47 PM, Michael Neuling wrote:
>
> On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote:
>> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB).
>> First is the addition of BHRB disable bit and second new filtering
>>
> On 07-Jul-2020, at 12:20 PM, Michael Neuling wrote:
>
>
>> @@ -480,6 +520,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
>> mmcr[1] = mmcr1;
>> mmcr[2] = mmcra;
>> mmcr[3] = mmcr2;
>> +mmcr[4] = mmcr3;
>
> This is fragile like the kvm vcpu case I commented on
> On 07-Jul-2020, at 11:52 AM, Michael Neuling wrote:
>
> On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote:
>> From: Madhavan Srinivasan
>>
>> Add power10 feature function to dt_cpu_ftrs.c along
>> with a power10 specific init() to initialize pmu
plied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Athira-Rajeev/powerpc-perf-Add-support-for-power10-PMU-Hardware/202007
> On 01-Jul-2020, at 4:41 PM, Paul Mackerras wrote:
>
> On Wed, Jul 01, 2020 at 05:20:54AM -0400, Athira Rajeev wrote:
>> PowerISA v3.1 has added new performance monitoring unit (PMU)
>> special purpose registers (SPRs). They are
>>
>> Monitor Mode Cont
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/uapi/asm
sample. Hence decide the mask value based on the processor
version.
Signed-off-by: Anju T Sudhakar
[Decide extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
arch/powerpc/include/asm
processors, since PowerISA v3.1
allows
only MSR[PR]=1 address to be written to BHRB buffer.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 27 +--
arch/powerpc/perf/isa207-common.c | 13 +
arch/powerpc/perf/power10-pmu.c |
nts.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 2 +-
arch/powerpc/perf/generic-compat-pmu.c | 2 +-
arch/powerpc/perf/mpc7450-pmu.c | 2 +-
arch/powerpc/perf/power5+-pmu.c | 2 +-
a
the support function in isa207_common.c to
include power10 pmu hardware.
[Enablement of base PMU driver code]
Signed-off-by: Madhavan Srinivasan
[Addition of ISA macros for counter support functions]
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc
From: Madhavan Srinivasan
Add power10 feature function to dt_cpu_ftrs.c along
with a power10 specific init() to initialize pmu sprs.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/reg.h| 3 +++
arch/powerpc/kernel/cpu_setup_power.S | 7 +++
From: Madhavan Srinivasan
PowerISA v3.1 added three new perfromance
monitoring unit (PMU) speical purpose register (SPR).
They are Monitor Mode Control Register 3 (MMCR3),
Sampled Instruction Event Register 2 (SIER2),
Sampled Instruction Event Register 3 (SIER3).
Patch here adds a new dump
entering/exiting guest.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +-
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kernel/asm-offsets.c | 3 +++
arch/powerpc/kvm/book3s_hv.c | 6 --
arch/powerpc/kvm
From: Madhavan Srinivasan
PowerISA v3.1 includes new performance monitoring unit(PMU)
special purpose registers (SPRs). They are
Monitor Mode Control Register 3 (MMCR3)
Sampled Instruction Event Register 2 (SIER2)
Sampled Instruction Event Register 3 (SIER3)
MMCR3 is added for further sampling
The patch series adds support for power10 PMU hardware.
Anju T Sudhakar (2):
powerpc/perf: Add support for outputting extended regs in perf
intr_regs
tools/perf: Add perf tools support for extended register capability in
powerpc
Athira Rajeev (5):
KVM: PPC: Book3S HV: Save/restore
processors, since PowerISA v3.1
allows
only MSR[PR]=1 address to be written to BHRB buffer.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 27 +--
arch/powerpc/perf/isa207-common.c | 13 +
arch/powerpc/perf/power10-pmu.c |
the support function in isa207_common.c to
include power10 pmu hardware.
[Enablement of base PMU driver code]
Signed-off-by: Madhavan Srinivasan
[Addition of ISA macros for counter support functions]
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc
nts.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 2 +-
arch/powerpc/perf/generic-compat-pmu.c | 2 +-
arch/powerpc/perf/mpc7450-pmu.c | 2 +-
arch/powerpc/perf/power5+-pmu.c | 2 +-
a
From: Madhavan Srinivasan
Add power10 feature function to dt_cpu_ftrs.c along
with a power10 specific init() to initialize pmu sprs.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/reg.h| 3 +++
arch/powerpc/kernel/cpu_setup_power.S | 7 +++
entering/exiting guest.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +-
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kernel/asm-offsets.c | 3 +++
arch/powerpc/kvm/book3s_hv.c | 6 --
arch/powerpc/kvm
From: Madhavan Srinivasan
PowerISA v3.1 added three new perfromance
monitoring unit (PMU) speical purpose register (SPR).
They are Monitor Mode Control Register 3 (MMCR3),
Sampled Instruction Event Register 2 (SIER2),
Sampled Instruction Event Register 3 (SIER3).
Patch here adds a new dump
From: Madhavan Srinivasan
PowerISA v3.1 includes new performance monitoring unit(PMU)
special purpose registers (SPRs). They are
Monitor Mode Control Register 3 (MMCR3)
Sampled Instruction Event Register 2 (SIER2)
Sampled Instruction Event Register 3 (SIER3)
MMCR3 is added for further sampling
The patch series adds support for power10 PMU hardware.
And code changes are based on powerpc/next.
Athira Rajeev (4):
KVM: PPC: Book3S HV: Save/restore new PMU registers
powerpc/perf: Update Power PMU cache_events to u64 type
powerpc/perf: power10 Performance Monitoring support
powerpc
sample. Hence decide the mask value based on the processor
version.
Signed-off-by: Anju T Sudhakar
[Decide extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
arch/powerpc/include/asm
Patch set to add support for perf extended register capability in
powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to
indicate the PMU which support extended registers. The generic code
define the mask of extended registers as 0 for non supported architectures.
patch 1/2 defines
sample. Hence decide the mask value based on the processor
version.
Signed-off-by: Anju T Sudhakar
[Decide extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event_server.h | 8 +++
arch
Patch set to add support for perf extended register capability in
powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to
indicate the PMU which support extended registers. The generic code
define the mask of extended registers as 0 for non supported architectures.
patch 1/2 defines
0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
---
Changes from v1 -> v2
- PERF_REG_EXTENDED_MASK` is defined at runtime in the kernel
based on platf
> On 06-May-2020, at 9:56 AM, Madhavan Srinivasan wrote:
>
>
>
> On 4/29/20 11:34 AM, Anju T Sudhakar wrote:
>> The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the
>> PMU which support extended registers. The generic code define the mask
>> of extended registers as 0 for
e VPA
flag "pmcregs_in_use". "pmcregs_in_use" flag is set in
"power_pmu_enable" via ppc_set_pmu_inuse(1) and it is unset
when there are no active events (n_events == 0 condition).
Patch here adds documentation on the ppc_set_pmu_inuse() usage.
Signed-off-by: Madhavan
Hi,
Please ignore this version as I messed up with the author information. I am
sending a V2 with the proper author name.
Thanks
Athira
> On 30-Mar-2020, at 5:08 PM, Athira Rajeev wrote:
>
> "pmcregs_in_use" flag is part of lppaca (Virtual Process Area),
> which is us
ot;. "pmcregs_in_use" flag is set in
"power_pmu_enable" via ppc_set_pmu_inuse(1) and it is unset
when there are no active events (n_events == 0 condition).
Patch here adds documentation on the ppc_set_pmu_inuse() usage.
Signed-off-by: Madhavan Srinivasan
Signed-off-by: At
> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote:
>
> Hi Athira,
>
> Athira Rajeev writes:
>> Sampled Instruction Event Register (SIE
rently all of the bits from SIER are saved for EBB events. Patch fixes
this by ANDing the "sier_user_mask" to data from SIER in ebb_switch_out().
This will force save only architected bits from the SIER.
Fixes: 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s"
> On 13-Mar-2020, at 11:36 PM, Segher Boessenkool
> wrote:
>
> On Fri, Mar 13, 2020 at 01:49:07PM -0400, Athira Rajeev wrote:
>> Sampled instruction address register (SIER), is a PMU register,
>
> SIER stands for "Sampled Instruction Event Register", instea
rently all of the bits from SIER are saved for EBB events. Patch fixes
this by ANDing the "sier_user_mask" to data from SIER in ebb_switch_out().
This will force save only architected bits from the SIER.
Fixes: 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s"
r 64-bit book3s")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 3086055..48b61cc 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/ar
601 - 700 of 700 matches
Mail list logo
