We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
v2: no change
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5 dele
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
v2: no change
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
v2: no change
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index a1571b3
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
v2: no change
arch/powerpc/kernel/head_8xx.S | 25
en CR is restored
Signed-off-by: Christophe Leroy
---
v2: removed the CPU6 specific handling of CR which was saving (only) 1 cycle but
was making the code more difficult to maintain due to too many different cases
arch/powerpc/kernel/head_8xx.S | 29 +++--
1 file change
:
* Without the patch : 2,8 Mbps
* With the patch : 4,3 Mbps
Signed-off-by: Christophe Leroy
---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 95 +++---
drivers/net/ethernet/freescale/fs_enet/fs_enet.h | 1 +
2 files changed, 66 insertions(+), 30 deletions(-)
diff --git
L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 34 +++---
1 file changed, 15 insertions(+), 19 deletions(-)
diff
11 - powerpc/8xx: Add support for TASK_SIZE greater than 0x8000
All changes have been successfully tested on MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
v3: 01-06 no change ; 07-11 changed
arch/powerpc/include/asm/pgtable-ppc32.h | 4 +
arch/powerpc/kernel
tries, remove all those
tests and let the 8xx handle it. This reduce the number of cycle when the
entries are valid which is the case most of the time, and doesn't significantly
increase the time for handling invalid entries.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
ar
When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to
optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide
aligned memory blocks, so lets use a kmem_cache pool instead.
Signed-off-by: Christophe Leroy
---
v2: changed to apply cleanly to linux
Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and
MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 6 --
1 file chang
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index a485ad7..a1571b3 100644
--- a/arch/powerpc/kernel
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07)
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Fixed the macro (missing -) and changed macro name to be more explicit
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.
Signed-off-by: Christophe Leroy
---
v2: fixed/added comments to explain what is the real content of M_TW
v3: no change
arch/powerpc/kernel/head_8xx.S
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07
en CR is restored
Signed-off-by: Christophe Leroy
---
v2: removed the CPU6 specific handling of CR which was saving (only) 1 cycle but
was making the code more difficult to maintain due to too many different cases
v3: no change (but impacted by patch 07)
arch/powerpc/kernel/head_8xx.S
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(
This patchset provides a few optimisations related to IP checksum functions.
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
arch/powerpc/include/asm/checksum.h | 28
arch/powerpc/lib/checksum_32.S | 16
2 files changed, 28
On PPC_8xx, lwz has a 2 cycles latency, and branching also takes 2 cycles.
As the size of the header is minimum 5 words, we can unroll the loop for the
first words to reduce number of branching, and we can re-order the instructions
to limit loading latency.
Signed-off-by: Christophe Leroy
include/net/checksum.h also offers the possibility to define an arch specific
function.
This patch provides a ppc32 specific csum_add() inline function.
Signed-off-by: Christophe Leroy
---
v2: changed constraints on the __asm__
arch/powerpc/include/asm/checksum.h | 12
1 file changed, 12
csum_tcpudp_nofold()
function.
Signed-off-by: Christophe Leroy
---
v2: no change
arch/powerpc/include/asm/checksum.h | 15 +++
arch/powerpc/lib/checksum_32.S | 16
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/checksum.h
b
- powerpc/8xx: dont save CR in SCRATCH registers
04 - powerpc/8xx: Use SPRG2 instead of DAR for saving r3
05 - powerpc/8xx: Add support for TASK_SIZE greater than 0x8000
All changes have been successfully tested on MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
v3: 01-06 no
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: Respined against scootwood.git next (0dc294f7)
arch/powerpc/kernel/head_
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Fixed the macro (missing -) and changed macro name to be more explicit
v4: Respined against scootwood.git next (0dc294f7)
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07)
v4: Respined against scootwood.git next (0dc294f7)
arch/powerpc/kernel
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07
en CR is restored
Signed-off-by: Christophe Leroy
---
v2: removed the CPU6 specific handling of CR which was saving (only) 1 cycle but
was making the code more difficult to maintain due to too many different cases
v3: no change (but impacted by patch 07)
v4: Respined against scootwood.git next (0dc
Le 13/02/2015 18:41, K Richard Pixley a écrit :
I'm having trouble figuring out how to embed a dtb file into my
kernel. I'm thinking that there should be a standard, architecture
independent facility for this akin to initramfs, yes?
Could someone please either point me to the standard facili
e CPM UART:
when the CPM is of type CPM1, we simply do an of_iomap() of the area provided
via the device tree.
Signed-off-by: Christophe Leroy
---
drivers/spi/spi-fsl-cpm.c | 32 +++-
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/spi-fsl-
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
SEC1 and SEC2 have different EU base addresses, so define base addresses
as #define
SEC1 and SEC2 have different bit masks for ISR registers, so create a
macro to define them
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.h | 85 ++--
1
During init and reset, some actions are different between SEC1 and SEC2
This patch isolates them in small helper functions that we will be able
to redefine for SEC1
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 20
1 file changed, 16 insertions(+), 4
utput scatterlists
We move to talitos.h some of the helpers that are used by both talitos.c
and talitos2.c
Signed-off-by: Christophe Leroy
---
drivers/crypto/Kconfig| 4 +
drivers/crypto/Makefile | 1 +
drivers/crypto/talitos.c | 666 +-
dr
In order to be able to manage differences between SEC1 and SEC2, we split
talitos.h into two parts.
talitos2.h will contain all parts that are specific to SEC2 and different on
SEC1
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.h | 163
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 163 ---
1 file changed, 85 insertions(+), 78 deletions(-)
diff --git a/drivers
SEC1 doesn't support scatter/gather, therefore this part of the code will
have to be implemented differently for SEC1, so we isolate it in a small
helper function
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 29 +++--
1 file changed, 19 inser
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 4 +---
drivers/crypto/talitos2.h | 2 ++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6c1f6f1..9f75ec9 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers
Move reset/init helpers init talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 19 ---
drivers/crypto/talitos2.h | 20
2 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/crypto
move sg_count() helper into talitos.h as it will be needed by SEC1 specific
functions
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 20
drivers/crypto/talitos.h | 21 +
2 files changed, 21 insertions(+), 20 deletions(-)
diff --git a
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 2 +-
drivers/crypto/talitos2.h | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a
Move hash chain handling into talitos2.h as only SEC2 has sg chaining
capatibility
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 34 --
drivers/crypto/talitos2.h | 34 ++
2 files changed, 34 insertions(+), 34
Move interrupt related macros in talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 58 -
drivers/crypto/talitos2.h | 60 +++
2 files changed, 60
This patch updates the documentation by including SEC1 into SEC2/3 doc
Signed-off-by: Christophe Leroy
---
Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
b
[17/17] crypto: talitos - Update DT bindings with SEC1
Signed-off-by: Christophe Leroy
.../devicetree/bindings/crypto/fsl-sec2.txt| 5 +-
drivers/crypto/Kconfig | 8 +
drivers/crypto/Makefile| 2 +
drivers/crypto/talitos.c
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos1.c | 21 +
drivers/crypto/talitos1.h | 4
drivers/crypto/talitos2.h | 6 ++
4 files
addition
* SEC1 doesn't support scatter/gather
* SEC1 has a different descriptor structure
We add a helper function for clearing the desc field in the descriptor as that
field needs to be cleared on SEC1 and doesn't exist on SEC2.
Signed-off-by: Christophe Leroy
---
drivers/cryp
SEC2 and SEC1 error handling will be different because so many bits are
different. So we move error handling into talitos2.c
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 103 +-
drivers/crypto/talitos.h | 8
drivers/crypto
SEC1 and SEC2 have different EU base addresses, so define base addresses
as #define
SEC1 and SEC2 have different bit masks for ISR registers, so create a
macro to define them
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.h | 85 ++--
1
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 163 ---
1 file changed, 85 insertions(+), 78 deletions(-)
diff --git a/drivers
During init and reset, some actions are different between SEC1 and SEC2
This patch isolates them in small helper functions that we will be able
to redefine for SEC1
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 20
1 file changed, 16 insertions(+), 4
SEC1 doesn't support scatter/gather, therefore this part of the code will
have to be implemented differently for SEC1, so we isolate it in a small
helper function
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 29 +++--
1 file changed, 19 inser
utput scatterlists
We move to talitos.h some of the helpers that are used by both talitos.c
and talitos2.c
Signed-off-by: Christophe Leroy
---
drivers/crypto/Kconfig| 4 +
drivers/crypto/Makefile | 1 +
drivers/crypto/talitos.c | 666 +-
dr
In order to be able to manage differences between SEC1 and SEC2, we split
talitos.h into two parts.
talitos2.h will contain all parts that are specific to SEC2 and different on
SEC1
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.h | 163
SEC2 and SEC1 error handling will be different because so many bits are
different. So we move error handling into talitos2.c
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 103 +-
drivers/crypto/talitos.h | 8
drivers/crypto
Move interrupt related macros in talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 58 -
drivers/crypto/talitos2.h | 60 +++
2 files changed, 60
Move reset/init helpers init talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 19 ---
drivers/crypto/talitos2.h | 20
2 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/crypto
Move hash chain handling into talitos2.h as only SEC2 has sg chaining
capatibility
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 34 --
drivers/crypto/talitos2.h | 34 ++
2 files changed, 34 insertions(+), 34
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 4 +---
drivers/crypto/talitos2.h | 2 ++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 8b627d0..0262e75 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers
move sg_count() helper into talitos.h as it will be needed by SEC1 specific
functions
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 20
drivers/crypto/talitos.h | 21 +
2 files changed, 21 insertions(+), 20 deletions(-)
diff --git a
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 2 +-
drivers/crypto/talitos2.h | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a
addition
* SEC1 doesn't support scatter/gather
* SEC1 has a different descriptor structure
We add a helper function for clearing the desc field in the descriptor as that
field needs to be cleared on SEC1 and doesn't exist on SEC2.
Signed-off-by: Christophe Leroy
---
drivers/cryp
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos1.c | 21 +
drivers/crypto/talitos1.h | 4
drivers/crypto/talitos2.h | 6 ++
4 files
This patch updates the documentation by including SEC1 into SEC2/3 doc
Signed-off-by: Christophe Leroy
---
Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
b
d
[15/17] crypto: talitos - Implementation of SEC1
[16/17] crypto: talitos - SEC1 bugs on 0 data hash
[17/17] crypto: talitos - Update DT bindings with SEC1
Signed-off-by: Christophe Leroy
.../devicetree/bindings/crypto/fsl-sec2.txt| 5 +-
drivers/crypto/Kc
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/cpm_uart/Make
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
drivers/mtd/maps/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
arch/um/sys-ppc/misc.S | 12 ++--
1 file changed, 6 insertions(+), 6 deletion
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
drivers/video/console/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
drivers/isdn/hardware/mISDN/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletion
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 2 +-
drivers/net/ethernet/freescale/f
get rid of CONFIG_8xx
All but the last one are independant and can be applied in any
order. Only the 8th one requires the first 7 patches to be applied.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 10 +-
arch/powerpc/Makefile
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/Kconfig.cputype | 5 -
1 file changed, 5 deletions(-)
diff --
mp to handle compat with arch=ppc"
It looks like not many places still have that old CONFIG_8xx used,
so it is likely to be a good time to get rid of it completely ?
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 10 +-
arch/powerp
Your patches seem to be under review in Patchwork, see
https://patchwork.ozlabs.org/patch/526275/
Why do you resend it ?
Christophe
Le 16/02/2016 07:37, Anshuman Khandual a écrit :
This is the continuation (rebased and reworked) of the series
posted at https://lkml.org/lkml/2014/5/5/15
Le 16/02/2016 22:21, Scott Wood a écrit :
On Thu, 2016-02-11 at 17:16 +0100, Christophe Leroy wrote:
This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
PPC32 doesn't have the PACA structure, so we use the task_info
structure to store the accounting data.
In order to reuse on
n PPC32 and
u64 on PPC64
Signed-off-by: Christophe Leroy
---
Changes in v3: unlike previous version of the patch that was inspired
from IA64 architecture, this new version tries to reuse as much as
possible the PPC64 implementation.
PPC32 doesn't have PACA and past discusion on v2 version
improving the system]
url:https://github.com/0day-ci/linux/commits/Christophe-Leroy/powerpc32-
provide-VIRT_CPU_ACCOUNTING/20160224-010322
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git ne
xt
config: powerpc-defconfig (attached as .config)
reproduce:
wget https
n PPC32 and
u64 on PPC64
Signed-off-by: Christophe Leroy
---
Changes in v3: unlike previous version of the patch that was inspired
from IA64 architecture, this new version tries to reuse as much as
possible the PPC64 implementation.
PPC32 doesn't have PACA and past discusion on v2 version
Le 23/09/2015 07:43, Denis Kirjanov a écrit :
On 9/22/15, Christophe Leroy wrote:
In several architectures, ip_fast_csum() is inlined
There are functions like ip_send_check() which do nothing
much more than calling ip_fast_csum().
Inlining ip_fast_csum() allows the compiler to optimise
Le 23/10/2015 05:33, Scott Wood a écrit :
On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
Simplify csum_add(a, b) in case a or b is constant 0
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/checksum.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch
Le 23/10/2015 05:30, Scott Wood a écrit :
On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
r5 does contain the value to be updated, so lets use r5 all way long
for that. It makes the code more readable.
To avoid confusion, it is better to use adde instead of addc
The first
multiple constant length
* uses ip_fast_csum() for other 32bits multiple constant
* uses __csum_partial() in all other cases
Signed-off-by: Christophe Leroy
---
v2: Taken into account Scott's comments
applies on top of scottwood/linux next
arch/powerpc/include/asm/checksum.h
Le 12/03/2016 00:15, Scott Wood a écrit :
On Tue, Feb 09, 2016 at 05:08:02PM +0100, Christophe Leroy wrote:
Once the linear memory space has been mapped with 8Mb pages, as
seen in the related commit, we get 11 millions DTLB missed during
the reference 600s period. 77% of the misses are on
simple variable.
Signed-off-by: Scott Wood
Cc: Christophe Leroy
---
Christope, could you test? And was there any particular reason for the [1]?
As far as I remember the idea behind the [1] was to ensure that the
variable was allocated from stack memory and not optimised in a register.
I will
bits, and
minor fixes/cleanup.
Hi Scott,
This one's giving me a few troubles.
[...]
Christophe Leroy (31):
powerpc/8xx: Handle CPU6 ERRATA directly in mtspr() macro
This breaks mpc866_ads_defconfig for me, with lots of:
arch/powerpc/mm/8xx_mmu.c:139:2: error: memory input 1 i
Some versions of GCC, reportedly before 4.8, fail with
arch/powerpc/mm/8xx_mmu.c:139:2: error: memory input 1 is not directly
addressable
Change the one-element array into a simple variable to avoid this.
Signed-off-by: Christophe Leroy
Cc: Scott Wood
---
Verified with GCC 4.4.4 and GCC 4.8.3
Le 15/03/2016 18:41, Scott Wood a écrit :
On Tue, 2016-03-15 at 14:07 +0100, Christophe Leroy wrote:
Some versions of GCC, reportedly before 4.8, fail with
arch/powerpc/mm/8xx_mmu.c:139:2: error: memory input 1 is not directly
addressable
"before 4.8" means "< 4.8",
Le 30/03/2016 10:50, Zhao Qiang a écrit :
The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.
When using TSA, how does the TSA gets configured ? Especially how do you
describe which Timeslot is switched to HDLC channels ?
Is it possible to route some Timeslots t
: 9 Local timer interrupts for others
SPU: 0 Spurious interrupts
PMI: 0 Performance monitoring interrupts
MCE: 0 Machine check exceptions
Signed-off-by: Christophe Leroy
---
arch/powerpc/sysdev/mpc8xx_pic.c | 2 +-
1 file changed, 1 insertion(+), 1
rh_alloc() returns (unsigned long)-ERRxx on error, which may
result in overwriting memory outside the MURAM AREA.
Signed-off-by: Christophe Leroy
---
arch/powerpc/sysdev/cpm_common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch
rivers/crypto/talitos.h:58: error: unknown field 'eptr' specified in
initializer
drivers/crypto/talitos.h:58: warning: excess elements in struct initializer
drivers/crypto/talitos.h:58: warning: (near initialization for 'zero_entry')
make[3]: *** [drivers/crypto/talito
Le 02/09/2015 16:20, Joakim Tjernlund a écrit :
On Thu, 2015-08-27 at 15:58 +0200, leroy christophe wrote:
Hi,
Has anybody already used 'perf' tool on powerpc MPC83xx ?
I have been succesfully using perf on MPC8xx, but on MPC83xx I get
something strange.
perf record/report reports addresses
inter() is
redefined in arch/powerpc/perf/core-book3s.c when CONFIG_PPC_PERF_CTRS
is selected.
This patch moves the selection of CONFIG_PPC_HAVE_PMU in 86xx section
so that CONFIG_PPC_PERF_CTRS won't be selected for other 6xx powerpc
Signed-off-by: Christophe Leroy
---
arch/powerpc/plat
Le 04/09/2015 15:33, Michal Sojka a écrit :
Dear Christophe,
my MPC5200-based system stopped booting recently. I bisected the problem
to your commit below. If I revert that commit (on top of
807249d3ada1ff28a47c4054ca4edd479421b671 = v4.2-6663-g807249d), my
system boots again.
Do you use ma
Le 04/09/2015 18:43, Scott Wood a écrit :
On Thu, Sep 03, 2015 at 11:27:03AM +0200, Christophe Leroy wrote:
On PPC832x, perf record/report reports martian addresses
2.62% perf_reseau4 libpthread-2.18.so [.] __libc_send
2.56% perf_reseau4 [kernel.kallsyms] [k] __ip_make_skb
Le 04/09/2015 16:35, Michal Sojka a écrit :
On Fri, Sep 04 2015, Christophe LEROY wrote:
Le 04/09/2015 15:33, Michal Sojka a écrit :
Dear Christophe,
my MPC5200-based system stopped booting recently. I bisected the problem
to your commit below. If I revert that commit (on top of
Le 05/09/2015 02:08, Michal Sojka a écrit :
On 4.9.2015 21:49, Michal Sojka wrote:
On 4.9.2015 20:10, christophe leroy wrote:
Le 04/09/2015 16:35, Michal Sojka a écrit :
On Fri, Sep 04 2015, Christophe LEROY wrote:
Le 04/09/2015 15:33, Michal Sojka a écrit :
Dear Christophe,
my MPC5200
Hi Michael
Le 07/09/2015 03:14, Michael Ellerman a écrit :
Hi Michal,
Thanks for finding the problem.
On Sun, 2015-09-06 at 23:01 +0200, Michal Sojka wrote:
I found the problem. The compiler replaces an assignment with a call to
memcpy. The following patch fixes the problem for me. However, I
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