On Aug 7, 2012, at 11:06 PM, Varun Sethi wrote:
All SOC device error interrupts are muxed and delivered to the core
as a single MPIC error interrupt. Currently all the device drivers
requiring access to device errors have to register for the MPIC error
interrupt as a shared interrupt.
On Aug 3, 2012, at 5:14 AM, Jia Hongtao wrote:
Remove the dependency on PCI initialization for SWIOTLB initialization.
So that PCI can be initialized at proper time.
SWIOTLB is partly determined by PCI inbound/outbound map which is assigned
in PCI initialization. But swiotlb_init() should
On Aug 9, 2012, at 2:42 AM, Olivia Yin wrote:
power-isa-version and power-isa-* are cpu node general properties defined in
ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of
On Aug 9, 2012, at 2:42 AM, Olivia Yin wrote:
power-isa-version and power-isa-* are cpu node general properties defined in
ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of
On Aug 9, 2012, at 2:42 AM, Olivia Yin wrote:
power-isa-version and power-isa-* are cpu node general properties defined in
ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of
On Aug 9, 2012, at 2:42 AM, Olivia Yin wrote:
power-isa-version and power-isa-* are cpu node general properties defined in
ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of
Ben,
Two updates from last week (one dts bug fix, one minor defconfig update)
- k
The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
are available in the git repository at:
On Aug 10, 2012, at 3:19 AM, Jia Hongtao wrote:
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function
On Aug 10, 2012, at 3:19 AM, Jia Hongtao wrote:
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function
On Aug 10, 2012, at 5:48 AM, Shengzhou Liu wrote:
when missing USB PHY clock, kernel booting up will hang during USB
initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
CPU hanging in this case.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
On Aug 9, 2012, at 12:05 AM, Li Yang wrote:
On Thu, Aug 9, 2012 at 10:52 AM, Jia Hongtao-B38951
b38...@freescale.com wrote:
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+b38951=freescale@lists.ozlabs.org] On Behalf Of Kumar Gala
Sent: Wednesday, August
On Jul 24, 2012, at 5:20 AM, Jia Hongtao wrote:
Power supply for PCI inbound/outbound window registers is off when
system
go to deep-sleep state. We save the values of registers before
suspend and restore to registers after resume.
Signed-off-by: Jiang Yutang b14...@freescale.com
On Aug 3, 2012, at 5:14 AM, Jia Hongtao wrote:
Remove the dependency on PCI initialization for SWIOTLB initialization.
So that PCI can be initialized at proper time.
SWIOTLB is partly determined by PCI inbound/outbound map which is assigned
in PCI initialization. But swiotlb_init() should
On Aug 7, 2012, at 10:34 AM, Scott Wood wrote:
On 08/07/2012 05:11 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 31, 2012 9:37 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott
On Aug 7, 2012, at 3:43 AM, Zhao Chenhui wrote:
The cpufreq driver of mpc85xx will disable/enable cpu hotplug temporarily.
Therefore, the related functions should be exported.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
include/linux/cpu.h |4
1 files changed, 4
On Aug 6, 2012, at 7:44 AM, Varun Sethi wrote:
All SOC device error interrupts are muxed and delivered to the core
as a single MPIC error interrupt. Currently all the device drivers
requiring access to device errors have to register for the MPIC error
interrupt as a shared interrupt.
With
On Aug 4, 2012, at 1:31 PM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, August 03, 2012 10:04 PM
To: Sethi Varun-B16395
Cc: ag...@suse.de; b...@kernel.crashing.org; linuxppc-
d...@lists.ozlabs.org; kvm
On Aug 5, 2012, at 10:10 PM, tiejun.chen wrote:
On 07/30/2012 04:15 PM, Tiejun Chen wrote:
We miss that correct WDIOC_GETSUPPORT return path when perform
copy_to_user() properly.
Any comments?
Thanks
Tiejun
Adding Timur, as he's touched watchdog last.
- k
Signed-off-by: Tiejun Chen
On Jul 9, 2012, at 7:55 AM, Varun Sethi wrote:
Move the E.HV check and CPU_FTR_EMB_HV flag manipulation to the cpu setup
code.
Create a separate routine for E.HV ivors setup.
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 29
On Jul 9, 2012, at 7:58 AM, Varun Sethi wrote:
Merge the 32 bit cpu setup code for e500mc/e5500 and define the cpu_restore
routine (for e5500/e6500) only for the 64 bit case. The cpu_restore routine
is used in the 64 bit case for setting up the secondary cores.
Signed-off-by: Varun Sethi
On Jul 9, 2012, at 8:01 AM, Varun Sethi wrote:
For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions.
The cpu_setup function (for the primary core) is passed the cpu_spec pointer,
which is not there in case of the cpu_restore function. Also, in our case
we will have to
On Aug 3, 2012, at 5:34 PM, Benjamin Herrenschmidt wrote:
On Fri, 2012-08-03 at 08:39 -0500, Kumar Gala wrote:
Ben,
Weekly bug fix pull request.
Well, Linus is on holiday so I don't think it makes sense for me to ask
him to pull anything just yet... I'll put it in my tree some time next
On Aug 2, 2012, at 9:21 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Thursday, August 02, 2012 8:55 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V4
On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
All SOC device error interrupts are muxed and delivered to the core as a
single
MPIC error interrupt. Currently all the device drivers requiring access to
device
errors have to register for the MPIC error interrupt as a shared interrupt.
Ben,
Weekly bug fix pull request.
- k
The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git merge
for you to fetch
upstream, Timur please verify)
powerpc/fsl: add MSI support for the Freescale hypervisor KVM/HV
Timur Tabi
[CORE]
powerpc/booke: Re-organize debug code COREKumar Gala
[USB] (Again, this is trivial and spend 10m and send upstream)
usb/fsl: fixed USB wakeup USB
On Aug 3, 2012, at 5:14 AM, Jia Hongtao wrote:
We change fsl_add_bridge to return -ENODEV if the controller is working in
agent mode. Then check the return value of fsl_add_bridge to guarantee
that only successfully added host bus will be scanned.
Signed-off-by: Jia Hongtao
On Aug 3, 2012, at 9:42 AM, Li Yang wrote:
On Fri, Aug 3, 2012 at 8:38 PM, Kumar Gala ga...@kernel.crashing.org wrote:
On Aug 2, 2012, at 9:21 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Thursday, August 02, 2012 8
On Jul 9, 2012, at 8:04 AM, Varun Sethi wrote:
Added CPU_FTR_EMB_HV feature check for e550.
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kernel/cpu_setup_fsl_booke.S |6 ++
1 files changed, 6
On Aug 3, 2012, at 11:44 AM, Scott Wood wrote:
On 08/03/2012 08:19 AM, Kumar Gala wrote:
On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
+ /* ioremap'ed base for error interrupt registers */
+ u32 __iomem *err_regs;
+ /* error interrupt config */
+ u32
On Aug 3, 2012, at 2:16 PM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, August 04, 2012 12:43 AM
To: Wood Scott-B07421
Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
d...@lists.ozlabs.org
Subject
On Aug 3, 2012, at 1:52 PM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, August 03, 2012 6:49 PM
To: Sethi Varun-B16395
Cc: linuxppc-dev@lists.ozlabs.org; Hamciuc Bogdan-BHAMCIU1
Subject: Re: [PATCH 3/3 v3
On Aug 2, 2012, at 6:42 AM, Jia Hongtao wrote:
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function
On Aug 2, 2012, at 6:42 AM, Jia Hongtao wrote:
Remove the dependency on PCI initialization for SWIOTLB initialization.
So that PCI can be initialized at proper time.
SWIOTLB is partly determined by PCI inbound/outbound map which is assigned
in PCI initialization. But swiotlb_init() should
On Jul 30, 2012, at 1:09 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, July 27, 2012 9:24 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH 5/6
On Jul 31, 2012, at 2:21 AM, Li Yang wrote:
On Mon, Jul 30, 2012 at 10:46 PM, Kumar Gala ga...@kernel.crashing.org
wrote:
On Jul 30, 2012, at 3:26 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, July 28
drivers/dma/fsldma.c: In function 'fsl_dma_tx_submit':
drivers/dma/fsldma.c:409:15: warning: 'cookie' may be used uninitialized in
this function
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
drivers/dma/fsldma.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Jul 20, 2012, at 7:42 AM, Zhao Chenhui wrote:
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep
On Jul 31, 2012, at 8:55 AM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 31, 2012 7:20 PM
To: Sethi Varun-B16395
Cc: Wood Scott-B07421
Subject: Re: [PATCH 1/3] powerpc/mpic: finish supporting timer group B
On Jul 20, 2012, at 7:42 AM, Zhao Chenhui wrote:
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/platforms/85xx/smp.c | 46 ++--
1 files changed, 23 insertions(+), 23 deletions(-)
applied to next
- k
On Jul 20, 2012, at 7:42 AM, Zhao Chenhui wrote:
In the case of cpu hotplug, the cpu_state should be set to CPU_UP_PREPARE
when kicking cpu.
Otherwise, the cpu_state is always CPU_DEAD after calling
generic_set_cpu_dead(), which
makes the delay in generic_cpu_die() not happen.
On Jul 20, 2012, at 7:42 AM, Zhao Chenhui wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao
On Jul 31, 2012, at 2:58 AM, Wang Dongsheng-B40534 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, July 27, 2012 9:14 PM
To: Wang Dongsheng-B40534
Cc: b...@kernel.crashing.org; pau...@samba.org; Wood Scott-B07421;
linuxppc-dev
On Jul 31, 2012, at 9:48 AM, Liu Qiang-B32616 wrote:
Hi Kumar,
From: Linuxppc-dev
[linuxppc-dev-bounces+qiang.liu=freescale@lists.ozlabs.org] on behalf of
Kumar Gala [ga...@kernel.crashing.org]
Sent: Tuesday, July 31, 2012 8:57 AM
On Jul 30, 2012, at 3:07 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, July 27, 2012 8:47 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5
On Jul 30, 2012, at 3:26 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, July 28, 2012 5:17 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
Li Yang-R58472
On Jul 27, 2012, at 5:20 PM, Benjamin Herrenschmidt wrote:
On Fri, 2012-07-27 at 16:58 -0500, Kumar Gala wrote:
On Jul 20, 2012, at 7:47 AM, Zhao Chenhui wrote:
During suspend, all interrupts including IPI will be disabled. In this case,
the suspend process will hang in SMP. To prevent
Ben,
A few patches that missed the initial 3.6 window. These are bug fixes at
this point.
- k
The following changes since commit 574ce79cea9d3fda109ffcc82f81733de4740e5c:
powerpc/mpic: Create a revmap with enough entries for IPIs and timers
(2012-07-23 14:20:42 +1000)
are available in the
On Jul 27, 2012, at 3:35 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:15 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1
On Jul 27, 2012, at 1:20 AM, dongsheng.w...@freescale.com
dongsheng.w...@freescale.com wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Global timers A and B internal to the PIC. The two independent groups
of global timer, group A and group B, are identical in their functionality.
On Jul 24, 2012, at 5:20 AM, Jia Hongtao wrote:
Power supply for PCI inbound/outbound window registers is off when system
go to deep-sleep state. We save the values of registers before suspend
and restore to registers after resume.
Signed-off-by: Jiang Yutang b14...@freescale.com
On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
Hi kumar,
I know duplicate code from pci_process_bridge_OF_ranges() is
hard to accept but refactor the code to have a shared function
is knotty. Actually this is the reason I didn't do the
On Jul 26, 2012, at 10:14 PM, Li Yang wrote:
On Fri, Jul 27, 2012 at 1:29 AM, Kumar Gala ga...@kernel.crashing.org wrote:
On Jul 26, 2012, at 9:02 AM, Li Yang wrote:
On Fri, Jul 20, 2012 at 8:42 PM, Zhao Chenhui
chenhui.z...@freescale.com wrote:
Changes for v8:
* Separated the cpu
On Jul 20, 2012, at 7:47 AM, Zhao Chenhui wrote:
During suspend, all interrupts including IPI will be disabled. In this case,
the suspend process will hang in SMP. To prevent this, pass the flag
IRQF_NO_SUSPEND when requesting IPI irq.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
On Jul 26, 2012, at 7:39 AM, Claudiu Manoil wrote:
On 7/19/2012 3:07 PM, Kumar Gala wrote:
On Jul 19, 2012, at 5:28 AM, Claudiu Manoil wrote:
The sram_offset parameter represents a physical address
and should be of type phys_addr_t. As part of this fix,
the extraction of sram_params
On Jul 26, 2012, at 9:02 AM, Li Yang wrote:
On Fri, Jul 20, 2012 at 8:42 PM, Zhao Chenhui
chenhui.z...@freescale.com wrote:
Changes for v8:
* Separated the cpu hotplug patch into three patches, as follows
[PATCH v8 1/7] powerpc/smp: use a struct epapr_spin_table to replace macros
[PATCH v8
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
PCI initialization is now done by PCI controller driver. In board_setup_arch
stage we don't need PCI init any more but swiotlb should be determined at this
stage.
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Li Yang
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
PCI initialization is now done by PCI controller driver. In board_setup_arch
stage we don't need PCI init any more but swiotlb should be determined at this
stage.
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Li Yang
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
PCI host bridge is primary bus if it contains an ISA node. But not all boards
fit this rule. Device tree should be updated for all these boards.
I don't really seen any reason for this patch. We can just use the code as
Scott wrote it that
On Jul 26, 2012, at 9:47 AM, Claudiu Manoil wrote:
The sram_offset parameter represents a physical address
and should be of type phys_addr_t. As part of this fix,
the extraction of sram_params is being cleaned-up and
fixed.
This patch fixes now the case when the offset value of
0xfff0
On Jul 23, 2012, at 3:43 PM, Timur Tabi wrote:
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead.
On Jul 26, 2012, at 10:08 AM, Timur Tabi wrote:
The PCI controller on the Freescale P5040 is v2.4.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
applied to next
- k
On Jul 26, 2012, at 10:08 AM, Timur Tabi wrote:
From: Kim Phillips kim.phill...@freescale.com
Add device tree (dtsi) files for the Freescale P5040 SOC. Since this
SOC introduces SEC v5.2, add the dtsi file for that also.
Signed-off-by: Kim Phillips kim.phill...@freescale.com
On Jul 26, 2012, at 10:08 AM, Timur Tabi wrote:
Add support for the Freescale P5040DS Reference Board (Superhydra), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040
On Jul 23, 2012, at 6:12 PM, Timur Tabi wrote:
The Freescale / iVeia P1022RDK reference board is a small-factor board
with a Freescale P1022 SOC. It includes:
1) 512 MB 64-bit DDR3-800 (max) memory
2) 8MB SPI serial flash memory for boot loader
3) Bootable 4-bit SD/MMC port
4) Two
On Jul 25, 2012, at 1:17 PM, Timur Tabi wrote:
Add support for the Freescale P5040DS Reference Board (Superhydra), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040
On Jul 20, 2012, at 2:17 AM, Joakim Tjernlund wrote:
Hi Guys
I see that you have been hacking Freescale PCI before so I send this to
you(and the list)
We are using PCIe(as RC) on P2010(basically a mpc85xx) and have PCI device
that
started from user space (needs advance clock conf)
On Jul 19, 2012, at 5:28 AM, Claudiu Manoil wrote:
The sram_offset parameter represents a physical address
and should be of type phys_addr_t. As part of this fix,
the extraction of sram_params is being cleaned-up and
fixed.
This patch fixes now the case when the offset value of
0xfff0
On Jul 17, 2012, at 2:18 AM, Shaohui Xie wrote:
Default CCB on P3041 is 750MHz, but espi cannot work at 40MHz with this CCB,
so we need to slow down the clock rate of espi to 35MHz to make it work stable
with the CCB.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
On Jul 13, 2012, at 5:40 PM, Timur Tabi wrote:
We only need two examples of CAMP device trees in the upstream kernel.
Co-operative Asymmetric Multi-Processing (CAMP) is a technique where two
or more operating systems (typically multiple copies of the same Linux kernel)
are loaded into
On Jul 13, 2012, at 2:28 PM, Timur Tabi wrote:
The Freescale P1022 has a unique pin muxing feature where the DIU video
controller's video signals are muxed with 24 of the local bus address signals.
When the DIU is enabled, the bulk of the local bus is disabled, preventing
access to
On Jul 16, 2012, at 2:06 PM, Stuart Yoder wrote:
From: Stuart Yoder stuart.yo...@freescale.com
without setting the stack limit like this there is the possibility
of stack overflow which corrupts the thread info but
is not detected by stack overflow detection
Signed-off-by: Stuart Yoder
On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:
On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
of timer can not reset by software after set to a non-zero value.
Which means software can not reset the timeout behaviour of watchdog timer.
This patch selects WATCHDOG_NOWAYOUT
) == CPU_UP_PREPARE;
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 2e65fe8..925e678 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -2,7 +2,7 @@
* Author: Andy Fleming aflem...@freescale.com
* Kumar Gala ga
On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
From: Li Yang le...@freescale.com
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
Some Freescale chips like MPC8536 and P1022 has deep
On Jul 13, 2012, at 7:25 AM, Josh Boyer wrote:
On Fri, Jul 13, 2012 at 7:50 AM, Kumar Gala ga...@kernel.crashing.org wrote:
On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:
On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
of timer can not reset by software after set
Is the functionality of all of these SDK patches upstream now?
[ ignore commit id's ]
b257909 powerpc/85xx: p1022ds: disable the NAND flash node if video is enabled
ee260f4 powerpc/mpc85xx: p1022ds support the MTD for NOR and NAND flash
4be8bb6 powerpc/mpc85xx: 32bit address support for p1022ds
On Jul 13, 2012, at 8:01 AM, Kumar Gala wrote:
Is the functionality of all of these SDK patches upstream now?
[ ignore commit id's ]
b257909 powerpc/85xx: p1022ds: disable the NAND flash node if video is enabled
ee260f4 powerpc/mpc85xx: p1022ds support the MTD for NOR and NAND flash
On Jul 12, 2012, at 9:27 PM, b29...@freescale.com b29...@freescale.com
wrote:
From: Tang Yuantian yuantian.t...@freescale.com
The following platforms are supported:
mpc8544, mpc8572, mpc8536, p1021, p1025, p1024, p1010.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
On Jul 12, 2012, at 9:27 PM, b29...@freescale.com b29...@freescale.com
wrote:
From: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/boot/dts/p2020rdb-pc_32b.dts |4 ++--
arch/powerpc/boot/dts/p2020rdb-pc_36b.dts |
On Jul 12, 2012, at 5:02 AM, Shengzhou Liu wrote:
On some platforms, in RC mode, root port has neither MSI/MSI-X nor INTx
interrupt generated, which are available only in EP mode on those platform.
In this case, we try to use other interrupt for port service driver to have
AER, Hot-plug,
On Jul 12, 2012, at 5:28 AM, Jia Hongtao-B38951 wrote:
Note that this patch works with uboot update.
Please refer to:
http://patchwork.ozlabs.org/patch/170627/
-Hongtao.
Will RGMII still work with this patch if I dont update u-boot?
I'm assuming yes.
- k
-Original Message-
On Jul 12, 2012, at 4:36 AM, Jia Hongtao wrote:
In SGMII riser card different PHY chip are used with different external
IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we
should add another group of PHY nodes for SGMII mode.
For MPC8572DS IRQ6 is used for PHY0~PHY1,
The following changes since commit db9112173b185995b80f56e136bd2ae44e4e6366:
powerpc: Turn on BPF_JIT in ppc64_defconfig (2012-07-10 19:19:02 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Christian Herzig (1):
On Jul 11, 2012, at 4:58 AM, Jiucheng Xu wrote:
On Tue, 2012-07-10 at 06:48 -0500, Kumar Gala wrote:
On Jul 10, 2012, at 3:39 AM, Xu Jiucheng wrote:
---
arch/powerpc/boot/dts/p1021rdb-pc.dtsi| 236
+
arch/powerpc/boot/dts/p1021rdb-pc_32b.dts | 96
On Jul 10, 2012, at 3:39 AM, Xu Jiucheng wrote:
P1021RDB-PC Overview
-
1Gbyte DDR3 (on board DDR)
16Mbyte NOR flash
32Mbyte eSLC NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
Real-time clock on I2C bus
SD/MMC connector to interface with the SD memory
On Jul 11, 2012, at 5:40 AM, Shengzhou Liu wrote:
- Enable NAND support
- Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/configs/corenet32_smp_defconfig |8
1 files changed, 8 insertions(+), 0
On Jul 11, 2012, at 5:40 AM, Shengzhou Liu wrote:
Enable USB, MMC, SATA, LBC, MTD, NAND, SPI, PCIe, EDAC, VFAT, NFS, etc.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/configs/corenet64_smp_defconfig | 59 -
1 files changed, 56
On Jul 11, 2012, at 4:56 AM, Shaohui Xie wrote:
Currently, BOOKE watchdog code for checking wdt and wdt_period is
in setup_32.c, it cannot be used in 64-bit, so move it to a common place
setup-common.c, which will be shared by 32-bit and 64-bit.
Also, replace the simple_strtoul with
On Jul 10, 2012, at 7:26 PM, Scott Wood wrote:
Similar to how the primary PCI bridge is identified by looking
for an isa subnode, we determine whether to apply uli exclusions
by looking for a uli subnode.
Signed-off-by: Scott Wood scottw...@freescale.com
---
v2: Rebased on Kumar's next
On Jul 10, 2012, at 7:26 PM, Scott Wood wrote:
This gives the kernel a paravirtualized machine to target, without
requiring both sides to pretend to be targeting a specific board
that likely has little to do with the host in KVM scenarios. This
avoids the need to add new boards to QEMU just
On Jul 10, 2012, at 7:26 PM, Scott Wood wrote:
As an alternative incremental starting point to Jia Hongtao's patchset,
get the FSL PCI init out of the board files, but do not yet convert to a
platform driver.
Rather than having each board supply a magic register offset for
determining the
On Jul 11, 2012, at 9:24 AM, Joakim Tjernlund wrote:
Joakim Tjernlund/Transmode wrote on 2012/06/04 11:06:41:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 2012/06/02
23:21:16:
On Sat, 2012-06-02 at 20:29 +0200, Joakim Tjernlund wrote:
hmm, where does this go w.r.t the
On Jul 10, 2012, at 7:25 AM, Tabi Timur-B04825 wrote:
On Tue, Jul 10, 2012 at 3:39 AM, Xu Jiucheng jiucheng...@freescale.com
wrote:
Create the dts files for each core and splits the devices between
the two cores for P1021RDB-PC.
Core0 has l2, serial0, i2c, spi, gpio, tdm,dma, usb, eth0,
On Jul 11, 2012, at 9:49 AM, Timur Tabi wrote:
Kumar Gala wrote:
Since we already have P1021RDB-PC w/AMP support in upstream I agree we don't
need another example on P1021RDB-PC.
Would you accept a patch that removes all AMP device trees from upstream?
I just don't think that these very
On Jul 11, 2012, at 9:56 AM, Timur Tabi wrote:
Kumar Gala wrote:
No, I think we should have at least one or two examples of AMP dts in
upstream.
We have more than that:
./p2020rdb_camp_core1.dts
./p1020rdb-pc_camp_core1.dts
./mpc8572ds_camp_core1.dts
./p2020rdb_camp_core0.dts
On Jul 11, 2012, at 10:53 PM, Tabi Timur-B04825 wrote:
Kumar Gala wrote:
./p2020rdb_camp_core1.dts
./p1020rdb-pc_camp_core1.dts
./mpc8572ds_camp_core1.dts
./p2020rdb_camp_core0.dts
./p1020rdb-pc_camp_core0.dts
./mpc8572ds_camp_core0.dts
./p1020rdb_camp_core1.dts
./p1020rdb_camp_core0
On May 8, 2012, at 10:46 PM, Bhushan Bharat-R65777 wrote:
.org] On Behalf Of Shaohui Xie
Sent: Tuesday, May 08, 2012 11:37 AM
To: linux-watch...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
Cc: Xie Shaohui-B21989
Subject: [PATCH 1/2] powerpc/watchdog: move booke watchdog param
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