On Friday 21 August 2009 07:17:09 vimal singh wrote:
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 89bf85a..497e175 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -101,9 +101,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtd,
On Friday 21 August 2009 07:41:42 tiejun.chen wrote:
+static void kilauea_fixups(void)
+{
+ /*TODO: Please change this as the real. Note that should be
33MHZ~100MHZ.*/
What does that mean?
It's difficult to check the sysclk value on all revision Kilauea board for
me, and we have to
Hi Feng,
On Friday 21 August 2009 01:42:42 Feng Kan wrote:
We had a board with high number of correctable ECC errors. Which crashed
the jffs when it
was miss correcting the wrong byte location.
OK, thanks.
Do you want me to submit a patch for this, or do you prefer to do it.
Sure, please
-by: Prodyut Hazarika phazar...@amcc.com
Acked-by: Stefan Roese s...@denx.de
Would be great if we could get this fix into 2.6.31.
Cheers,
Stefan
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On Friday 11 September 2009 04:44:34 Benjamin Herrenschmidt wrote:
On Thu, 2009-09-10 at 13:30 -0700, Pravin Bathija wrote:
There is also a patch that was submitted for 440EPX a couple of years
back. The 440EPX SOC causes hangs with Memory Read Multiple (MRM)
commands. Whether MRM is used
On Friday 11 September 2009 07:17:50 Benjamin Herrenschmidt wrote:
On Fri, 2009-09-11 at 07:12 +0200, Stefan Roese wrote:
It's already there. See commit:
5ce4b59653b2c2053cd9a011918ac1e4747f24cc
powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata
Ok, that's another way to do
Hi Sylvain,
On Friday 18 September 2009 17:50:24 Cote, Sylvain wrote:
USB gadget support -- y
Maximum VBUS power usage = 500
Synopsys DWC OTG controller
Synopsys DWC OTG internal DMA mode -- y
USB gadget -- M
gadget zero -- M
On Monday 21 September 2009 15:44:30 Cote, Sylvain wrote:
Looks good so far. I suspect that the only thing missing for your 405EX
custom
board is the following line in the arch/powerpc/sysdev/Makefile:
obj-$(CONFIG_KILAUEA) += amcc-usbotg.o
I have created a new platform
On Tuesday 22 September 2009 23:20:49 Sean MacLennan wrote:
What is the status of this bug?
I've noticed that David pulled in into his repo. So I expect it to hit
mainline in this merge window.
Cheers,
Stefan
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-off-by: Stefan Roese s...@denx.de
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Anton Blanchard an...@samba.org
Cc: Detlev Zundel d...@denx.de
---
Ben, Anton, how should we handle this? Is this patch acceptable? Or how
should this be solved?
arch/powerpc/kernel/time.c | 11
On Thursday 08 October 2009 22:12:56 Benjamin Herrenschmidt wrote:
On Thu, 2009-10-08 at 16:49 +0200, Stefan Roese wrote:
We noticed that recent kernels didn't boot on our 1GHz Canyonlands
460EX
boards anymore. As it seems, patch 8d165db1 [powerpc: Improve
decrementer accuracy] introduced
Additionally to increasing #size-cells to in the root node, we also
need to explicitly define the ranges property in the plb node, because
of the different #size-cells between child and parent.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
---
arch/powerpc
Hi Pravin,
On Wednesday 18 November 2009 01:19:48 pbath...@amcc.com wrote:
From: Pravin Bathija pbath...@amcc.com
Set size cell value to 2 for 4GB memory support in katmai. Also set
PCI-E node inbound DMA ranges size to 4GB for correct boot up of katmai.
As Josh already mentioned, I
Acked-by: Prodyut Hazarika phazar...@appliedmicro.com
Acked-by: Stefan Roese s...@denx.de
Would be great if this could go into 2.6.32. Thanks.
Cheers,
Stefan
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...@amcc.com
Acked-by: Prodyut Hazarika phazar...@amcc.com
Acked-by: Loc Ho l...@amcc.com
Acked-by: Tirumala Reddy Marri tma...@amcc.com
Acked-by: Victor Gallardo vgalla...@amcc.com
Acked-by: Stefan Roese s...@denx.de
Cheers,
Stefan
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Hi Jeff,
On Thursday 03 December 2009 07:21:56 Jeff Hane wrote:
I'm trying to get interrupts working for my PCI device on a 460ex and
am having problem. My ISR never triggers.
Which 460EX board is this? Canyonlands or some custom board?
I'm new to PCI(and ppc) and LDD said that I could
On Thursday 03 December 2009 20:39:00 Jeff Hane wrote:
Can you clarify:
1. 460EX is your PCI host CPU?
yes. We are using a canyonlands board with 460ex.
PCI works on Canyonlands without any problems. I just tested latest Linux
release (2.6.32) with an PCI USB card:
-bash-3.2# uname -a
On Wednesday 23 December 2009 08:52:23 tma...@amcc.com wrote:
From: Tirumala Marri tma...@amcc.com
Please find some mostly nitpicking comments below.
BTW: Did you already test this on other 4xx platforms, like 440SPe or 405EX?
What are your plans here?
Signed-off-by: Tirumala Marri
On Sunday 15 February 2009, Josh Boyer wrote:
On Sun, Feb 15, 2009 at 05:31:40AM -0800, Felix Radensky wrote:
What about 4xx SPI driver ? Is it planned for inclusion in 2.6.30 ?
I really hope so. I've Acked it twice now I think. However, that needs
to go in through the SPI tree, which
On Wednesday 25 February 2009, Adish Kuvelker wrote:
I am developing a Host Controller Driver for the PPC405EX based board. I
have a OTG controller on it, which I have to configure as Host Controller
and thus I am witting a HCD for the same. I am stuck at the Control stage
wherein although my
On Wednesday 25 February 2009, Stefan Roese wrote:
On Wednesday 25 February 2009, Adish Kuvelker wrote:
I am developing a Host Controller Driver for the PPC405EX based board. I
have a OTG controller on it, which I have to configure as Host Controller
and thus I am witting a HCD for the same
On Wednesday 11 March 2009, Valentine Barshak wrote:
I've been looking at the docs once again and actually I couldn't find an
explanation there. And I don't have that e-mail from AMCC support
that I got a while back regarding the issue anymore.
There might have been some misunderstanding.
On Thursday 12 March 2009, Benjamin Herrenschmidt wrote:
On Thu, 2009-03-12 at 07:02 +0100, Stefan Roese wrote:
I'll apply the U-Boot patch today. But as Josh pointed out, we should
try to
find a way for the bootwrapper to work in all cases.
uboot is passing some kind of bt_t
On Thursday 12 March 2009, Benjamin Herrenschmidt wrote:
On Thu, 2009-03-12 at 09:05 +0100, Stefan Roese wrote:
Both is possible. Older U-Boot versions only passed the bd_t struct to
the kernel. For those U-Boot's the wrapper is needed. More recent U-Boot
versions support passing a device
On Thursday 12 March 2009, Josh Boyer wrote:
Yes, that's also how I use it on canyonlands... now, the wrapper could
probably be used to look at the bd_t anyways, no ?
Sure.
Do newer U-Boot versions pass both the dtb and the bd_t?
Both is possible. The user can choose by using different
I just noticed that physmap_of can't handle multiple devices of different type
described in one device node. For example the Intel P30 48F4400 (64MByte)
consists internally of 2 non-identical NOR chips. So a simple
fl...@0,0 {
#address-cells = 1;
On Monday 23 March 2009, Grant Likely wrote:
On Mon, Mar 23, 2009 at 4:51 AM, Stefan Roese s...@denx.de wrote:
I just noticed that physmap_of can't handle multiple devices of different
type described in one device node. For example the Intel P30 48F4400
(64MByte) consists internally of 2
On Tuesday 24 March 2009, Grant Likely wrote:
Sounds to me like a physmap_of driver bug. I don't think there is any
advantage in changing the partition syntax since concatenated flash
will always be used as a single device. It doesn't make any sense to
try and span partitions over two
On Tuesday 24 March 2009, Grant Likely wrote:
OK, in the example above such a spanning partition is not so likely. But
think about my original example, the Intel P30 with two different cfi
compatible chips on one die. Here a partition spanning over both devices
is very likely.
I agree.
On Wednesday 25 March 2009, Grant Likely wrote:
This case really does sound like a driver bug and that the existing
cfi-flash binding is sufficient to describe the hardware. IIUC, when
all the flash chips are of the same type the physmap_of driver should
be smart enough to detect each of
;
reg = 0 0x 0x0200
0 0x0200 0x0200;
bank-width = 2;
partit...@0 {
label = test-part1;
reg = 0 0x0400;
};
};
Signed-off-by: Stefan Roese s
,
factor out the MTD stuff and move it to
Documentation/powerpc/dts-bindings/. Remember to cc: the
devicetree-disc...@ozlabs.org list when you post the binding
documentation.
OK, will do.
Signed-off-by: Stefan Roese s...@denx.de
CC: Grant Likely grant.lik...@secretlab.ca
---
drivers/mtd
This patchset adds support to handle multiple non-identical chips in one
flash device tree node. It also adds concat support to physmap_of. This
makes it possible to support e.g. the Intel P30 48F4400 chip which
internally consists of 2 non-identical NOR chips on one die. Additionally
partitions
;
reg = 0 0x 0x0200
0 0x0200 0x0200;
bank-width = 2;
partit...@0 {
label = test-part1;
reg = 0 0x0400;
};
};
Signed-off-by: Stefan Roese s
Signed-off-by: Stefan Roese s...@denx.de
CC: Grant Likely grant.lik...@secretlab.ca
---
Documentation/powerpc/booting-without-of.txt | 89 +++-
Documentation/powerpc/dts-bindings/mtd-physmap.txt | 63 ++
2 files changed, 75 insertions(+), 77 deletions
This property is unused. It's not handled as all by the physmap_of
driver. So let's remove it from the documentation.
Signed-off-by: Stefan Roese s...@denx.de
CC: Grant Likely grant.lik...@secretlab.ca
---
Documentation/powerpc/dts-bindings/mtd-physmap.txt |3 ---
1 files changed, 0
Signed-off-by: Stefan Roese s...@denx.de
CC: Grant Likely grant.lik...@secretlab.ca
---
Documentation/powerpc/dts-bindings/mtd-physmap.txt | 20 +++-
1 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/mtd-physmap.txt
b
Now that the 4xx NAND driver is available again in arch/powerpc, let's
enable it on Sequoia. This patch also disables the early debug messages
(CONFIG_PPC_EARLY_DEBUG) in the Sequoia defconfig.
Signed-off-by: Stefan Roese s...@denx.de
---
arch/powerpc/boot/dts/sequoia.dts | 22
On Tuesday 07 April 2009, Scott Wood wrote:
Stefan Roese wrote:
This property is unused. It's not handled as all by the physmap_of
driver. So let's remove it from the documentation.
Signed-off-by: Stefan Roese s...@denx.de
CC: Grant Likely grant.lik...@secretlab.ca
The device tree
On Tuesday 07 April 2009, Grant Likely wrote:
Phy address 0 is the broadcast address. All phys will usually respond
to address 0 accesses.
Not all. Some (e.g. LXT971) can be used at this address. But you're correct,
it's definitely a bad idea to use 0 as an PHY address.
Not sure how the
On Wednesday 08 April 2009, Eddie Dawydiuk wrote:
I found the ibm_newemac driver(2.6.29) makes the assumption that the
bootloader has already configured the tx enable pin as it is a
multiplexed pin. Unfortuantley I am not using U-Boot and our minimal
bootloader does not do this. After
On Wednesday 08 April 2009, Grant Likely wrote:
I would like to eventually submit our changes for upstream support.
Based on this would you recommend ensuring tx enable is configured
properly in the initialization of the ibm_newemac driver or the platform
initialization?
This GPIO
Hi Sun,
On Tuesday 14 April 2009, SunNeo wrote:
My platform uses the MICRON MT47H256M8THN DDRII SDRAM and the DDRII SDRAM
is soldered on the board.
As I said, my board was similar with Kilauea evb, so I created my
configuration header file from Kilauea's at U-Boot. In the configuration
On Sunday 12 April 2009, Grant Likely wrote:
On Tue, Apr 7, 2009 at 2:39 AM, Stefan Roese s...@denx.de wrote:
This patch adds support to handle multiple non-identical chips in one
flash device tree node. It also adds concat support to physmap_of. This
makes it possible to support e.g
On Sunday 12 April 2009, Grant Likely wrote:
+ info = kzalloc(sizeof(struct of_flash) +
+ sizeof(struct of_flash_list) * count, GFP_KERNEL);
+ if (!info)
+ goto err_out;
+
+ mtd_list = kzalloc(sizeof(struct mtd_info) * count,
This patchset adds support to handle multiple non-identical chips in one
flash device tree node. It also adds concat support to physmap_of. This
makes it possible to support e.g. the Intel P30 48F4400 chip which
internally consists of 2 non-identical NOR chips on one die. Additionally
partitions
;
reg = 0 0x 0x0200
0 0x0200 0x0200;
bank-width = 2;
partit...@0 {
label = test-part1;
reg = 0 0x0400;
};
};
Signed-off-by: Stefan Roese s
It's easier to find bindings descriptions in separate files. So let's factor out
the MTD physmap bindings into Documentation/powerpc/dts-bindings/mtd-physmap.txt
to not clutter booting-without-of.txt more.
Signed-off-by: Stefan Roese s...@denx.de
Acked-by: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Stefan Roese s...@denx.de
CC: Grant Likely grant.lik...@secretlab.ca
---
Changes in ver3:
- Removed reference to Intel P30 parts
- Added exact chip compatible property for best practice.
Documentation/powerpc/dts-bindings/mtd-physmap.txt | 19 ++-
1 files changed
On Thursday 16 April 2009, Artem Bityutskiy wrote:
On Thu, 2009-04-16 at 14:05 +0200, Stefan Roese wrote:
This patchset adds support to handle multiple non-identical chips in one
flash device tree node. It also adds concat support to physmap_of. This
makes it possible to support e.g
On Thursday 16 April 2009, Grant Likely wrote:
Signed-off-by: Stefan Roese s...@denx.de
Reviewd-by: Grant Likely grant.lik...@secretlab.ca
Yup, still looks good to me. What boards has this been tested on?
I tested this version on PPC405EX Kilauea equipped only one standard
Spansion
On Thursday 16 April 2009, Grant Likely wrote:
Yup, still looks good to me. What boards has this been tested on?
I tested this version on PPC405EX Kilauea equipped only one standard
Spansion S29GL512 NOR chip. And a slightly modified version on an MPC8360
board (kmeter1) which is
On Wednesday 22 April 2009, David Brownell wrote:
On Thursday 08 January 2009, Stefan Roese wrote:
This adds a SPI driver for the SPI controller found in the IBM/AMCC
4xx PowerPC's.
Note that given some patches now in the mm tree, this needs
something like the appended fixup. Some common
implies 64-bit
wide memory.
Signed-off-by: Valentine Barshak vbars...@ru.mvista.com
Signed-off-by: Steven A. Falco sfa...@harris.com
Acked-by: Stefan Roese s...@denx.de
Thanks.
Best regards,
Stefan
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On Wednesday 30 January 2008, Stefan Roese wrote:
On Wednesday 30 January 2008, Sean MacLennan wrote:
There seems to be a byte order conflict between the u-boot and Linux
ndfc drivers.
u-boot has the following:
/* The NDFC uses Smart Media (SMC) bytes order*/
ecc_code[0] = p
On Friday 01 February 2008, Stefan Roese wrote:
So the SMC byte ordering is selected and it should match the version used
in U-Boot. In Linux the swapping is done in nand_ecc.c.
Seems that I was incorrect here. Tests showed that writing from Linux and
then reading back from U-Boot results
On Wednesday 06 February 2008, Jeff Garzik wrote:
Jeff, any chance this can get into .25 soon? I have another patch
queued up behind this one that requires it, and I don't see it in any
of your trees or branches.
Or, if you aren't opposed, I can take it through Paul's tree with your
With the removal the the rgmii-interface device_type property from the
dts files, the newemac driver needs an update to only rely on compatible
property.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
Acked-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
drivers/net/ibm_newemac/rgmii.c |1
On Sunday 03 February 2008, Imre Kaloz wrote:
Signed-off-by: Imre Kaloz [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/taishan.dts | 33 +++-
arch/powerpc/configs/taishan_defconfig | 89
++-- 2 files changed, 116 insertions(+), 6
deletions(-)
diff
Commit 2f569afd9ced9ebec9a6eb3dbf6f83429be0a7b4 (CONFIG_HIGHPTE vs.
sub-page page tables.) breaks compilation of arch/ppc since it
introduces the pgtable_t type which was not added to arch/ppc.
This patch now adds the missing typedef.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
include
ethernet ports are under heavy load.
Signed-off-by: Wolfgang Ocker [EMAIL PROTECTED]
Thanks, looks good.
Acked-by: Stefan Roese [EMAIL PROTECTED]
Best regards,
Stefan
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On Tuesday 19 February 2008, Jean Delvare wrote:
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index b61f56b..44c0984 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -244,7 +244,6 @@ config I2C_PIIX4
config I2C_IBM_IIC
Since the 4xx PCIe driver checks for 405ex compatibility, the
PCIe interface was not detected as it is currently defined as
405exr compatible. This patch changes it to 405ex.
The 405EX and 405EXr are identical exept that the 2nd PCIe and the
2nd EMAC interfaces are missing.
Signed-off-by: Stefan
On Wednesday 20 February 2008, Josh Boyer wrote:
Since the 4xx PCIe driver checks for 405ex compatibility, the
PCIe interface was not detected as it is currently defined as
405exr compatible. This patch changes it to 405ex.
The 405EX and 405EXr are identical exept that the 2nd PCIe and
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
I removed some whitespace warning in this version thanks to checkpatch.
arch/powerpc/boot/dts/canyonlands.dts | 398 +
1 files changed, 398 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/canyonlands.dts | 398 +
1 files changed, 398 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/canyonlands.dts
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b
Tested on AMCC Canyonlands eval board.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/sysdev/ppc4xx_pci.c | 114 ++
arch/powerpc/sysdev/ppc4xx_pci.h | 59 +++
2 files changed, 173 insertions(+), 0 deletions(-)
diff --git
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/configs/canyonlands_defconfig | 721
1 files changed, 721 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/configs/canyonlands_defconfig
diff --git a/arch/powerpc/configs
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
Now the L1 cache is correct. Thanks, Olof
arch/powerpc/boot/dts/canyonlands.dts | 398 +
1 files changed, 398 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/canyonlands.dts
diff --git
This patch changes the katmai (440SPe) L1 cache size to 32k. Some
whitespace issues are cleaned up too.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/katmai.dts | 58 +++---
1 files changed, 29 insertions(+), 29 deletions(-)
diff --git
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
And now the I2C device-types are removed. Sorry for the mail-flood.
arch/powerpc/boot/dts/canyonlands.dts | 393 +
1 files changed, 393 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts
405EX(r) has SDR0_MFR[E0CS/E1CS] set after reset. This selects
the internal loopback mode. Clear these bits so that both EMACs
don't use loopback mode as default.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
I'm not sure if this should be done here in the board platform code
On Friday 22 February 2008, Benjamin Herrenschmidt wrote:
On Fri, 2008-02-22 at 09:32 +0100, Stefan Roese wrote:
405EX(r) has SDR0_MFR[E0CS/E1CS] set after reset. This selects
the internal loopback mode. Clear these bits so that both EMACs
don't use loopback mode as default.
Signed-off
On Friday 22 February 2008, Josh Boyer wrote:
On Fri, 22 Feb 2008 09:32:12 +0100
Stefan Roese [EMAIL PROTECTED] wrote:
405EX(r) has SDR0_MFR[E0CS/E1CS] set after reset. This selects
the internal loopback mode. Clear these bits so that both EMACs
don't use loopback mode as default
On Saturday 23 February 2008, Paul Mackerras wrote:
Stefan Roese writes:
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
That's a very uninformative commit message. :)
How about putting a brief description of the AMCC 460 family in here?
You're right. I was a little bit lazy. :)
I'll add
Canyonlands is the AMCC 460EX eval board, featuring nearly all of the 460EX
interfaces:
- 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane)
- 2 * GBit Ethernet with TCP/IP acceleration
- USB 2.0 Host/Device OTG and Host interface
- SATA port
Signed-off-by: Stefan Roese [EMAIL PROTECTED
(one 4-lane, one 1-lane)
- 2 * GBit Ethernet with TCP/IP acceleration
- USB 2.0 Host/Device OTG and Host interface
- SATA controller
- Optional security feature
460GT (only changes to 460EX):
- 4 * GBit Ethernet with TCP/IP acceleration
- RapidIO
- No SATA
- No USB
Signed-off-by: Stefan Roese
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
And now the I2C device-types are removed. Sorry for the mail-flood.
arch/powerpc/boot/dts/canyonlands.dts | 393 +
1 files changed, 393 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/configs/canyonlands_defconfig | 721
1 files changed, 721 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/configs/canyonlands_defconfig
diff --git a/arch/powerpc/configs
.
Unfortunately all IBM/AMCC chips currently supported in this PCIe driver need
a different reset-/init-sequence.
Tested on AMCC Canyonlands eval board.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/sysdev/ppc4xx_pci.c | 114 ++
arch/powerpc
On Friday 29 February 2008, Josh Boyer wrote:
On Sat, 23 Feb 2008 22:08:01 +0100
Stefan Roese [EMAIL PROTECTED] wrote:
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
And now the I2C device-types are removed. Sorry for the mail-flood.
arch/powerpc/boot/dts/canyonlands.dts | 393
This dts version has the following changes to the previous one:
- Remove linux,network-index from EMAC device nodes
- Fix spelling in IIC1 node
- Assign correct PCI interrupt (external IRQ2 is mapped to UIC1-0)
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts
On Tuesday 04 March 2008, Josh Boyer wrote:
Is anybody using Bamboo PCI support right now? Does it actually work?
I plugged in an old 3Com ethernet card tonight. Slot 0. It was
assigned dev #4 IRQ 25. Using the device tree as-is, I could see
interrupts happening in /proc/interrupts but
On Friday 22 February 2008, Valentine Barshak wrote:
Move the skb-ip_summed == CHECKSUM_PARTIAL part out of
emac_has_feature parameters.
Signed-off-by: Valentine Barshak [EMAIL PROTECTED]
Acked-by: Stefan Roese [EMAIL PROTECTED]
I think this is 2.6.25 material. I just stumbled over
Add ibm,tah to the compatible matching table of the ibm_newemac
tah driver. The type tah is still preserved for compatibility reasons.
New dts files should use the compatible property though.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
drivers/net/ibm_newemac/tah.c |4
1 files
This patch adds TAH (TCP/IP Acceleration Hardware) support to the
taishan 440GX dts. It depends on the NEWEMAC/tah patch that adds the
compatible ibm,tah property to the matching table.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/taishan.dts | 13 +
1
. If the
default reserved multicast MAC address is not programmed into the
GAHT[1-4] registers this Pause packet will be dropped by PPC EMAC and no
Flow Control will be done.
Signed-off-by: Pravin M. Bathija [EMAIL PROTECTED]
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
drivers/net/ibm_newemac/core.c
On Friday 14 March 2008, Prakash S wrote:
Sorry if I am posting this in a wrong forum. I am looking at RISC watch
debugger for our PPC board. We are currently trying to estimate the cost
and effort of porting a vxworks image to a linux based image. Does any of
you know the approximate cost
not defined.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
Documentation/powerpc/booting-without-of.txt | 17 -
drivers/net/ibm_newemac/mal.c| 20 ++--
drivers/net/ibm_newemac/mal.h|2 ++
3 files changed, 32 insertions(+), 7
in arch/ppc
with small modifications.
Tested on AMCC Taishan 440GX and Canyonlands 460EX.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/Kconfig |3 +
arch/powerpc/platforms/44x/Kconfig |2 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev
This patch adds the L2 cache node to the Taishan 440GX dts file.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/taishan.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/taishan.dts
b/arch/powerpc/boot/dts
On Wednesday 19 March 2008, David Gibson wrote:
On Tue, Mar 18, 2008 at 02:37:46PM +0100, Stefan Roese wrote:
This patch adds the L2 cache node to the Taishan 440GX dts file.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/taishan.dts | 10 ++
1
On Tuesday 18 March 2008, Segher Boessenkool wrote:
+ L2C0: [EMAIL PROTECTED] {
+ compatible = ibm,l2-cache-440gx, ibm,l2-cache;
+ dcr-reg = 20 8 /* Internal SRAM DCR's */
+ 30 8; /* L2 cache DCR's */
The unit
The patch adds the Glacier dts. The Glacier is nearly identical to the
Canyonlands (460EX). Here the differences:
- 4 ethernet ports instead of 2
- no SATA port
- no USB port
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/glacier.dts | 464
The patch adds the Glacier dts. The Glacier is nearly identical to the
Canyonlands (460EX). Here the differences:
- 4 ethernet ports instead of 2
- no SATA port
- no USB port
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
This version adds amcc,glacier to the toplevel compatible property
Hi Stephan,
On Thursday 20 March 2008, Stephen Rothwell wrote:
Just a few trivial things ...
Thanks. Will fix and resubmit.
Best regards,
Stefan
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On Thursday 20 March 2008, Benjamin Herrenschmidt wrote:
On Tue, 2008-03-18 at 14:36 +0100, Stefan Roese wrote:
This patch adds support for the 256k L2 cache found on some IBM/AMCC
4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
which currently only adds the L2 cache
On Thursday 20 March 2008, David Gibson wrote:
You did build your device tree with -b 0, didn't you?
Ugh.. I really need to fix dtc to pick the default boot cpu value more
sensibly, don't I.
I didn't specify -b 0. This shouldn't be neccessary on a single
processor system ! After all
Currently Haleakala uses the Kilauea platform code. This patch adds
haleakala to the compatible property, in case later kernel versions
will introduce a Haleakala platform code.
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/haleakala.dts |2 +-
1 files changed, 1
On Friday 21 March 2008, Benjamin Herrenschmidt wrote:
On Wed, 2008-03-19 at 17:15 +0100, Stefan Roese wrote:
+ [EMAIL PROTECTED] {
+ device_type = cpu;
+ model = PowerPC,460GT;
+ reg = 0;
I wonder if we
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