Hi Michael,
On Fri, Jan 31, 2014 at 03:18:30PM -0800, David Hawkins wrote:
1. Peripheral board DMA (board-to-board)
2. Peripheral board DMA to host memory.
3. Host (root complex) DMA.
As far as verification of your custom peripheral board FPGA IP is
concerned, if I was a customer, and you had
Hi Michael,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an e500v2, I had no success at all
so far.
Whenever I want to benchmark
Hi S.Saravanan,
You'll have two drivers;
* The root-complex.
This is a standard PCIe driver, so you'll just follow convention
there
* The end-point driver.
This driver needs to use the PCIe bus, but its not responsible
for the PCIe bus in the way a root-complex is. The driver
Hi S.Saravanan,
I successfully mapped the Programmable Interrupt Controller registers
in the EP to the PCI space. Thus now I can write the shared message
interrupt registers in the EP from the RC over PCI.
Excellent.
But I am facing the following problems now.
1) In my driver at EP, to
Hi S.Saravanan,
Root complex's would normally interrupt a device via a PCIe write
to a register in a BAR on the end-point (or in extended configuration
space registers depending on the hardware implementation).
MPC8640 End point implements only the Type 0 header (Page 1116) . The
header
Hi S.Saravanan,
I have a custom board with four MPC8640 nodes connected over
a transparent PCI express switch . In this configuration one node is
configured as host(Root Complex) and others as agents(End Point). Thus
the legacy PCI software works fine . However the mainline kernel lacks
any
Hi Pete,
For those that are interested, we did figure out what was going on.
Turns out that the clock buffer driving the PCI connector was, well,
less than adequate. With some cards, the load on the clock line was
large enough that the clock was in horrible shape. Fixing the clock
line and
Hi Pete,
On Mon, Aug 5, 2013 at 11:25 AM, Anatolij Gustschin ag...@denx.de wrote:
Maybe this card needs bigger delay to respond after PCI reset. You can
try to re-build U-Boot with defined CONFIG_PCI_BOOTDELAY. Use 1000
for CONFIG_PCI_BOOTDELAY in the first step and if detection works,
try to
Hi Pete,
1. Have you checked the power supplies on the PCI board?
PCI boards can be powered from 3.3V or 5V, or both. I've had
old PCs that only supply one or the other rail, and various
evaluation boards that only supply 3.3V.
If you can put together a working x86 setup that
Hi Pete,
Actually, before going down that route, I would get a PCI extender
that you can use to trace the traffic with your board. Does the
network card use 33MHz or 66MHz?
I wonder if something like this board:
http://www.logicsupply.com/products/pci122_dflex
can be used to make a single
Hi Pete,
On Mon, Aug 5, 2013 at 4:07 PM, Peter LaDow pet...@gocougs.wsu.edu wrote:
However, replacing the 82540 based card with either a 3com 3C905TXM or
the Netgear FA331, there is no response on the 0x10 IDSEL line. Thus
it appears these cards are NOT responding to configuration reads. I
Using PMC -PCI Adapter card ,i have interfaced my *PowerPC MPC8280*
(which is configured as *PCI bridge*) as agent to personal computer.
when this setup having MPC8280 card with *powered ON* and connected to
*PC* .*PC* is getting hanged while system is booting up. I am finding
problem when this
Hi Bruce,
This isn't really a Linux PPC question, but this is the smartest mailing
list I know for asking PPC hardware questions, so here goes.
We're using an MPC8308 and want to use the DMA engine to move data in and
out of an FPGA hanging on the local bus. Our bandwidth/local bus burden
Hi Bruce,
Read my MPC8349EA UPM setup notes and see if you have used
similar settings (I assume the local bus UPMs are similar):
I found you paper interesting. I didn't have a problem with my UPM
settings, single beat reads and writes worked just fine, however it did
tickle my memory and
Hi Ajith,
I have come across this forum, and I have a question. I am working on
PCI device driver, I am trying to insert the pci card in to the pci slot
of the main computer, I am finding a problem here, when I insert the
card in to the pci slot, my pci device ID and vendor Id are not getting
Hi Jeff,
I'm trying to get interrupts working for my PCI device on a 460ex and
am having problem. My ISR never triggers.
I'm new to PCI(and ppc) and LDD said that I could read the config reg
INTURRUPT_LINE to get the interrupt assigned to my PCI device. Well,
this always reads zero.
Hi Ira,
When Linux is assigning BARs and IRQs, it writes the BAR addresses to
the PCI cards, but does not write the IRQ. This was my experience with
PCI hotplug.
Ooh, subtle.
Bottom line is; if the IRQ field of lspci is 0, then you
need to figure out that problem first :)
In the PCI
Hi Wolfgang,
In message 4b1816f9.1020...@ovro.caltech.edu you wrote:
Yep. It might require enabling a PCI subsystem in U-Boot.
I recall playing with a Yosemite board and a PCI card,
but I forget whether I had to do anything to enable
PCI configuration space setup. Post a question to the
U-Boot
Hi Felix,
On a custom MPC8536 board running linux-2.6.31,
I'd like to load FPGA code from linux and then rescan
PCI-E bus to discover FPGA device. Is that possible ?
When linux boots FPGA is not loaded, so initial PCI
scan does not detect it.
I've tried playing with /sys/bus/pci/rescan and
Hi Felix,
On my custom MPC8536 based board running 2.6.31 kernel
FPGA is connected via x2 PCI-E lane. FPGA is identified
during PCI scan and is visible via lspci.
:01:00.0 Class ff00: Altera Corporation Unknown device 0004 (rev 01)
Subsystem: Altera Corporation Unknown device 0004
Hi Leon,
I'll be testing the design tomorrow on the reference board, I'll
report results in this thread.
Interesting.
Looking forward to the results.
Design works as expected on the now slightly modified MPC8313E-RDB
board.
That's great!
Kudos to David.
I'm sure you would have come up
Hi Leon,
Most MPC8xxx board designs I have seen suffer from this possible dead lock:
- NOR Flash is put in erase mode or write mode
- Hardware watchdog triggers
- HRESET# is asserted by the processor, during which the configuration
words are read from NOR Flash.
Either
HRESET# is not attached
Hi Leon,
Most MPC8xxx board designs I have seen suffer from this possible dead
lock:
- NOR Flash is put in erase mode or write mode
- Hardware watchdog triggers
- HRESET# is asserted by the processor, during which the configuration
words are read from NOR Flash.
Either
HRESET# is not attached
Hi,
my processor is MPC8247, on Linux 2.6.11
in MPC8247 manual reference, the interrupt of DMA unit belonged PCI bridge.
that is different from SDMA and IDMA. through i do not know what 's the
different. heard SDMA is used to transfer between CPM and 60x. DMA is used
to transfer between 60x
Hi,
Now I attempt to fetch data from peripheral device to SDRAM, and it has been
successed
but how the DMA controller know the data bandwidth of src and dest.
for example, if i get a 16bits data with a 32bits bus, and other 16bits will
be set high
and data will fetched into cache line of dma,
Hi all,
You are assuming the PCI memory space is prefetchable( no side effect)
for DMA. Is it possible that DMA is from non-prefetchable memory space?
This should be a safe assumption for this driver. Remember, this
driver just does offload memcpy, from one region to another. So the
PCI
Would you like some sort of summary of this info for a commit
message?
That's probably overkill. I just want a sentence or two that tells
someone looking at the code casually that the behavior of reading PCI
memory might be different than what they expect.
Ok, will-do.
Would you like us
Can you give me an example of non-PCI memory that would be
non-prefetchable that you'd like us to try? We can see if our
host CPUs have an area like that ... we just need to know
what device to look for first :)
You can mark the pci inbound window on the 83xx as non-prefetchable
(assuming
You can mark the pci inbound window on the 83xx as non-prefetchable
(assuming 83xx is host). On a x86 host I doubt there is any easy way
to get non-prefetchable memory.
One more note; we don't have access to a host-mode MPC8349EA,
our boards are all targets.
Cheers,
Dave
Can you give me an example of non-PCI memory that would be
non-prefetchable that you'd like us to try? We can see if our
host CPUs have an area like that ... we just need to know
what device to look for first :)
You can mark the pci inbound window on the 83xx as non-prefetchable
(assuming 83xx
Hi Timur,
Would you like some sort of summary of this info for a commit
message?
That's probably overkill. I just want a sentence or two that tells
someone looking at the code casually that the behavior of reading PCI
memory might be different than what they expect.
Could you help us with
Hi Timur,
PRC_RM - PCI read multiple
The default PCI read command used by the DMA controller is
PCI Read (PCI command 6h). When the burst length is 32-bytes
or longer, PCI Read Line (PCI command Eh) is used (undocumented
feature of the controller). Using PCI read multiple
(PCI
Timur Tabi wrote:
David Hawkins wrote:
Ira will add your comment to the body of the code near
the PRC_RM command and submit a new patch.
I'd rather have it near the top where people can see it.
Looks like Ira had the same thought :)
Dave
How about FIFO RAM case?
If the FIFO has a fixed address, then according to
the user guide, the DMA controller won't generate
a burst transaction to it.
We can try confirming this if you'd like.
Cheers,
Dave
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Linuxppc-dev mailing list
Hi Dave,
For the DMA PCI read/line/multi-line is outbound transaction.
So according to your experiment, the 8349 PCI controller(as master)
attemp to streaming/combining the outbound transaction(treated as
prefetchable space).
Yep, with the MPC8349EA configured as a PCI Target,
and operating
Hi Grant,
I like this a lot. I need to do much the same thing on one of my
platforms, so I'm going to use your patch as my starting point. Have
you made many changes since you posted this version of your patch?
I'd like to collaborate on the development and help to get it
mainlined.
In my
Hi Grant,
Thanks David. I haven't looked closely at the xilinx pci data sheet
yet, but I don't expect too many issues in this area. As you say, it
won't take much to code it up. I'll be poking my VHDL engineer to
make it do what I want it to. :-)
The key aspects of the core will be that
Hi Grant,
Hmmm, I hadn't thought about this. I was intending to use the
Virtex's memory region for all virtio, but if I can allocate memory
regions on both sides of the PCI bus, then that may be best.
Sounds like you can experiment and see what works best :)
If you use
a PCI Target only
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