Hi,
On a custom board based on MPC8260 I have to replace end-of-life
2GB Sandisk mDoc H3 by other storage device of comparable density.
The most natural choice seems to be NAND connected to UPM.
However FSL UPM NAND driver in mainline does not support MPC82xx.
I have several questions in this
Hi Zhao,
From: Li Yang leoli at freescale.com
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the
Hi Zhao,
From: Li Yang leoli at freescale.com
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the
Interrupt handler in MPC8xxx GPIO driver is missing the call
to PIC EOI (end of interrupt) handler. As a result, at least
on 85XX systems, GPIO interrupt is delivered only once. This
patch adds the missing EOI call. Tested on custom P1022 board.
Signed-off-by: Felix Radensky fe...@embedded
Hi Grant,
On 09/29/2011 08:27 PM, Grant Likely wrote:
On Wed, Sep 28, 2011 at 08:52:30PM +, Tabi Timur-B04825 wrote:
On Tue, Sep 27, 2011 at 1:29 PM, Grant Likelygrant.lik...@secretlab.ca wrote:
The solution is to make the gpio driver register as a regular
interrupt handler, and not as
() is invoked
3 times with same hardware irq number. The result is interrupt
storm, mpc8xxx_gpio_irq_cascade() is invoked indefinitely.
What would be the best way to fix the problem ?
Thanks.
Felix Radensky.
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Hi Grant,
On 09/27/2011 09:29 PM, Grant Likely wrote:
On Tue, Sep 27, 2011 at 04:59:28PM +0300, Felix Radensky wrote:
Hi,
Looks like 8xxx GPIO driver cannot properly handle interrupts
when multiple GPIO controllers exist in the system.
On Freescale P1022 there are 3 GPIO controllers. All 3
Hi,
DTS bindings document for mpc8xxx GPIOs implies that to use GPIO as IRQ
one should specify GPIO controller node and GPIO number in device tree
node,
like this:
funkyfpga@0 {
compatible = funky-fpga;
...
interrupts = 9 2;
interrupt-parent = gpio2;
};
Hi,
On 07/31/2011 04:59 PM, Tabi Timur-B04825 wrote:
Felix Radensky wrote:
What happens when I load my driver is single execution of interrupt
handler
followed by system freeze. Even if I call disable_irq() in interrupt
handler the
system still freezes.
I don't know anything
Hi,
I'm running kernel 3.0 on a custom board based on Freescale P1022.
The interrupt line of on-board FPGA is connected to GPIO2_9. FPGA
IRQ is level, active low. The GPIOs are mapped like this:
GPIOs 160-191, /soc@ffe0/gpio-controller@f200:
GPIOs 192-223,
Hi Timur,
On 07/31/2011 04:59 PM, Tabi Timur-B04825 wrote:
Felix Radensky wrote:
What happens when I load my driver is single execution of interrupt
handler
followed by system freeze. Even if I call disable_irq() in interrupt
handler the
system still freezes.
I don't know
Hi Wolfgang,
On 07/31/2011 06:19 PM, Wolfgang Grandegger wrote:
On 07/31/2011 12:38 PM, Felix Radensky wrote:
Hi,
I'm running kernel 3.0 on a custom board based on Freescale P1022.
The interrupt line of on-board FPGA is connected to GPIO2_9. FPGA
IRQ is level, active low. The GPIOs are mapped
Hi Wolfgang,
On 07/31/2011 08:49 PM, Wolfgang Grandegger wrote:
Hi Felix,
On 07/31/2011 05:51 PM, Felix Radensky wrote:
Hi Wolfgang,
On 07/31/2011 06:19 PM, Wolfgang Grandegger wrote:
On 07/31/2011 12:38 PM, Felix Radensky wrote:
Hi,
I'm running kernel 3.0 on a custom board based
On P1022DS both ethernet controllers are connected to RGMII PHYs
accessible via MDIO bus. Remove fixed-link property from ethernet
nodes as they only required when fixed link PHYs without MDIO bus
are used.
Signed-off-by: Felix Radensky fe...@embedded-sol.com
---
arch/powerpc/boot/dts
Hi,
On 06/22/2011 08:12 PM, Felix Radensky wrote:
Hi Timur,
On 06/22/2011 07:18 PM, Timur Tabi wrote:
Felix Radensky wrote:
What am I doing wrong ?
Can you debug the PHY driver to see if it's getting called and
trying to talk to
the PHY itself?
I'll do that tomorrow and report back
Hi,
On a custom P1022-based board I have SGMII PHY connected to eTSEC1.
PHY address is 0x1. Ethernet works fine in u-boot, but in linux
there's no link.
I have the following in my device tree:
mdio@24000 {
#address-cells = 1;
#size-cells = 0;
Hi Timur,
On 06/22/2011 07:18 PM, Timur Tabi wrote:
Felix Radensky wrote:
What am I doing wrong ?
Can you debug the PHY driver to see if it's getting called and trying to talk to
the PHY itself?
I'll do that tomorrow and report back.
Thanks.
Felix
This patch extends NDFC driver to support all 4 chip selects
available in NDFC NAND controller. Tested on custom 460EX board
with 2 chip select NAND device.
Signed-off-by: Felix Radensky fe...@embedded-sol.com
---
I'd appreciate some testing on 44x boards with multiple NAND
devices, like bamboo
Hi Poonam,
Thanks for the confirmation.
Felix.
On 04/15/2011 09:27 AM, Kushwaha Prabhakar-B32579 wrote:
Added Linxppc-dev
-Original Message-
From: Aggrwal Poonam-B10812
Sent: Friday, April 15, 2011 11:47 AM
To: Felix Radensky
Cc: Kushwaha Prabhakar-B32579; leon.woestenb...@gmail.com
Hi,
Adding linux-mtd list to CC.
On 04/14/2011 10:06 AM, emre kara wrote:
Hi Scott, Roy.
Scott's "mtd: eLBC NAND: increase bus timeout to maximum" patch is excluded from kernel with Roy's "P4080/eLBC: Make Freescale elbc interrupt common to elbc devices"
: Monday, April 11, 2011 1:53 PM
To: Kushwaha Prabhakar-B32579
Cc: Leon Woestenberg; linuxppc-...@ozlabs.org; Mahajan Vivek-B08308;
Felix Radensky; Aggrwal Poonam-B10812; Gupta Maneesh-B18878
Subject: Re: Problem with mini-PCI-E slot on P2020RDB
Hello Kushwaha Prabhakar,
Our impression
. The problem was
fixed in board revision D. To use legacy interrupts one has to modify
pci-e nodes in device tree and add interrupt-map-mask and
interrupt-map properties.
Do you agree with this analysis ?
Felix.
-Original Message-
From: Felix Radensky [mailto:fe...@embedded-sol.com]
Sent
Hi,
On 04/12/2011 07:35 AM, Benjamin Herrenschmidt wrote:
On Tue, 2011-04-12 at 04:05 +, Aggrwal Poonam-B10812 wrote:
May be you can look at
http://old.nabble.com/Problem-with-mini-PCI-E-slot-on-P2020RDB-td26802038.html
Felix we do not have the atheros driver for 2.6.38 and the issue is
on P2020RDB
-Original Message-
From: Felix Radensky [mailto:fe...@embedded-sol.com]
Sent: Monday, April 11, 2011 7:16 PM
To: Kushwaha Prabhakar-B32579
Cc: Fabian Bertholm; Leon Woestenberg; linuxppc-...@ozlabs.org; Mahajan
Vivek-B08308; Aggrwal Poonam-B10812; Gupta Maneesh-B18878
Subject
Hi Leon,
I think there's a hardware problem with mini PCI-E slot
on P2020RDB related to legacy IRQ routing. See this
thread for details
http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg40037.html
You may have better luck with PCI-E slot and mini PCI-E to
PCI-E adapter.
Felix.
Hi Leon,
On 04/06/2011 11:58 PM, Leon Woestenberg wrote:
Hello Felix,
On Wed, Apr 6, 2011 at 10:49 PM, Felix Radenskyfe...@embedded-sol.com wrote:
I think there's a hardware problem with mini PCI-E slot
on P2020RDB related to legacy IRQ routing. See this
thread for details
Hi Ira,
I've successfully tested this version on P2020RDB,
with 10 threads per channel, 10 iterations per
thread.
Tested-by: Felix Radensky fe...@embedded-sol.com
Felix.
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https
Hi Ira,
On 03/01/2011 09:52 PM, Ira W. Snyder wrote:
On Tue, Mar 01, 2011 at 08:55:15AM -0800, Ira W. Snyder wrote:
[ big snip ]
I'd still like the bisect if you have a chance. I've re-reviewed the
patch series, and found the places that change register writes to the
controller.
The patch
Hi Ira,
I've tried your patches with linux-2.6.38-rc6 on P2020RDB.
DMA test fails with the following errors if threads_per_chan != 1
dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
dma0chan0-copy2: #0: test timed out
I've run the test like this:
modprobe dmatest
From:
Ira W. Snyder i...@ovro.caltech.edu
To:
Felix Radensky fe...@embedded-sol.com
CC:
linuxppc-...@ozlabs.org linuxppc-...@ozlabs.org
On Mon, Feb 28, 2011 at 01
Hi Ira,
Thank you very much Felix. The dmesg output shows that the controller
never got an interrupt for the second transaction. The patch below has
extra debugging information that may help determine why this happens.
Please apply it and re-run the test.
The last section of dmesg (after
Hi Ira,
On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
Hi Ira,
Thank you very much Felix. The dmesg output shows that the controller
never got an interrupt for the second transaction. The patch below has
extra debugging
Hi Ira,
On 03/01/2011 02:21 AM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
Hi Ira,
On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
Hi Ira,
Thank you very much Felix. The dmesg output
Hi Ira,
On 03/01/2011 02:21 AM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
Hi Ira,
On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
Hi Ira,
Thank you very much Felix. The dmesg output
Hi Ira,
On 01/25/2011 06:29 PM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 04:32:02PM +0200, Felix Radensky wrote:
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to perform
Hi,
I'm trying to use FSL DMA engine to perform DMA transfer from
memory buffer obtained by kmalloc() to PCI memory. This is on
custom board based on P2020 running linux-2.6.35. The PCI
device is Altera FPGA, connected directly to SoC PCI-E controller.
01:00.0 Unassigned class [ff00]: Altera
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to perform DMA transfer from
memory buffer obtained by kmalloc() to PCI memory. This is on
custom board based on P2020 running linux
Hi Timur,
There are currently no drivers in mainline for FSL eSPI controller and eSPI
flash.
They are present only in FSL BSP kernel. Do you think it makes sense to keep
DTS entries for something that is not supported ?
Felix.
On 7/3/2010 1:25 AM, Timur Tabi wrote:
Introduce basic support
Hi Kumar,
On 5/11/2010 3:36 PM, Kumar Gala wrote:
On May 10, 2010, at 2:15 PM, Felix Radensky wrote:
Fix legacy PCI-E interrupt mapping for PCI-E slot 0 of
P2020DS evaluation board. The patch is based on P2020DS
device tree from Freescale BSP for this board.
Signed-off-by: Felix Radensky
Fix legacy PCI-E interrupt mapping for PCI-E slot 0 of
P2020DS evaluation board. The patch is based on P2020DS
device tree from Freescale BSP for this board.
Signed-off-by: Felix Radensky fe...@embedded-sol.com
---
arch/powerpc/boot/dts/p2020ds.dts |8
1 files changed, 4 insertions
Hi Kumar,
On 4/27/2010 2:05 AM, Kumar Gala wrote:
Ben,
I've updated this to include this one additional patch for dealing with
CONFIG_RELOCATE on FSL-BookE ppc32
http://patchwork.ozlabs.org/patch/51011/
Can this patch also be included: http://patchwork.ozlabs.org/patch/50289/
Thanks.
Hi Anton,
On 4/15/2010 9:36 PM, Anton Vorontsov wrote:
This patch adds support for eTSEC 2.0 as found in P1020.
The changes include introduction of the group nodes for
the etsec nodes.
Signed-off-by: Sandeep Gopalpetsandeep.ku...@freescale.com
Signed-off-by: Anton
Hi Kumar,
On 4/9/2010 8:43 AM, Kumar Gala wrote:
On Apr 8, 2010, at 5:53 AM, Felix Radensky wrote:
Hi,
I've just noticed that ethernet nodes are missing in p1020rdb device tree.
Are there any known problems with ethernet controllers on p1020rdb ?
I'd say its not problems, its
Hi,
I've just noticed that ethernet nodes are missing in p1020rdb device tree.
Are there any known problems with ethernet controllers on p1020rdb ?
Thanks.
Felix.
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Hello Kenji-san,
Kenji Kaneshige wrote:
Felix, I think assigning hpXXsize at boot time is the simpler solution,
if it is acceptable workaround for you. And as Yinghai suggested in the
another email, removing slot's parent bridge first should be one of the
workaround. But the problem is
Hello, Kenji-san
Kenji Kaneshige wrote:
Felix Radensky wrote:
Hello, Kenji-san
Kenji Kaneshige wrote:
I misunderstood the problem.
My understanding was memory resource was not enabled even though
Linux set
the Memory Space bit in the command register. But it was not
correct. The
bridge
Hi Ben,
Benjamin Herrenschmidt wrote:
On Sun, 2010-03-28 at 12:13 +0300, Felix Radensky wrote:
I've tried Jesse's tree with Yinghai's patches, but they don't seem to help.
Memory for bridge is not allocated after insertion of hotplug device and
bus rescan. Attached dmesg output in case
Hello Kenj-san
Kenji Kaneshige wrote:
By the way, I think Yinghai's bridge resource reallocation patch series
might help you. It is in Jesse's PCI tree. Please take a look.
I've tried Jesse's tree on my custom board and on 460EX evaluation board
(Canyonlands). In both cases the kernel
Hello, Kenji-san
Kenji Kaneshige wrote:
I misunderstood the problem.
My understanding was memory resource was not enabled even though Linux
set
the Memory Space bit in the command register. But it was not correct. The
bridge memory window was marked unused and Linux didn't try to set Memory
Hello, Kenji-san
Kenji Kaneshige wrote:
I misunderstood the problem.
My understanding was memory resource was not enabled even though Linux
set
the Memory Space bit in the command register. But it was not correct. The
bridge memory window was marked unused and Linux didn't try to set Memory
Hello Kenji-san,
Kenji Kaneshige wrote:
Felix Radensky wrote:
Hello Kenji-san,
Kenji Kaneshige wrote:
I'm not sure, but I guess pci_setup_bridge() didn't update IO
base/limit
and Mem base/limit of the bridge (:00:02.0) because of the
following
lines.
static void pci_setup_bridge
Hello, Kenji-san
I think the device is expected to be ready to work if pci_enable_device()
returns without error. So I think pci_enable_device() should return an
error if it fails to enable the device (device is not ready to work). In
this case, detecting your bridge's failure seems PPC
Hello Kenji-san,
Kenji Kaneshige wrote:
I'm not sure, but I guess pci_setup_bridge() didn't update IO base/limit
and Mem base/limit of the bridge (:00:02.0) because of the following
lines.
static void pci_setup_bridge(struct pci_bus *bus)
{
struct pci_dev *bridge = bus-self;
Hi Alex,
Thanks a lot for replying.
Alex Chiang wrote:
* Felix Radensky fe...@embedded-sol.com:
The problem arises when device is plugged in after boot. After doing
echo 1 /sys/bus/pci/rescan
the device is identified, but bridge memory window is not allocated,
and reads from
Hi Ben,
Benjamin Herrenschmidt wrote:
Yes, we need to do a resource allocation pass, setup DMA, etc... and
that is not done in that manual rescan case I suppose. I have to look.
Part of the problem is that there is no proper hooks in the generic
PCI code that I know of for that, but I'll have
Hi Alex,
Resending, previous attempt was erroneously send as HTML.
Thanks a lot for replying.
Alex Chiang wrote:
* Felix Radensky fe...@embedded-sol.com:
The problem arises when device is plugged in after boot. After doing
echo 1 /sys/bus/pci/rescan
the device is identified, but bridge
Hi,
I'm running linux-2.6.33 on a custom board based on 460EX.
There's a PCI-PCI bridge on this board, PLX 6254, and a single
hot-pluggable device behind the bridge.
When this device is plugged in before system boots everything works
fine: bridge and device are properly recognized by kernel,
Hi,
We'd like to run Linux on core0 of P2020 and some bare metal application
running without OS
on core1. Is it possible to start this application from Linux ? I've
seen example of running 2 copies
of Linux in AMP mode, in which case both are started from u-boot. I'd
like to leave core1 in
Hi, Stef
Benjamin Herrenschmidt wrote:
On Wed, 2010-01-20 at 00:52 +0200, Felix Radensky wrote:
405XX - no
440EP - no
440GR - no
440EPx/440GRx - no
440GP - yes
440GX - yes
440SP - yes
440SPe - yes
460XX - yes
The distinction between these groups is pretty clear in the device trees
Benjamin Herrenschmidt wrote:
On Wed, 2010-01-13 at 10:18 +1100, Benjamin Herrenschmidt wrote:
On Tue, 2010-01-12 at 15:09 +0100, Stef van Os wrote:
This patch adds type 1 PCI transactions to 4xx PCI code, enabling the
discovery of
devices behind a PCI bridge.
Your patch
Hi Ben
Benjamin Herrenschmidt wrote:
On Tue, 2010-01-12 at 00:48 +0200, Felix Radensky wrote:
Maybe because the bus behind root P2P bridge is bus 0, and type 1
cycles are
needed for bus numbers greater than 0. That's what 460EX manual says.
Well, no... the bus behind the root P2P
Hi Stef,
Stef van Os wrote:
Hello Felix,
I had a problem similar to this on the 440GX, the PCI code was not
sending type 1 transactions when scanning behind bridges. Perhaps you
could try this:
Index: linux/arch/powerpc/sysdev/ppc4xx_pci.c
Hi Stef
Felix Radensky wrote:
Hi Stef,
Stef van Os wrote:
Hello Felix,
I had a problem similar to this on the 440GX, the PCI code was not
sending type 1 transactions when scanning behind bridges. Perhaps you
could try this:
Index: linux/arch/powerpc/sysdev/ppc4xx_pci.c
Hi, Ben
Benjamin Herrenschmidt wrote:
It seems I was wrong. I've manually applied the patch at the wrong
place. After patching the correct function
I'm not getting hard resets any more, which is a great improvement !
Thanks a lot, I really appreciate your help !
This is somewhat
Hi, Ben
Felix Radensky wrote:
Hi, Ben
Adding Feng Kan from AMCC to CC.
Benjamin Herrenschmidt wrote:
On Mon, 2009-12-28 at 12:51 +0200, Felix Radensky wrote:
Hi,
I'm running linux-2.6.33-rc2 on Canyonlands board. When PLX 6254
transparent PCI-PCI
bridge is plugged into PCI slot
Benjamin Herrenschmidt wrote:
On Sun, 2010-01-10 at 14:56 +0200, Felix Radensky wrote:
I now have a custom board with 460EX and the same PLX bridge, running
2.6.23-rc3
Things look better here, as u-boot is now able to properly detect PLX
and device behind
it, but kernel still has problems
Hi, Ben
Adding Feng Kan from AMCC to CC.
Benjamin Herrenschmidt wrote:
On Mon, 2009-12-28 at 12:51 +0200, Felix Radensky wrote:
Hi,
I'm running linux-2.6.33-rc2 on Canyonlands board. When PLX 6254
transparent PCI-PCI
bridge is plugged into PCI slot the kernel simply resets the board
Hi,
I'm running linux-2.6.33-rc2 on Canyonlands board. When PLX 6254
transparent PCI-PCI
bridge is plugged into PCI slot the kernel simply resets the board
without printing anything
to console. Without PLX bridge kernel boots fine.
I've tracked down the problem to the following code in
Hi,
Almost all MPC85XX based systems have the compatible=:fsl-i2c in
respective
i2c device tree nodes. This causes FSL i2c driver to use the following
backward
compatible values: FSR=0x31 DFSR=0x10. This is regardless of CCB clock
frequency and i2c clock prescaler.
On my custom MPC8536 based
Hi, Wolfgang
Wolfgang Grandegger wrote:
Felix Radensky wrote:
Hi,
Almost all MPC85XX based systems have the compatible=:fsl-i2c in
respective
i2c device tree nodes. This causes FSL i2c driver to use the following
backward
compatible values: FSR=0x31 DFSR=0x10. This is regardless of CCB
Hi, Wolfgang
Wolfgang Grandegger wrote:
Felix Radensky wrote:
Hi, Wolfgang
Wolfgang Grandegger wrote:
Felix Radensky wrote:
Hi,
Almost all MPC85XX based systems have the compatible=:fsl-i2c in
respective
i2c device tree nodes. This causes FSL i2c driver to use
Mahajan Vivek-B08308 wrote:
From:
linuxppc-dev-bounces+vivek.mahajan=freescale@lists.ozlabs.
org
[mailto:linuxppc-dev-bounces+vivek.mahajan=freescale@lists
.ozlabs.org] On Behalf Of Felix Radensky
Sent: Thursday, December 17, 2009 12:52 PM
I just noticed a MSI enable bit
Hi, Kumar
Kumar Gala wrote:
On Dec 17, 2009, at 2:59 AM, Mahajan Vivek-B08308 wrote:
Thanks a lot. If I understand you correctly, the only way I
can get ath9k driver to work on this board using legacy
interrupts is to wait for a hardware fix. Right ?
Correct
I'm confused.
Hi,
Mahajan Vivek-B08308 wrote:
Hi,
I'm trying to use mini-PCI-E WLAN card on P2020RDB running
2.6.32, but so far without success.
ath9k driver identifies the device, I can run ifconfig,
iwconfig and hostapd on wlan0, but device is not getting any
interrupts, so I suspect the interrupt
Mahajan Vivek-B08308 wrote:
From: Felix Radensky [mailto:fe...@embedded-sol.com]
Sent: Wednesday, December 16, 2009 2:56 PM
To: Mahajan Vivek-B08308
Cc: linuxppc-...@ozlabs.org; Aggrwal Poonam-B10812; Kumar Gala
Subject: Re: Problem with mini-PCI-E slot on P2020RDB
Hi,
Looks like INTA
Hi,
Mahajan Vivek-B08308 wrote:
I've enabled MSI in ath9k driver, by simply adding
pci_enable_msi() and
pci_disable_msi() at relevant places. The MSI interrupt is allocated.
irq: irq 0 on host /s...@ffe0/m...@41600 mapped to virtual irq 18
phy0: Atheros AR9280 MAC/BB Rev:2 AR5133 RF
Hi,
I'm trying to use mini-PCI-E WLAN card on P2020RDB running 2.6.32, but
so far without success.
ath9k driver identifies the device, I can run ifconfig, iwconfig and
hostapd on wlan0, but device is not
getting any interrupts, so I suspect the interrupt configuration is
wrong. Atheros ath9k
Hi,
Michael Chan wrote:
On Thu, 2009-11-19 at 08:08 -0800, Felix Radensky wrote:
Hi,
The problem goes away if I remove the call to
tg3_set_power_state(tp, PCI_D3hot);
from tg3_close().
Added Matt to CC. He is on vacation and may not be able to look into
this right away. Thanks
Hi,
I have a problem with tg3 driver on a custom MPC8536 based board
running linux-2.6.31, with tg3 and Broadcom phy drivers taken from
linux-2.6.32-rc7. Broadcom NIC is BCM57760, phy is BCM57780.
The problem I'm seeing is that the downing and interface leads to
permanent link loss, even after
[7618] dma_mask[64-bit]
Is my problem related to hardware or it's a tg3 driver bug ?
Thanks a lot.
Felix.
Felix Radensky wrote:
Hi,
I have a problem with tg3 driver on a custom MPC8536 based board
running linux-2.6.31, with tg3 and Broadcom phy drivers taken from
linux-2.6.32-rc7. Broadcom
Hi,
Can someone who used CompactPCI hotplug drivers on PowerPC
systems please share their experience ? Any pitfalls that
should be avoided, things to take into consideration, etc.
I may soon be involved in project using 460EX CPU, PLX6254
transparent PCI-PCI bridge, and CompactPCI cards. The
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed
Scott Wood wrote:
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex
Scott Wood wrote:
On Sun, Oct 18, 2009 at 11:38:13AM +0200, Felix Radensky wrote:
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC
Scott Wood wrote:
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed
Hi, Norbert
Norbert van Bolhuis wrote:
Hi Felix,
do you have CONFIG_NO_HZ defined ?
I've seen similar problems with powerpc + CONFIG_NO_HZ. In my case the
low-level
do_write_buffer (cfi_cmdset_0002.c) timed out too early. See
http://lkml.org/lkml/2009/9/3/84
Maybe in your case it's the
Hi, Scott
Scott Wood wrote:
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after that.
If I don't start NOR erase, everything works fine. Also, If I run sync
Hi, Adrian
Adrian Hunter wrote:
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after
that.
If I don't start
Adrian Hunter wrote:
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after
that.
If I don't start NOR erase
Adrian Hunter wrote:
Felix Radensky wrote:
Adrian Hunter wrote:
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition
Hi, Scott
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports
Hi, Benjamin
Benjamin Herrenschmidt wrote:
Right. However, in case it's a bit too much work to get
hotswap implemented on the machine, you may still be able
to do something simpler from your platform code, after you've
finished loading the FPGA. I assume the FPGA doesn't contain a
P2P bridge
Hi,
On a custom MPC8536 board running linux-2.6.31,
I'd like to load FPGA code from linux and then rescan
PCI-E bus to discover FPGA device. Is that possible ?
When linux boots FPGA is not loaded, so initial PCI
scan does not detect it.
I've tried playing with /sys/bus/pci/rescan and
Hi, Benjamin
Benjamin Herrenschmidt wrote:
However when I attempt to access FPGA memory my mmapping it in
userspace the read hangs. The same happens in kernel space. Does it
happen because FPGA memory is marked as disabled, or because FPGA
code is doing something wrong ?
Can you access the
Hi,
On my custom MPC8536 based board running 2.6.31 kernel
FPGA is connected via x2 PCI-E lane. FPGA is identified
during PCI scan and is visible via lspci.
:01:00.0 Class ff00: Altera Corporation Unknown device 0004 (rev 01)
Subsystem: Altera Corporation Unknown device 0004
Hi,
Compilation of gianfar driver fails in 2.6.31-rc9:
CC drivers/net/gianfar.o
drivers/net/gianfar.c: In function 'gfar_remove':
drivers/net/gianfar.c:494: error: 'dev' undeclared (first use in this
function)
drivers/net/gianfar.c:494: error: (Each undeclared identifier is
reported
Hi,
Feng Kan wrote:
This patch adds support for the AMCC (AppliedMicro) PPC460SX Eiger evaluation
board.
Signed-off-by: Tai Tri Nguyen ttngu...@amcc.com
Acked-by: Feng Kan f...@amcc.com
Acked-by: Tirumala Marri tma...@amcc.com
---
arch/powerpc/boot/dts/eiger.dts| 421 ++
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