Re: [PATCH v7 0/5] powerpc/64: memcmp() optimization

Hi Naveen, On Wed, Jun 06, 2018 at 12:06:09PM +0530, Naveen N. Rao wrote: > Simon Guo wrote: > >Hi Michael, > >On Tue, Jun 05, 2018 at 12:16:22PM +1000, Michael Ellerman wrote: > >>Hi Simon, > >> > >>wei.guo.si...@gmail.com writes: > >>> From:

Re: [PATCH v6 2/4] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

Hi segher, On Wed, May 30, 2018 at 05:03:21PM +0800, Simon Guo wrote: > On Wed, May 30, 2018 at 03:35:40AM -0500, Segher Boessenkool wrote: > > On Wed, May 30, 2018 at 04:14:02PM +0800, Simon Guo wrote: > > > Hi Segher, > > > On Mon, May 28, 2018 at 06:05:59AM -050

Re: [PATCH v7 0/5] powerpc/64: memcmp() optimization

Hi Michael, On Tue, Jun 05, 2018 at 12:16:22PM +1000, Michael Ellerman wrote: > Hi Simon, > > wei.guo.si...@gmail.com writes: > > From: Simon Guo > > > > There is some room to optimize memcmp() in powerpc 64 bits version for > > following 2 cases: > > (1)

Re: [PATCH v7 0/5] powerpc/64: memcmp() optimization

Hi Michael, On Tue, Jun 05, 2018 at 12:16:22PM +1000, Michael Ellerman wrote: > Hi Simon, > > wei.guo.si...@gmail.com writes: > > From: Simon Guo > > > > There is some room to optimize memcmp() in powerpc 64 bits version for > > following 2 cases: > > (1)

Re: [PATCH v4 04/29] KVM: PPC: Book3S PR: Move kvmppc_save_tm/kvmppc_restore_tm to separate file

On Wed, May 30, 2018 at 09:40:27AM +1000, Paul Mackerras wrote: > On Wed, May 23, 2018 at 03:01:47PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo > > > > It is a simple patch just for moving kvmppc_save_tm/kvmppc_restore_tm() > > functionalities to tm.

Re: [PATCH v6 2/4] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

On Wed, May 30, 2018 at 03:35:40AM -0500, Segher Boessenkool wrote: > On Wed, May 30, 2018 at 04:14:02PM +0800, Simon Guo wrote: > > Hi Segher, > > On Mon, May 28, 2018 at 06:05:59AM -0500, Segher Boessenkool wrote: > > > On Fri, May 25, 2018 at 12:07:34PM +0800, wei.g

Re: [PATCH v6 1/4] powerpc/64: Align bytes before fall back to .Lshort in powerpc64 memcmp()

On Wed, May 30, 2018 at 03:27:39AM -0500, Segher Boessenkool wrote: > Hi! > > On Wed, May 30, 2018 at 04:11:50PM +0800, Simon Guo wrote: > > On Mon, May 28, 2018 at 05:35:12AM -0500, Segher Boessenkool wrote: > > > On Fri, May 25, 2018 at 12:07:33PM +0800, wei.g

Re: [PATCH v6 2/4] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

Hi Michael, On Mon, May 28, 2018 at 09:59:29PM +1000, Michael Ellerman wrote: > Hi Simon, > > wei.guo.si...@gmail.com writes: > > diff --git a/arch/powerpc/lib/memcmp_64.S b/arch/powerpc/lib/memcmp_64.S > > index f20e883..4ba7bb6 100644 > > --- a/arch/powerpc/lib/memcmp_64.S > > +++

Re: [PATCH v6 2/4] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

Hi Segher, On Mon, May 28, 2018 at 06:05:59AM -0500, Segher Boessenkool wrote: > On Fri, May 25, 2018 at 12:07:34PM +0800, wei.guo.si...@gmail.com wrote: > > + /* save and restore cr0 */ > > + mfocrf r5,64 > > + EXIT_VMX_OPS > > + mtocrf 64,r5 > > + b .LcmpAB_lightweight > >

Re: [PATCH v6 1/4] powerpc/64: Align bytes before fall back to .Lshort in powerpc64 memcmp()

Hi Segher, On Mon, May 28, 2018 at 05:35:12AM -0500, Segher Boessenkool wrote: > On Fri, May 25, 2018 at 12:07:33PM +0800, wei.guo.si...@gmail.com wrote: > > _GLOBAL(memcmp) > > cmpdi cr1,r5,0 > > > > - /* Use the short loop if both strings are not 8B aligned */ > > - or r6,r3,r4

Re: [PATCH] KVM: PPC: remove mmio_vsx_tx_sx_enabled in PR KVM MMIO emulation

On Thu, May 24, 2018 at 05:01:26PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo <wei.guo.si...@gmail.com> > > Originally PR KVM MMIO emulation uses only 0~31#(5 bits) for VSR > reg number, and use mmio_vsx_tx_sx_enabled field together for > 0~63# VSR regs. >

Re: [PATCH v5 2/4] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

Hi Michael, On Thu, May 24, 2018 at 05:44:33PM +1000, Michael Ellerman wrote: > Hi Simon, > > wei.guo.si...@gmail.com writes: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch add VMX primitives to do memcmp() in case the compare size > > ex

Re: [PATCH v3 24/29] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM.

Hi Paul, On Tue, May 22, 2018 at 09:44:47PM +1000, Paul Mackerras wrote: > On Mon, May 21, 2018 at 12:09:41PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently guest kernel doesn't handle TAR fac unavailable and it a

Re: [PATCH v3 5/7] KVM: PPC: reimplements LOAD_VSX/STORE_VSX instruction mmio emulation with analyse_intr() input

Hi Paul, On Tue, May 22, 2018 at 07:41:51PM +1000, Paul Mackerras wrote: > On Mon, May 21, 2018 at 01:24:24PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch reimplements LOAD_VSX/STORE_VSX instruction MMIO emul

Re: [PATCH v4 3/4] powerpc/64: add 32 bytes prechecking before using VMX optimization on memcmp()

Hi Michael, On Fri, May 18, 2018 at 12:13:52AM +1000, Michael Ellerman wrote: > wei.guo.si...@gmail.com writes: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch is based on the previous VMX patch on memcmp(). > > > > To optimize ppc64 memcmp()

Re: [PATCH v2 05/10] KVM: PPC: reimplement non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

Hi Paul, On Thu, May 17, 2018 at 09:49:18AM +1000, Paul Mackerras wrote: > On Mon, May 07, 2018 at 02:20:11PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch reimplements non-SIMD LOAD/STORE instruction MMIO emul

Re: [PATCH v2 07/10] KVM: PPC: reimplement LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

On Thu, May 17, 2018 at 09:52:07AM +1000, Paul Mackerras wrote: > On Mon, May 07, 2018 at 02:20:13PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch reimplements LOAD_FP/STORE_FP instruction MMIO emulation wi

Re: [PATCH v2 29/30] KVM: PPC: add KVM_SET_ONE_REG/KVM_GET_ONE_REG to async ioctl

Hi Paul, On Tue, May 15, 2018 at 04:15:26PM +1000, Paul Mackerras wrote: > On Wed, Feb 28, 2018 at 01:52:37AM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > In both HV/PR KVM, the KVM_SET_ONE_REG/KVM_GET_ONE_REG ioctl sh

Re: [PATCH v2 18/30] KVM: PPC: Book3S PR: always fail transaction in guest privilege state

Hi Paul, On Tue, May 15, 2018 at 04:07:55PM +1000, Paul Mackerras wrote: > On Wed, Feb 28, 2018 at 01:52:26AM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently kernel doesn't use transaction memory. > > And ther

Re: [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs

On Tue, May 15, 2018 at 04:07:03PM +1000, Paul Mackerras wrote: > On Wed, Feb 28, 2018 at 01:52:25AM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged > >

Re: [PATCH v2 07/30] KVM: PPC: Book3S PR: add C function wrapper for _kvmppc_save/restore_tm()

On Tue, May 15, 2018 at 04:05:48PM +1000, Paul Mackerras wrote: > On Wed, Feb 28, 2018 at 01:37:14AM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently _kvmppc_save/restore_tm() APIs can only be invoked from > > a

Re: [PATCH v2 00/30] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

On Tue, May 15, 2018 at 04:01:54PM +1000, Paul Mackerras wrote: > On Wed, Feb 28, 2018 at 01:37:07AM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > In current days, many OS distributions have utilized transaction > >

Re: [PATCH 11/11] KVM: PPC: reconstruct LOAD_VSX/STORE_VSX instruction mmio emulation with analyse_intr() input

On Thu, May 03, 2018 at 04:26:12PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:44PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch reconstructs LOAD_VSX/STORE_VSX instruction MMIO emulation wi

Re: [PATCH 10/11] KVM: PPC: reconstruct LOAD_VMX/STORE_VMX instruction mmio emulation with analyse_intr() input

On Thu, May 03, 2018 at 04:17:15PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:43PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch reconstructs LOAD_VMX/STORE_VMX instruction MMIO emulation wi

Re: [PATCH 09/11] KVM: PPC: reconstruct LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

On Thu, May 03, 2018 at 04:10:49PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:42PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch reconstructs LOAD_FP/STORE_FP instruction MMIO emulation wi

Re: [PATCH 08/11] KVM: PPC: add giveup_ext() hook for PPC KVM ops

On Thu, May 03, 2018 at 04:08:17PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:41PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently HV will save math regs(FP/VEC/VSX) when trap into host. But >

Re: [PATCH 07/11] KVM: PPC: reconstruct non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

On Thu, May 03, 2018 at 04:03:46PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:40PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch reconstructs non-SIMD LOAD/STORE instruction MMIO emulation &g

Re: [PATCH 04/11] KVM: PPC: fix incorrect element_size for stxsiwx in analyse_instr

On Thu, May 03, 2018 at 03:50:47PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:37PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > stwsiwx will place contents of word element 1 of VSR into word > > s

Re: [PATCH 05/11] KVM: PPC: add GPR RA update skeleton for MMIO emulation

On Thu, May 03, 2018 at 03:58:14PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:38PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > To optimize kvm emulation code with analyse_instr, adds new > > mmio_

Re: [PATCH 03/11] KVM: PPC: Fix a mmio_host_swabbed uninitialized usage issue when VMX store

On Thu, May 03, 2018 at 03:48:26PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:36PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > When KVM emulates VMX store, it will invoke kvmppc_get_vmx_data()

Re: [PATCH 02/11] KVM: PPC: mov nip/ctr/lr/xer registers to pt_regs in kvm_vcpu_arch

On Thu, May 03, 2018 at 03:46:01PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:35PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch moves nip/ctr/lr/xer registers from scattered places in &

Re: [PATCH 01/11] KVM: PPC: add pt_regs into kvm_vcpu_arch and move vcpu->arch.gpr[] into it

On Thu, May 03, 2018 at 03:34:01PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:34PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Current regs are scattered at kvm_vcpu_arch structure and it will > &

Re: [PATCH 00/11] KVM: PPC: reconstruct mmio emulation with analyse_instr()

On Thu, May 03, 2018 at 03:31:17PM +1000, Paul Mackerras wrote: > On Wed, Apr 25, 2018 at 07:54:33PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > We already have analyse_instr() which analyzes instructions for the >

Re: [PATCH 01/11] KVM: PPC: add pt_regs into kvm_vcpu_arch and move vcpu->arch.gpr[] into it

On Fri, Apr 27, 2018 at 11:47:21AM +0800, kbuild test robot wrote: > Hi Simon, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on powerpc/next] > [also build test ERROR on v4.17-rc2 next-20180426] > [if your patch is applied to the wrong git tree, please drop us

Re: [PATCH] KVM: PPC: Book3S PR: close a race window when SVCPU pointer is hold before kvmppc_copy_from_svcpu()

Hi Alex, On Wed, Jan 31, 2018 at 10:28:05AM +0100, Alexander Graf wrote: > > > On 31.01.18 05:23, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > commit 40fdd8c88c4a ("KVM: PPC: Book3S: PR: Make svcpu -> vcpu store &g

Re: [PATCH 25/26] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM.

Hi Paul, On Wed, Jan 24, 2018 at 03:02:58PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:38PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently guest kernel doesn't handle TAR fac unavailable and it a

Re: [PATCH 23/26] KVM: PPC: Book3S PR: add emulation for tabort. for privilege guest

Hi Paul, On Tue, Jan 23, 2018 at 08:44:16PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:36PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently privilege guest will be run with TM disabled. > >

Re: [PATCH 21/26] KVM: PPC: Book3S PR: adds emulation for treclaim.

Hi Paul, On Tue, Jan 23, 2018 at 08:23:23PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:34PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch adds support for "treclaim." emulation wh

Re: [PATCH 22/26] KVM: PPC: Book3S PR: add emulation for trechkpt in PR KVM.

Hi Paul, On Tue, Jan 23, 2018 at 08:36:44PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:35PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch adds host emulation when guest PR KVM exec

Re: [PATCH 19/26] KVM: PPC: Book3S PR: always fail transaction in guest privilege state

Hi Paul, On Tue, Jan 23, 2018 at 07:30:33PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:32PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently kernel doesn't use transaction memory. > > And ther

Re: [PATCH 18/26] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs

Hi Paul, On Tue, Jan 23, 2018 at 07:17:45PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:31PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileg

Re: [PATCH 17/26] KVM: PPC: Book3S PR: add math support for PR KVM HTM

Hi Paul, On Tue, Jan 23, 2018 at 06:29:27PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:30PM +0800, wei.guo.si...@gmail.com wrote: > > ines: 219 > > > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > The math registers will be saved

Re: [PATCH 16/26] KVM: PPC: Book3S PR: add transaction memory save/restore skeleton for PR KVM

Hi Paul, On Tue, Jan 23, 2018 at 05:04:09PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:29PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > The transaction memory checkpoint area save/restore behavior is &

Re: [PATCH 04/26] KVM: PPC: Book3S PR: add C function wrapper for _kvmppc_save/restore_tm()

Hi Paul, On Tue, Jan 23, 2018 at 04:49:16PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:17PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > Currently _kvmppc_save/restore_tm() APIs can only be invoked

Re: [PATCH 02/26] KVM: PPC: Book3S PR: add new parameter (guest MSR) for kvmppc_save_tm()/kvmppc_restore_tm()

Hi Paul, On Tue, Jan 23, 2018 at 04:42:09PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:15PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > HV KVM and PR KVM need different MSR source to indicate whether >

Re: [PATCH 13/26] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for PR KVM.

Hi Paul, On Tue, Jan 23, 2018 at 04:52:19PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:26PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch adds 2 new APIs: kvmppc_copyto_vcpu_tm() and > > kv

Re: [PATCH 00/26] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

Hi Paul, On Tue, Jan 23, 2018 at 04:38:32PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:13PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > In current days, many OS distributions have utilized transacti

Re: [PATCH 00/26] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

Hi Gustavo, On Thu, Jan 11, 2018 at 11:56:59AM -0200, Gustavo Romero wrote: > Hi Simon, > > On 01/11/2018 08:11 AM, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > In current days, many OS distributions have utilized tra

Re: [PATCH v3 3/3] powerpc:selftest update memcmp_64 selftest for VMX implementation

Hi Cyril, Thanks for the review. On Mon, Oct 16, 2017 at 02:32:58PM +1100, Cyril Bur wrote: > On Fri, 2017-10-13 at 12:30 +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch adjust selftest memcmp_64 so that memcmp s

Re: [PATCH] selftests/powerpc: fix build error in powerpc ptrace selftests.

Hi Michael, On Tue, Oct 10, 2017 at 09:10:32PM +1100, Michael Ellerman wrote: > wei.guo.si...@gmail.com writes: > > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > GCC 7 will take "r2" in clobber list as an error will it will get following > >

Re: [PATCH v2 2/3] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

On Wed, Sep 27, 2017 at 09:43:44AM +, David Laight wrote: > From: Segher Boessenkool > > Sent: 27 September 2017 10:28 > ... > > You also need nasty code to deal with the start and end of strings, with > > conditional branches and whatnot, which quickly overwhelms the benefit > > of using

Re: [PATCH v2 2/3] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

Hi Michael, On Wed, Sep 27, 2017 at 01:38:09PM +1000, Michael Ellerman wrote: > Segher Boessenkool writes: > > > On Tue, Sep 26, 2017 at 03:34:36PM +1000, Michael Ellerman wrote: > >> Cyril Bur writes: > >> > This was written for userspace which

Re: [PATCH v2 3/3] powerpc:selftest update memcmp_64 selftest for VMX implementation

Hi David, On Mon, Sep 25, 2017 at 09:30:28AM +, David Laight wrote: > From: wei.guo.si...@gmail.com > > Sent: 21 September 2017 00:35 > > This patch adjust selftest memcmp_64 so that memcmp selftest can be > > compiled successfully. > ... > > #define ITERATIONS 1 > > > > +#define

Re: [PATCH v2 2/3] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

Hi Cyril, On Sat, Sep 23, 2017 at 12:06:48AM +1000, Cyril Bur wrote: > On Thu, 2017-09-21 at 07:34 +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > This patch add VMX primitives to do memcmp() in case the compare size > &g

Re: [PATCH v2 2/3] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

Hi, On Thu, Sep 21, 2017 at 07:34:39AM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo <wei.guo.si...@gmail.com> > > This patch add VMX primitives to do memcmp() in case the compare size > exceeds 4K bytes. > > Test result with following test program(replace the &

Re: [PATCH v1 0/3] powerpc: memcmp() optimization

Hi Chris, On Tue, Sep 19, 2017 at 02:21:33PM +0200, Christophe LEROY wrote: > Hi > > Could you in the email/patch subject and in the commit texts write > powerpc/64 instead of powerpc as it doesn't apply to powerpc/32 > > Christophe > Sure. I will update in v2. BR, - Simon

Re: [PATCH v1 1/3] powerpc: Align bytes before fall back to .Lshort in powerpc memcmp

On Tue, Sep 19, 2017 at 10:12:50AM +, David Laight wrote: > From: wei.guo.si...@gmail.com > > Sent: 19 September 2017 11:04 > > Currently memcmp() in powerpc will fall back to .Lshort (compare per byte > > mode) if either src or dst address is not 8 bytes aligned. It can be > > opmitized if

Re: Build failures in powerpc ptrace selftests

Hi Seth, On Wed, Aug 30, 2017 at 08:05:25AM -0500, Seth Forshee wrote: > With gcc 7 from Ubuntu 17.10 I'm getting the follwing error building the > ptrace selftests for powerpc: > > ptrace-tm-vsx.c: In function ‘tm_vsx’: > ptrace-tm-vsx.c:42:2: error: PIC register clobbered by ‘r2’ in ‘asm’ >

Re: [PATCH v15 03/15] selftests/powerpc: Add ptrace tests for EBB

On Fri, Oct 07, 2016 at 08:44:48AM +1100, Michael Ellerman wrote: > wei.guo.si...@gmail.com writes: > > > From: Anshuman Khandual > > > > This patch adds ptrace interface test for EBB/PMU specific > > registers. This also adds some generic ptrace interface > > based

Re: [PATCH v14 13/15] selftests/powerpc: Add ptrace tests for TM SPR registers

system-ppc64 --enable-kvm -machine pseries,accel=kvm,usb=off -m > 4096 -realtime mlock=off -smp 4,sockets=1,cores=2,threads=2 -nographic > -vga none > > > > Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> > > Signed-off-by: Simon Guo <wei.guo.si...@gmail.

Re: [PATCH 2/2] powerpc: tm: Enable transactional memory (TM) lazily for userspace

On Wed, Sep 14, 2016 at 06:02:16PM +1000, Cyril Bur wrote: > @@ -954,8 +963,16 @@ static inline void __switch_to_tm(struct task_struct > *prev, > struct task_struct *new) > { > if (cpu_has_feature(CPU_FTR_TM)) { > - tm_enable(); > -

Re: [PATCH v14 13/15] selftests/powerpc: Add ptrace tests for TM SPR registers

On Wed, Sep 14, 2016 at 03:04:12PM +1000, Cyril Bur wrote: > On Mon, 2016-09-12 at 15:33 +0800, wei.guo.si...@gmail.com wrote: > > From: Anshuman Khandual > > > > This patch adds ptrace interface test for TM SPR registers. This > > also adds ptrace interface based

Re: [PATCH v14 00/15] selftests/powerpc: Add ptrace tests for ppc registers

Hi Cyril, On Tue, Sep 13, 2016 at 03:49:10PM +1000, Cyril Bur wrote: > Thanks for putting the effort in to get these merged! I have a few > remarks that apply to more than one patch which I'll say here. > > I'm not sure #defining the TM instructions as .long for the selftests > is useful.

Re: [PATCH] powerpc: set used_vsr/used_vr/used_spe in sigreturn path when MSR bits are active

On Tue, Jul 26, 2016 at 04:06:01PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo <wei.guo.si...@gmail.com> > > Normally, when MSR[VSX/VR/SPE] bits = 1, the used_vsr/used_vr/used_spe > bit have already been set. However signal frame locates at user space > and it

Re: [PATCH] powerpc/ptrace: Fix cppcheck issue in gpr32_set_common/gpr32_get_common.

On Fri, Sep 09, 2016 at 08:52:52PM +1000, Michael Ellerman wrote: > I do - Sorry Simon but your patch just adds too many #ifdefs. > > Any time you have to do something like: > > +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM > } > +#endif > > It should be a sign that something

Re: [PATCH] powerpc/ptrace: Fix cppcheck issue in gpr32_set_common/gpr32_get_common.

Hi Daniel, On Wed, Aug 24, 2016 at 12:21:23PM +1000, Daniel Axtens wrote: > Hi Simon, > > > The ckpt_regs usage in gpr32_set_common/gpr32_get_common() > > will lead to cppcheck error. > > > > [arch/powerpc/kernel/ptrace.c:2062]: (error) Uninitialized variable: > > ckpt_regs > >

Re: [PATCH v3] powerpc: signals: Discard transaction state from signal frames

w it away. > + * The purpose of a sigreturn is to destroy all traces of the > + * signal frame, this includes any transactional state created > + * within in. We only check for suspended as we can never be > + * active in the kernel, we are active, there is nothing better to > + * do than go ahead and Bad Thing later. > + * The cause is not important as there will never be a > + * recheckpoint so it's not user visible. > + */ > + if (MSR_TM_SUSPENDED(mfmsr())) > + tm_reclaim_current(0); > + > if (__get_user(msr, >uc_mcontext.gp_regs[PT_MSR])) > goto badframe; > if (MSR_TM_ACTIVE(msr)) { > -- > 2.9.3 > Acked-by: Simon Guo <wei.guo.si...@gmail.com> Thanks, - Simon

Re: [PATCH] powerpc: signals: Discard transaction state from signal frames

Hi Cyril, On Mon, Aug 22, 2016 at 05:32:06PM +1000, Cyril Bur wrote: > diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c > index b6aa378..31e4e15 100644 > --- a/arch/powerpc/kernel/signal_32.c > +++ b/arch/powerpc/kernel/signal_32.c > @@ -1226,7 +1226,19 @@ long

Re: [PATCH v3 19/21] powerpc: tm: Always use fp_state and vr_state to store live registers

> live state and prevents the use of common functions designed (probably > before TM) to save the live state. > > With this patch pt_regs, fp_state and vr_state all represent the > same thing and the other structures [pending rename] are for > checkpointed state. > > Signed-off-by: Cyril Bur <cyril...@gmail.com> Acked-by: Simon Guo <wei.guo.si...@gmail.com> Thanks, - Simon

Re: [PATCH v2 18/20] powerpc: tm: Always use fp_state and vr_state to store live registers

Hi Cyril, On Mon, Aug 15, 2016 at 05:25:53PM +1000, Cyril Bur wrote: > > There are 2 "giveall_all()" in above path: > > __switch_to() > > giveup_all()  // first time > > __switch_to_tm() > > tm_reclaim_task() > > tm_reclaim_thread() > >   

Re: [PATCH v2 18/20] powerpc: tm: Always use fp_state and vr_state to store live registers

On Fri, Aug 12, 2016 at 09:28:17AM +1000, Cyril Bur wrote: > @@ -846,7 +834,9 @@ static void tm_reclaim_thread(struct thread_struct *thr, > if (!MSR_TM_SUSPENDED(mfmsr())) > return; > > - tm_reclaim(thr, thr->regs->msr, cause); > + giveup_all(container_of(thr, struct

Re: [PATCH] ppc64: allow ptrace to set TM bits

Hi Laurent, On Fri, Jul 29, 2016 at 11:51:22AM +0200, Laurent Dufour wrote: > static int set_user_msr(struct task_struct *task, unsigned long msr) > { > +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM > + if (!(task->thread.regs->msr & MSR_TM)) { > + /* If TM is not available, discard TM

Re: [v4] powerpc: Export thread_struct.used_vr/used_vsr to user space

On Thu, Jul 21, 2016 at 08:57:29PM +1000, Michael Ellerman wrote: > Can one of you send a properly formatted and signed-off patch. I will work on that. Thanks, Simon ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org

Re: [PATCH 3/5] powerpc: tm: Always use fp_state and vr_state to store live registers

On Mon, Jul 18, 2016 at 11:28:30AM +1000, Cyril Bur wrote: > On Sun, 17 Jul 2016 11:25:43 +0800 > > The aim of this patch is to ensure that pt_regs, fp_state and vr_state always > hold a threads 'live' registers. So, after a recheckpoint fp_state is where > the > the state should be.

Re: [PATCH 3/5] powerpc: tm: Always use fp_state and vr_state to store live registers

Hi Cyril, On Wed, Jun 08, 2016 at 02:00:34PM +1000, Cyril Bur wrote: > @@ -917,24 +907,10 @@ static inline void tm_recheckpoint_new_task(struct > task_struct *new) >"(new->msr 0x%lx, new->origmsr 0x%lx)\n", >new->pid, new->thread.regs->msr, msr); > > - /*

Re: [v4] powerpc: Export thread_struct.used_vr/used_vsr to user space

Michael, Ben, On Fri, Jul 08, 2016 at 08:02:42PM +1000, Michael Ellerman wrote: > Benjamin Herrenschmidt writes: > > > On Thu, 2016-07-07 at 23:21 +1000, Benjamin Herrenschmidt wrote: > >>  > >> I think the right fix is that if a restore_sigcontext() has the MSR > >>

Re: [v4] powerpc: Export thread_struct.used_vr/used_vsr to user space

On Fri, Jul 08, 2016 at 08:02:42PM +1000, Michael Ellerman wrote: > Benjamin Herrenschmidt writes: > > > On Thu, 2016-07-07 at 23:21 +1000, Benjamin Herrenschmidt wrote: > >>  > >> I think the right fix is that if a restore_sigcontext() has the MSR > >> bits set, > >>

Re: [v4] powerpc: Export thread_struct.used_vr/used_vsr to user space

On Thu, Jul 07, 2016 at 11:21:18PM +1000, Benjamin Herrenschmidt wrote: > I think the right fix is that if a restore_sigcontext() has the MSR bits set, > it should set the corresponding used_* flag. > > Or is there a reason why that won't work ? That sounds reaonable to me. I will prepare a

Re: [RESEND, v2] powerpc: Export thread_struct.used_vr/used_vsr to user space

Hi Michael, On Tue, Jul 05, 2016 at 03:40:40PM +1000, Michael Ellerman wrote: > On Wed, 2016-06-04 at 07:00:12 UTC, Simon Guo wrote: > > These 2 fields track whether user process has used Altivec/VSX > > registers or not. They are used by kernel to setup signal frame > > on

Re: [PATCH 3/5] powerpc: tm: Always use fp_state and vr_state to store live registers

hi Cyril, On Wed, Jun 08, 2016 at 02:00:34PM +1000, Cyril Bur wrote: > @@ -1108,11 +1084,11 @@ struct task_struct *__switch_to(struct task_struct > *prev, >*/ > save_sprs(>thread); > > - __switch_to_tm(prev); > - > /* Save FPU, Altivec, VSX and SPE state */ >

Re: [RESEND][PATCH v2] powerpc: Export thread_struct.used_vr/used_vsr to user space

On Tue, Jun 21, 2016 at 02:30:06PM +0800, Simon Guo wrote: > Hi Michael, > On Wed, Apr 06, 2016 at 03:00:12PM +0800, Simon Guo wrote: > > These 2 fields track whether user process has used Altivec/VSX > > registers or not. They are used by kernel to setup signal frame > >

Re: [RESEND][PATCH v2] powerpc: Export thread_struct.used_vr/used_vsr to user space

Hi Michael, On Wed, Apr 06, 2016 at 03:00:12PM +0800, Simon Guo wrote: > These 2 fields track whether user process has used Altivec/VSX > registers or not. They are used by kernel to setup signal frame > on user stack correctly regarding vector part. > > CRIU(Checkpoint and Restor

[RESEND][PATCH v2] powerpc: Export thread_struct.used_vr/used_vsr to user space

to setup signal frame correctly. And CRIU will need to restore these 2 fields for the restored process. Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> Reviewed-by: Laurent Dufour <lduf...@linux.vnet.ibm.com> --- arch/powerpc/include/uapi/asm/ptrace.h | 11 ++ arch/po

[PATCH] powerpc: Export thread_struct.used_vr/used_vsr to user space

to setup signal frame correctly. And CRIU will need to restore these 2 fields for the restored process. Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> Reviewed-by: Laurent Dufour <lduf...@linux.vnet.ibm.com> --- arch/powerpc/include/uapi/asm/ptrace.h | 11 ++ arch/po

[PATCH] powerpc: Export thread_struct.used_vr/used_vsr to user space

to setup signal frame correctly. And CRIU will need to restore these 2 fields for the restored process. Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> Reviewed-by: Laurent Dufour <lduf...@linux.vnet.ibm.com> --- arch/powerpc/include/uapi/asm/ptrace.h | 11 ++ arch/po

[PATCH] powerpc: correct VSX used_vsr comment

used_vsr flag is set if process has used VSX register, instead of Altivec register. This patch corrects the wrong comment. Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> --- arch/powerpc/include/asm/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git