OK. I will do.
-Chenhui
From: Wood Scott-B07421
Sent: Thursday, October 17, 2013 7:20
To: Zhao Chenhui-B35336
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [4/4] powerpc/mpc8548: Add workaround for erratum NMG_SRIO135
On Tue, Mar 06, 2012 at 05:10:56PM
On Wed, Jun 12, 2013 at 01:25:22PM +1000, Benjamin Herrenschmidt wrote:
On Mon, 2013-06-03 at 18:43 +0800, Zhao Chenhui wrote:
On Sat, Jun 01, 2013 at 07:49:44AM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2013-05-28 at 15:59 +0800, Zhao Chenhui wrote:
Some features depend on the boot
For the mpic with a flag MPIC_SINGLE_DEST_CPU, only one bit should be
set in interrupt destination registers.
The code is applicable to 64-bit platforms as well as 32-bit.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/sysdev/mpic.c |4 ++--
1 files changed, 2
Some features depend on the boot cpu, for instance, hibernate/suspend.
So disable hotplug for the boot cpu.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/kernel/sysfs.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel
On Thu, Apr 25, 2013 at 07:07:24PM -0500, Scott Wood wrote:
On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote:
On Wed, Apr 24, 2013 at 05:38:16PM -0500, Scott Wood wrote:
On 04/24/2013 06:29:29 AM, Zhao Chenhui wrote:
On Tue, Apr 23, 2013 at 07:04:06PM -0500, Scott Wood wrote:
On 04/19/2013
On Tue, Apr 23, 2013 at 06:53:20PM -0500, Scott Wood wrote:
On 04/19/2013 05:47:35 AM, Zhao Chenhui wrote:
static int pmc_suspend_enter(suspend_state_t state)
{
-int ret;
+int ret = 0;
+
+switch (state) {
+#ifdef CONFIG_PPC_85xx
+case PM_SUSPEND_MEM:
+#ifdef CONFIG_SPE
On Tue, Apr 23, 2013 at 06:46:10PM -0500, Scott Wood wrote:
On 04/19/2013 05:47:34 AM, Zhao Chenhui wrote:
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily. And, add cache operations for backside L2 cache
On Tue, Apr 23, 2013 at 07:00:49PM -0500, Scott Wood wrote:
On 04/19/2013 05:47:46 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao chenhui.z...@freescale.com
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
On Tue, Apr 23, 2013 at 07:04:06PM -0500, Scott Wood wrote:
On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao chenhui.z...@freescale.com
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip
On Wed, Apr 24, 2013 at 05:38:16PM -0500, Scott Wood wrote:
On 04/24/2013 06:29:29 AM, Zhao Chenhui wrote:
On Tue, Apr 23, 2013 at 07:04:06PM -0500, Scott Wood wrote:
On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao chenhui.z...@freescale.com
For e6500, two threads
Hi Kumar, Scott,
Do you have any comments on this set of patches?
Best Regards,
-Chenhui
On Fri, Apr 19, 2013 at 06:47:34PM +0800, Zhao Chenhui wrote:
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily
On Mon, Apr 22, 2013 at 08:55:35AM +0530, Viresh Kumar wrote:
On Fri, Apr 19, 2013 at 4:17 PM, Zhao Chenhui
chenhui.z...@freescale.com wrote:
diff --git a/drivers/cpufreq/mpc85xx-cpufreq.c
b/drivers/cpufreq/mpc85xx-cpufreq.c
+#include linux/module.h
+#include linux/cpufreq.h
On Mon, Apr 22, 2013 at 01:43:29AM +0200, Rafael J. Wysocki wrote:
On Friday, April 19, 2013 07:00:57 PM Zhao Chenhui wrote:
- Forwarded message from Zhao Chenhui chenhui.z...@freescale.com -
Date: Fri, 19 Apr 2013 18:47:39 +0800
From: Zhao Chenhui chenhui.z...@freescale.com
by this patch is L2 Look-Aside Cache, which appears on SoCs
with e500v1/e500v2 core, such as MPC8572, P1020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/cacheflush.h |8 ++
arch/powerpc/kernel/Makefile
of Linux Power Management.
Command to enter sleep mode.
echo standby /sys/power/state
Command to enter deep sleep mode.
echo mem /sys/power/state
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile |1
le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/sysdev/fsl_pmc.c | 72 -
arch/powerpc/sysdev/fsl_soc.h | 11 ++
2 files changed, 82 insertions(+), 1 deletions
The Power Management device tree stub indicated that the platform
supports Power Management feature.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi | 14 ++-
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi |2 +
arch/powerpc/boot
From: Li Yang le...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 59 +++
1 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/Documentation
of MPC8536 have corrected the erratum.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
arch/powerpc/platforms
by individual
cpus. Platform implementations can override the platform_cpu_die().
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/smp.h
-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/Kconfig|4 +-
arch/powerpc/include/asm/fsl_guts.h |1 +
arch/powerpc/platforms/85xx/Kconfig |1 +
arch/powerpc/sysdev/Kconfig |5 ++
arch/powerpc/sysdev
.
* Rearrange the code segment in smp_85xx_kick_cpu() to share codes
between PPC64 and PPC32 as far as possible.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/Kconfig
the register map.
This patch supports SoCs based on e500mc/e5500, such as P4080, P5020,
etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 38 +++
arch/powerpc/platforms/85xx/smp.c
From: Chen-Hui Zhao chenhui.z...@freescale.com
Add struct ccsr_rcpm_v2 to descibe the v2 RCPM register map on some SoCs,
such as T4240, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
From: Chen-Hui Zhao chenhui.z...@freescale.com
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/kernel
-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/include/asm/cputable.h | 10
arch/powerpc/kernel/cputable.c |5
arch/powerpc/platforms/85xx/smp.c | 40
internal timers
and internal and external interrupts.
When the device enter sleep state, it will be put in LPM20 mode.
The command is echo standby /sys/power/state.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem
From: Chen-Hui Zhao chenhui.z...@freescale.com
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
On Wed, Apr 03, 2013 at 09:09:11PM +0800, Zhao Chenhui wrote:
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily. And, add cache operations for backside L2 cache and platform cache.
The backside L2 cache
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+b29983=freescale@lists.ozlabs.org] On Behalf Of Zhao Chenhui
Sent: 2013年4月3日 21:09
To: linuxppc-dev@lists.ozlabs.org
Subject: [PATCH 08/17] powerpc/85xx: add support to JOG feature using
cpufreq interface
From: Chen-Hui Zhao chenhui.z...@freescale.com
The bootloader have done time base sync for all cores, so skip
the synchronization process at boot time of kernel.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem
From: Chen-Hui Zhao chenhui.z...@freescale.com
mpic_reset_core() need a logical cpu number instead of physical.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/platforms/85xx/smp.c |2 +-
1 files changed, 1 insertions(+), 1
of Linux Power Management.
Command to enter sleep mode.
echo standby /sys/power/state
Command to enter deep sleep mode.
echo mem /sys/power/state
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile |1
...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/sysdev/fsl_pmc.c | 71 -
arch/powerpc/sysdev/fsl_soc.h |9 +
2 files changed, 79 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch
The Power Management device tree stub indicated that the platform
supports Power Management feature.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi | 14 ++-
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi |2 +
arch/powerpc/boot
From: Li Yang le...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 59 +++
1 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/Documentation
corrected the erratum.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc/sysdev
the register map.
This patch supports SoCs based on e500mc/e5500, such as P4080, P5020,
etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 38 +++
arch/powerpc/platforms/85xx/smp.c
by individual
cpus. Platform implementations can override the platform_cpu_die().
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/smp.h
-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/Kconfig|4 +-
arch/powerpc/include/asm/fsl_guts.h |1 +
arch/powerpc/platforms/85xx/Kconfig |1 +
arch/powerpc/sysdev/Kconfig |5 ++
arch/powerpc/sysdev
.
* Rearrange the code segment in smp_85xx_kick_cpu() to share codes
between PPC64 and PPC32 as far as possible.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/Kconfig
From: Chen-Hui Zhao chenhui.z...@freescale.com
Add struct ccsr_rcpm_v2 to descibe the v2 RCPM register map on some SoCs,
such as T4240, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
From: Chen-Hui Zhao chenhui.z...@freescale.com
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/kernel
From: Chen-Hui Zhao chenhui.z...@freescale.com
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/include/asm/cputable.h | 10
arch/powerpc/kernel/cputable.c |5
arch/powerpc/platforms/85xx/smp.c | 40
internal timers
and internal and external interrupts.
When the device enter sleep state, it will be put in LPM20 mode.
The command is echo standby /sys/power/state.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem
No other reason. Just avoid doing it again at boot time in kernel.
-Chenhui
From: Kumar Gala [ga...@kernel.crashing.org]
Sent: Wednesday, April 03, 2013 23:10
To: Zhao Chenhui-B35336
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 02/17] powerpc
MPIC_SINGLE_DEST_CPU is set.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/sysdev/mpic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9c6e535..cc537f8
On Sat, Aug 11, 2012 at 08:19:43AM -0500, Tabi Timur-B04825 wrote:
On Tue, Aug 7, 2012 at 3:43 AM, Zhao Chenhui chenhui.z...@freescale.com
wrote:
+ return -EINVAL;
+
+ prop = of_get_property(clk_np, fsl,pmcdr-mask, NULL);
+ if (!prop) {
+ ret
On Sat, Aug 11, 2012 at 08:19:43AM -0500, Tabi Timur-B04825 wrote:
On Tue, Aug 7, 2012 at 3:43 AM, Zhao Chenhui chenhui.z...@freescale.com
wrote:
+int mpc85xx_pmc_set_wake(struct device *dev, bool enable)
+{
+ int ret = 0;
+ struct device_node *clk_np;
+ const u32
On Tue, Aug 07, 2012 at 04:43:25PM +0800, Zhao Chenhui wrote:
The cpufreq driver of mpc85xx will disable/enable cpu hotplug temporarily.
Therefore, the related functions should be exported.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
include/linux/cpu.h |4
1 files
-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
v2:
* use get/put_online_cpus() to disable/enable cpu hotplug.
arch
On Wed, Aug 08, 2012 at 11:43:22AM +0530, Srivatsa S. Bhat wrote:
On 08/07/2012 11:21 PM, Kumar Gala wrote:
On Aug 7, 2012, at 3:43 AM, Zhao Chenhui wrote:
The cpufreq driver of mpc85xx will disable/enable cpu hotplug temporarily.
Therefore, the related functions should be exported
-by: Jerry Huang chang-ming.hu...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/cacheflush.h |2 +
arch/powerpc/kernel/Makefile |1 +
arch/powerpc
The cpufreq driver of mpc85xx will disable/enable cpu hotplug temporarily.
Therefore, the related functions should be exported.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
include/linux/cpu.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/include/linux
-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Replace this patch mpc85xx_defconfig: add IDE support for MPC85xxCDS.
arch/powerpc/configs/mpc85xx_defconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc85xx_defconfig
b/arch/powerpc
On Sat, Jul 28, 2012 at 08:20:31AM +1000, Benjamin Herrenschmidt wrote:
On Fri, 2012-07-27 at 16:58 -0500, Kumar Gala wrote:
On Jul 20, 2012, at 7:47 AM, Zhao Chenhui wrote:
During suspend, all interrupts including IPI will be disabled. In this
case,
the suspend process will hang
On Tue, Jul 31, 2012 at 09:15:33AM -0500, Kumar Gala wrote:
On Jul 20, 2012, at 7:42 AM, Zhao Chenhui wrote:
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
Some Freescale chips
On Fri, Jul 20, 2012 at 03:09:00PM +0100, Alan Cox wrote:
On Fri, 20 Jul 2012 20:45:25 +0800
Zhao Chenhui chenhui.z...@freescale.com wrote:
Add IDE support for MPC85xxCDS.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/configs/mpc85xx_defconfig |2
Changes for v8:
* Separated the cpu hotplug patch into three patches, as follows
[PATCH v8 1/7] powerpc/smp: use a struct epapr_spin_table to replace macros
[PATCH v8 2/7] powerpc/smp: add generic_set_cpu_up() to set cpu_state as
CPU_UP_PREPARE
[PATCH v8 4/7] powerpc/85xx: add HOTPLUG_CPU
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/platforms/85xx/smp.c | 46 ++--
1 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index ff42490..4827709
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le
In the case of cpu hotplug, the cpu_state should be set to CPU_UP_PREPARE when
kicking cpu.
Otherwise, the cpu_state is always CPU_DEAD after calling
generic_set_cpu_dead(), which
makes the delay in generic_cpu_die() not happen.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch
and 36-bit physical address.
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/Kconfig |6 ++-
arch/powerpc/include/asm/cacheflush.h |2 +
arch/powerpc/include/asm
-by: Jerry Huang chang-ming.hu...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/cacheflush.h |2 +
arch/powerpc/kernel/Makefile |3 +
arch/powerpc
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc
Add IDE support for MPC85xxCDS.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/configs/mpc85xx_defconfig |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc85xx_defconfig
b/arch/powerpc/configs/mpc85xx_defconfig
index
During suspend, all interrupts including IPI will be disabled. In this case,
the suspend process will hang in SMP. To prevent this, pass the flag
IRQF_NO_SUSPEND when requesting IPI irq.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch
The Power Management device tree stub indicated that the platform
supports Power Management feature.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi | 14 ++-
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi |2 +
arch/powerpc/boot
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, July 13, 2012 8:15 PM
To: Zhao Chenhui-B35336
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
linux-ker...@vger.kernel.org; Li Yang-R58472
Subject: Re: [PATCH v7 2/5] powerpc/85xx: add
On Wed, Jul 04, 2012 at 10:19:54AM -0500, Tabi Timur-B04825 wrote:
Zhao Chenhui wrote:
On Tue, Jul 03, 2012 at 10:17:12PM -0500, Tabi Timur-B04825 wrote:
Zhao Chenhui wrote:
If the guts variable is NULL, it indicates there is error in dts or
kernel.
We should fix the error, rather than
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le
at runtime.
It supports 32-bit and 36-bit physical address.
Add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE in kick_cpu().
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
v7:
* removed
On Tue, Jul 03, 2012 at 07:46:24AM -0500, Tabi Timur-B04825 wrote:
On Tue, Jul 3, 2012 at 5:21 AM, Zhao Chenhui chenhui.z...@freescale.com
wrote:
+ np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
+ if (np) {
+ guts = of_iomap(np, 0
On Tue, Jul 03, 2012 at 10:17:12PM -0500, Tabi Timur-B04825 wrote:
Zhao Chenhui wrote:
If the guts variable is NULL, it indicates there is error in dts or kernel.
We should fix the error, rather than ignore it.
And that's why there's a warning message. Crashing the kernel is not
going
On Fri, Jun 29, 2012 at 10:39:24AM -0500, Tabi Timur-B04825 wrote:
On Tue, Jun 26, 2012 at 5:25 AM, Zhao Chenhui
chenhui.z...@freescale.com wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all
On Thu, Jun 28, 2012 at 08:50:51PM +1000, Benjamin Herrenschmidt wrote:
On Thu, 2012-06-28 at 11:38 +0800, Zhao Chenhui wrote:
The bootloader have done a timebase sync. If we do not need KEXEC or
HOTPLUG_CPU feature, it is unnecessary to do it again at boot time of
kernel. I only
-Original Message-
From: Linuxppc-dev
[mailto:linuxppc-dev-bounces+chenhui.zhao=freescale@lists.ozlabs.org] On
Behalf
Of Kumar Gala
Sent: Friday, June 29, 2012 2:30 AM
To: Zhao Chenhui-B35336
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org list;
linux-ker
On Tue, Jun 26, 2012 at 09:03:42AM -0500, Kumar Gala wrote:
On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual
On Wed, Jun 27, 2012 at 08:10:34AM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2012-06-26 at 18:25 +0800, Zhao Chenhui wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only
On Wed, Jun 27, 2012 at 09:48:52PM +1000, Benjamin Herrenschmidt wrote:
On Wed, 2012-06-27 at 18:21 +0800, Zhao Chenhui wrote:
What's that CONFIG option for ?
Cheers,
Ben.
This option is to guard the timebase sync routines. It is selected
when KEXEC or HOTPLUG_CPU is enabled
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le
at runtime.
It supports 32-bit and 36-bit physical address.
Add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE in kick_cpu().
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Changes for v6
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
Changes for v6:
* changed mpc85xx_jog_probe()
* call
b24...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Changes for v6:
* changed the declaration of flush_dcache_L1()
* some minor changes
arch/powerpc/Kconfig
On Tue, Jun 05, 2012 at 11:07:41AM -0500, Scott Wood wrote:
On 06/05/2012 04:08 AM, Zhao Chenhui wrote:
On Fri, Jun 01, 2012 at 10:40:00AM -0500, Scott Wood wrote:
I know you say this is for dual-core chips only, but it would be nice if
you'd write this in a way that doesn't assume
On Tue, Jun 05, 2012 at 11:15:52AM -0500, Scott Wood wrote:
On 06/05/2012 06:18 AM, Zhao Chenhui wrote:
On Mon, Jun 04, 2012 at 11:32:47AM -0500, Scott Wood wrote:
On 06/04/2012 06:04 AM, Zhao Chenhui wrote:
On Fri, Jun 01, 2012 at 04:27:27PM -0500, Scott Wood wrote:
On 05/11/2012 06:53
On Tue, Jun 05, 2012 at 10:58:41AM -0500, Scott Wood wrote:
On 06/05/2012 05:59 AM, Zhao Chenhui wrote:
On Fri, Jun 01, 2012 at 06:30:55PM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
The jog mode frequency transition process on the MPC8536 is similar to
the deep
On Wed, Jun 06, 2012 at 01:26:16PM -0500, Scott Wood wrote:
On 06/06/2012 04:31 AM, Zhao Chenhui wrote:
On Tue, Jun 05, 2012 at 11:07:41AM -0500, Scott Wood wrote:
On 06/05/2012 04:08 AM, Zhao Chenhui wrote:
On Fri, Jun 01, 2012 at 10:40:00AM -0500, Scott Wood wrote:
I know you say
On Fri, Jun 01, 2012 at 10:40:00AM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
#ifdef CONFIG_KEXEC
+static struct ccsr_guts __iomem *guts;
+static u64 timebase;
+static int tb_req;
+static int tb_valid;
+
+static void mpc85xx_timebase_freeze(int freeze
On Fri, Jun 01, 2012 at 06:30:55PM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
Some 85xx silicons like MPC8536 and P1022 have a JOG feature, which provides
a dynamic mechanism to lower or raise the CPU core clock at runtime.
Is there a reason P1023 isn't supported
On Mon, Jun 04, 2012 at 11:32:47AM -0500, Scott Wood wrote:
On 06/04/2012 06:04 AM, Zhao Chenhui wrote:
On Fri, Jun 01, 2012 at 04:27:27PM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
-#ifdef CONFIG_KEXEC
+#if defined(CONFIG_KEXEC) || defined(CONFIG_HOTPLUG_CPU
On Mon, Jun 04, 2012 at 05:58:38PM -0500, Scott Wood wrote:
On 06/04/2012 06:12 AM, Zhao Chenhui wrote:
On Fri, Jun 01, 2012 at 04:54:35PM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
diff --git a/arch/powerpc/include/asm/cacheflush.h
b/arch/powerpc/include/asm
On Fri, Jun 01, 2012 at 04:27:27PM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
\ +#if defined(CONFIG_FSL_BOOKE) || defined(CONFIG_6xx)
+extern void __flush_disable_L1(void);
+#endif
Prototypes aren't normally guarded by ifdefs.
OK. Thanks.
+static void
On Fri, Jun 01, 2012 at 04:54:35PM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
From: Li Yang le...@freescale.com
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running
On Fri, Jun 01, 2012 at 05:08:52PM -0500, Scott Wood wrote:
On 05/11/2012 06:53 AM, Zhao Chenhui wrote:
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed
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