Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE
Excerpts from Mathieu Desnoyers's message of July 9, 2020 12:12 am: > - On Jul 8, 2020, at 1:17 AM, Nicholas Piggin npig...@gmail.com wrote: > >> Excerpts from Mathieu Desnoyers's message of July 7, 2020 9:25 pm: >>> - On Jul 7, 2020, at 1:50 AM, Nicholas Piggin npig...@gmail.com wrote: >>> > [...] I should actually change the comment for 64-bit because soft masked interrupt replay is an interesting case. I thought it was okay (because the IPI would cause a hard interrupt which does do the rfi) but that should at least be written. >>> >>> Yes. >>> The context synchronisation happens before the Linux IPI function is called, but for the purpose of membarrier I think that is okay (the membarrier just needs to have caused a memory barrier + context synchronistaion by the time it has done). >>> >>> Can you point me to the code implementing this logic ? >> >> It's mostly in arch/powerpc/kernel/exception-64s.S and >> powerpc/kernel/irq.c, but a lot of asm so easier to explain. >> >> When any Linux code does local_irq_disable(), we set interrupts as >> software-masked in a per-cpu flag. When interrupts (including IPIs) come >> in, the first thing we do is check that flag and if we are masked, then >> record that the interrupt needs to be "replayed" in another per-cpu >> flag. The interrupt handler then exits back using RFI (which is context >> synchronising the CPU). Later, when the kernel code does >> local_irq_enable(), it checks the replay flag to see if anything needs >> to be done. At that point we basically just call the interrupt handler >> code like a normal function, and when that returns there is no context >> synchronising instruction. > > AFAIU this can only happen for interrupts nesting over irqoff sections, > therefore over kernel code, never userspace, right ? Right. >> So membarrier IPI will always cause target CPUs to perform a context >> synchronising instruction, but sometimes it happens before the IPI >> handler function runs. > > If my understanding is correct, the replayed interrupt handler logic > only nests over kernel code, which will eventually need to issue a > context synchronizing instruction before returning to user-space. Yes. > All we care about is that starting from the membarrier, each core > either: > > - interrupt user-space to issue the context synchronizing instruction if > they were running userspace, or > - _eventually_ issue a context synchronizing instruction before returning > to user-space if they were running kernel code. > > So your earlier statement "the membarrier just needs to have caused a memory > barrier + context synchronistaion by the time it has done" is not strictly > correct: the context synchronizing instruction does not strictly need to > happen on each core before membarrier returns. A similar line of thoughts > can be followed for memory barriers. Ah okay that makes it simpler, then no such speical comment is required for the powerpc specific interrupt handling. Thanks, Nick
Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE
- On Jul 8, 2020, at 1:17 AM, Nicholas Piggin npig...@gmail.com wrote: > Excerpts from Mathieu Desnoyers's message of July 7, 2020 9:25 pm: >> - On Jul 7, 2020, at 1:50 AM, Nicholas Piggin npig...@gmail.com wrote: >> [...] >>> I should actually change the comment for 64-bit because soft masked >>> interrupt replay is an interesting case. I thought it was okay (because >>> the IPI would cause a hard interrupt which does do the rfi) but that >>> should at least be written. >> >> Yes. >> >>> The context synchronisation happens before >>> the Linux IPI function is called, but for the purpose of membarrier I >>> think that is okay (the membarrier just needs to have caused a memory >>> barrier + context synchronistaion by the time it has done). >> >> Can you point me to the code implementing this logic ? > > It's mostly in arch/powerpc/kernel/exception-64s.S and > powerpc/kernel/irq.c, but a lot of asm so easier to explain. > > When any Linux code does local_irq_disable(), we set interrupts as > software-masked in a per-cpu flag. When interrupts (including IPIs) come > in, the first thing we do is check that flag and if we are masked, then > record that the interrupt needs to be "replayed" in another per-cpu > flag. The interrupt handler then exits back using RFI (which is context > synchronising the CPU). Later, when the kernel code does > local_irq_enable(), it checks the replay flag to see if anything needs > to be done. At that point we basically just call the interrupt handler > code like a normal function, and when that returns there is no context > synchronising instruction. AFAIU this can only happen for interrupts nesting over irqoff sections, therefore over kernel code, never userspace, right ? > > So membarrier IPI will always cause target CPUs to perform a context > synchronising instruction, but sometimes it happens before the IPI > handler function runs. If my understanding is correct, the replayed interrupt handler logic only nests over kernel code, which will eventually need to issue a context synchronizing instruction before returning to user-space. All we care about is that starting from the membarrier, each core either: - interrupt user-space to issue the context synchronizing instruction if they were running userspace, or - _eventually_ issue a context synchronizing instruction before returning to user-space if they were running kernel code. So your earlier statement "the membarrier just needs to have caused a memory barrier + context synchronistaion by the time it has done" is not strictly correct: the context synchronizing instruction does not strictly need to happen on each core before membarrier returns. A similar line of thoughts can be followed for memory barriers. Thanks, Mathieu -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com
Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE
Excerpts from Mathieu Desnoyers's message of July 7, 2020 9:25 pm: > - On Jul 7, 2020, at 1:50 AM, Nicholas Piggin npig...@gmail.com wrote: > >> Excerpts from Christophe Leroy's message of July 6, 2020 7:53 pm: >>> >>> >>> Le 06/07/2020 à 04:18, Nicholas Piggin a écrit : diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 47bd4ea0837d..b88cb3a989b6 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -68,6 +68,10 @@ * * The nop instructions allow us to insert one or more instructions to flush the * L1-D cache when returning to userspace or a guest. + * + * powerpc relies on return from interrupt/syscall being context synchronising + * (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE + * without additional additional synchronisation instructions. >>> >>> This file is dedicated to BOOK3S/64. What about other ones ? >>> >>> On 32 bits, this is also valid as 'rfi' is also context synchronising, >>> but then why just add some comment in exception-64s.h and only there ? >> >> Yeah you're right, I basically wanted to keep a note there just in case, >> because it's possible we would get a less synchronising return (maybe >> unlikely with meltdown) or even return from a kernel interrupt using a >> something faster (e.g., bctar if we don't use tar register in the kernel >> anywhere). >> >> So I wonder where to add the note, entry_32.S and 64e.h as well? >> > > For 64-bit powerpc, I would be tempted to either place the comment in the > header > implementing the RFI_TO_USER and RFI_TO_USER_OR_KERNEL macros or the .S files > using them, e.g. either: > > arch/powerpc/include/asm/exception-64e.h > arch/powerpc/include/asm/exception-64s.h > > or > > arch/powerpc/kernel/exceptions-64s.S > arch/powerpc/kernel/entry_64.S > > And for 32-bit powerpc, AFAIU > > arch/powerpc/kernel/entry_32.S > > uses SYNC + RFI to return to user-space. RFI is defined in > > arch/powerpc/include/asm/ppc_asm.h > > So a comment either near the RFI define and its uses should work. > >> I should actually change the comment for 64-bit because soft masked >> interrupt replay is an interesting case. I thought it was okay (because >> the IPI would cause a hard interrupt which does do the rfi) but that >> should at least be written. > > Yes. > >> The context synchronisation happens before >> the Linux IPI function is called, but for the purpose of membarrier I >> think that is okay (the membarrier just needs to have caused a memory >> barrier + context synchronistaion by the time it has done). > > Can you point me to the code implementing this logic ? It's mostly in arch/powerpc/kernel/exception-64s.S and powerpc/kernel/irq.c, but a lot of asm so easier to explain. When any Linux code does local_irq_disable(), we set interrupts as software-masked in a per-cpu flag. When interrupts (including IPIs) come in, the first thing we do is check that flag and if we are masked, then record that the interrupt needs to be "replayed" in another per-cpu flag. The interrupt handler then exits back using RFI (which is context synchronising the CPU). Later, when the kernel code does local_irq_enable(), it checks the replay flag to see if anything needs to be done. At that point we basically just call the interrupt handler code like a normal function, and when that returns there is no context synchronising instruction. So membarrier IPI will always cause target CPUs to perform a context synchronising instruction, but sometimes it happens before the IPI handler function runs. Thanks, Nick
Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE
Le 07/07/2020 à 13:25, Mathieu Desnoyers a écrit : - On Jul 7, 2020, at 1:50 AM, Nicholas Piggin npig...@gmail.com wrote: Excerpts from Christophe Leroy's message of July 6, 2020 7:53 pm: Le 06/07/2020 à 04:18, Nicholas Piggin a écrit : diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 47bd4ea0837d..b88cb3a989b6 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -68,6 +68,10 @@ * * The nop instructions allow us to insert one or more instructions to flush the * L1-D cache when returning to userspace or a guest. + * + * powerpc relies on return from interrupt/syscall being context synchronising + * (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE + * without additional additional synchronisation instructions. This file is dedicated to BOOK3S/64. What about other ones ? On 32 bits, this is also valid as 'rfi' is also context synchronising, but then why just add some comment in exception-64s.h and only there ? Yeah you're right, I basically wanted to keep a note there just in case, because it's possible we would get a less synchronising return (maybe unlikely with meltdown) or even return from a kernel interrupt using a something faster (e.g., bctar if we don't use tar register in the kernel anywhere). So I wonder where to add the note, entry_32.S and 64e.h as well? For 64-bit powerpc, I would be tempted to either place the comment in the header implementing the RFI_TO_USER and RFI_TO_USER_OR_KERNEL macros or the .S files using them, e.g. either: arch/powerpc/include/asm/exception-64e.h arch/powerpc/include/asm/exception-64s.h or arch/powerpc/kernel/exceptions-64s.S arch/powerpc/kernel/entry_64.S And for 32-bit powerpc, AFAIU arch/powerpc/kernel/entry_32.S uses SYNC + RFI to return to user-space. RFI is defined in arch/powerpc/include/asm/ppc_asm.h So a comment either near the RFI define and its uses should work. For 32-bit, RFI is likely to go away the day 40x goes away, so I wouldn't put it there. Places like head_8xx.S use rfi not RFI. And the SYNC is about to go when we decide to retire 601 SYNC FIX. So it would be probably better to put it somewhere in entry_32.S Christophe
Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE
- On Jul 7, 2020, at 1:50 AM, Nicholas Piggin npig...@gmail.com wrote: > Excerpts from Christophe Leroy's message of July 6, 2020 7:53 pm: >> >> >> Le 06/07/2020 à 04:18, Nicholas Piggin a écrit : >>> diff --git a/arch/powerpc/include/asm/exception-64s.h >>> b/arch/powerpc/include/asm/exception-64s.h >>> index 47bd4ea0837d..b88cb3a989b6 100644 >>> --- a/arch/powerpc/include/asm/exception-64s.h >>> +++ b/arch/powerpc/include/asm/exception-64s.h >>> @@ -68,6 +68,10 @@ >>>* >>>* The nop instructions allow us to insert one or more instructions to >>> flush the >>>* L1-D cache when returning to userspace or a guest. >>> + * >>> + * powerpc relies on return from interrupt/syscall being context >>> synchronising >>> + * (which hrfid, rfid, and rfscv are) to support >>> ARCH_HAS_MEMBARRIER_SYNC_CORE >>> + * without additional additional synchronisation instructions. >> >> This file is dedicated to BOOK3S/64. What about other ones ? >> >> On 32 bits, this is also valid as 'rfi' is also context synchronising, >> but then why just add some comment in exception-64s.h and only there ? > > Yeah you're right, I basically wanted to keep a note there just in case, > because it's possible we would get a less synchronising return (maybe > unlikely with meltdown) or even return from a kernel interrupt using a > something faster (e.g., bctar if we don't use tar register in the kernel > anywhere). > > So I wonder where to add the note, entry_32.S and 64e.h as well? > For 64-bit powerpc, I would be tempted to either place the comment in the header implementing the RFI_TO_USER and RFI_TO_USER_OR_KERNEL macros or the .S files using them, e.g. either: arch/powerpc/include/asm/exception-64e.h arch/powerpc/include/asm/exception-64s.h or arch/powerpc/kernel/exceptions-64s.S arch/powerpc/kernel/entry_64.S And for 32-bit powerpc, AFAIU arch/powerpc/kernel/entry_32.S uses SYNC + RFI to return to user-space. RFI is defined in arch/powerpc/include/asm/ppc_asm.h So a comment either near the RFI define and its uses should work. > I should actually change the comment for 64-bit because soft masked > interrupt replay is an interesting case. I thought it was okay (because > the IPI would cause a hard interrupt which does do the rfi) but that > should at least be written. Yes. > The context synchronisation happens before > the Linux IPI function is called, but for the purpose of membarrier I > think that is okay (the membarrier just needs to have caused a memory > barrier + context synchronistaion by the time it has done). Can you point me to the code implementing this logic ? Thanks, Mathieu > > Thanks, > Nick -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com
Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE
Excerpts from Christophe Leroy's message of July 6, 2020 7:53 pm: > > > Le 06/07/2020 à 04:18, Nicholas Piggin a écrit : >> diff --git a/arch/powerpc/include/asm/exception-64s.h >> b/arch/powerpc/include/asm/exception-64s.h >> index 47bd4ea0837d..b88cb3a989b6 100644 >> --- a/arch/powerpc/include/asm/exception-64s.h >> +++ b/arch/powerpc/include/asm/exception-64s.h >> @@ -68,6 +68,10 @@ >>* >>* The nop instructions allow us to insert one or more instructions to >> flush the >>* L1-D cache when returning to userspace or a guest. >> + * >> + * powerpc relies on return from interrupt/syscall being context >> synchronising >> + * (which hrfid, rfid, and rfscv are) to support >> ARCH_HAS_MEMBARRIER_SYNC_CORE >> + * without additional additional synchronisation instructions. > > This file is dedicated to BOOK3S/64. What about other ones ? > > On 32 bits, this is also valid as 'rfi' is also context synchronising, > but then why just add some comment in exception-64s.h and only there ? Yeah you're right, I basically wanted to keep a note there just in case, because it's possible we would get a less synchronising return (maybe unlikely with meltdown) or even return from a kernel interrupt using a something faster (e.g., bctar if we don't use tar register in the kernel anywhere). So I wonder where to add the note, entry_32.S and 64e.h as well? I should actually change the comment for 64-bit because soft masked interrupt replay is an interesting case. I thought it was okay (because the IPI would cause a hard interrupt which does do the rfi) but that should at least be written. The context synchronisation happens before the Linux IPI function is called, but for the purpose of membarrier I think that is okay (the membarrier just needs to have caused a memory barrier + context synchronistaion by the time it has done). Thanks, Nick
Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE
Le 06/07/2020 à 04:18, Nicholas Piggin a écrit : powerpc return from interrupt and return from system call sequences are context synchronising. Signed-off-by: Nicholas Piggin --- .../features/sched/membarrier-sync-core/arch-support.txt | 4 ++-- arch/powerpc/Kconfig | 1 + arch/powerpc/include/asm/exception-64s.h | 4 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt index 8a521a622966..52ad74a25f54 100644 --- a/Documentation/features/sched/membarrier-sync-core/arch-support.txt +++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt @@ -5,7 +5,7 @@ # # Architecture requirements # -# * arm/arm64 +# * arm/arm64/powerpc # # Rely on implicit context synchronization as a result of exception return # when returning from IPI handler, and when returning to user-space. @@ -45,7 +45,7 @@ | nios2: | TODO | |openrisc: | TODO | | parisc: | TODO | -| powerpc: | TODO | +| powerpc: | ok | | riscv: | TODO | |s390: | TODO | | sh: | TODO | diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 9fa23eb320ff..920c4e3ca4ef 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -131,6 +131,7 @@ config PPC select ARCH_HAS_PTE_DEVMAP if PPC_BOOK3S_64 select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_MEMBARRIER_CALLBACKS + select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64 select ARCH_HAS_STRICT_KERNEL_RWX if (PPC32 && !HIBERNATION) select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 47bd4ea0837d..b88cb3a989b6 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -68,6 +68,10 @@ * * The nop instructions allow us to insert one or more instructions to flush the * L1-D cache when returning to userspace or a guest. + * + * powerpc relies on return from interrupt/syscall being context synchronising + * (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE + * without additional additional synchronisation instructions. This file is dedicated to BOOK3S/64. What about other ones ? On 32 bits, this is also valid as 'rfi' is also context synchronising, but then why just add some comment in exception-64s.h and only there ? */ #define RFI_FLUSH_SLOT \ RFI_FLUSH_FIXUP_SECTION;\ Christophe
