Re: [PATCH 2/2] Add PCI/PCI Express node for 8544DS board]

[Segher Boessenkool]

It looks real good now :-)

One tiny comment...

 + [EMAIL PROTECTED] {
 + compatible = fsl,mpc8548-pcie;

I would name the node [EMAIL PROTECTED] instead; generic names
aren't for machine consumption anyway, and most humans
want to know which buses are plain PCI vs. PCI-X vs.
PCI Express.

This could be changed with a follow-up patch of course.


Segher

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[PATCH 2/2] Add PCI/PCI Express node for 8544DS board]

[Zang Roy-r61911]

From: Roy Zang [EMAIL PROTECTED]

Add PCI/PCI Express node for 8544DS board.

---
 arch/powerpc/boot/dts/mpc8544ds.dts |  211 +++
 1 files changed, 211 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts 
b/arch/powerpc/boot/dts/mpc8544ds.dts
index 43bf5c1..aab0bc6 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -143,6 +143,217 @@
fsl,has-rstcr;
};
 
+   [EMAIL PROTECTED] {
+   compatible = fsl,mpc8540-pci;
+   device_type = pci;
+   interrupt-map-mask = f800 0 0 7;
+   interrupt-map = 
+
+   /* IDSEL 0x11 J17 Slot 1 */
+   8800 0 0 1 mpic 2 1
+   8800 0 0 2 mpic 3 1
+   8800 0 0 3 mpic 4 1
+   8800 0 0 4 mpic 1 1
+
+   /* IDSEL 0x12 J16 Slot 2 */
+
+   9000 0 0 1 mpic 3 1
+   9000 0 0 2 mpic 4 1
+   9000 0 0 3 mpic 2 1
+   9000 0 0 4 mpic 1 1;
+
+   interrupt-parent = mpic;
+   interrupts = 18 2;
+   bus-range = 0 ff;
+   ranges = 0200 0 8000 8000 0 1000
+ 0100 0  e200 0 0080;
+   clock-frequency = 3f940aa;
+   #interrupt-cells = 1;
+   #size-cells = 2;
+   #address-cells = 3;
+   reg = 8000 1000;
+   };
+
+   [EMAIL PROTECTED] {
+   compatible = fsl,mpc8548-pcie;
+   device_type = pci;
+   #interrupt-cells = 1;
+   #size-cells = 2;
+   #address-cells = 3;
+   reg = a000 1000;
+   bus-range = 0 ff;
+   ranges = 0200 0 9000 9000 0 1000
+ 0100 0  e280 0 0080;
+   clock-frequency = 1fca055;
+   interrupt-parent = mpic;
+   interrupts = 19 2;
+   interrupt-map-mask = f800 0 0 7;
+   interrupt-map = 
+   /* IDSEL 0x0 */
+    0 0 1 mpic 0 1
+    0 0 2 mpic 1 1
+    0 0 3 mpic 2 1
+    0 0 4 mpic 3 1
+   ;
+   };
+
+   [EMAIL PROTECTED] {
+   compatible = fsl,mpc8548-pcie;
+   device_type = pci;
+   #interrupt-cells = 1;
+   #size-cells = 2;
+   #address-cells = 3;
+   reg = 9000 1000;
+   bus-range = 0 ff;
+   ranges = 0200 0 a000 a000 0 1000
+ 0100 0  e300 0 0080;
+   clock-frequency = 1fca055;
+   interrupt-parent = mpic;
+   interrupts = 1a 2;
+   interrupt-map-mask = f800 0 0 7;
+   interrupt-map = 
+   /* IDSEL 0x0 */
+    0 0 1 mpic 4 1
+    0 0 2 mpic 5 1
+    0 0 3 mpic 6 1
+    0 0 4 mpic 7 1
+   ;
+   };
+
+   [EMAIL PROTECTED] {
+   compatible = fsl,mpc8548-pcie;
+   device_type = pci;
+   #interrupt-cells = 1;
+   #size-cells = 2;
+   #address-cells = 3;
+   reg = b000 1000;
+   bus-range = 0 ff;
+   ranges = 0200 0 b000 b000 0 1000
+ 0100 0  e380 0 0080;
+   clock-frequency = 1fca055;
+   interrupt-parent = mpic;
+   interrupts = 1b 2;
+   interrupt-map-mask = f800 0 0 7;
+   interrupt-map = 
+
+   // IDSEL 0x1a
+   d000 0 0 1 i8259 6 2
+   d000 0 0 2 i8259 3 2
+   d000 0 0 3 i8259 4 2
+   d000 0 0 4 i8259 5 2
+
+   // IDSEL 0x1b
+   d800 0 0 1 i8259 5 2
+