Hi Anatolij,
we have tried again… but the problem is still there… we are not able to
read/write, not only CS4, but also CS1, CS2, CS3, etc…
According to you, could we fix the problem if we include our Virtex FPGA in
Device Tree?
U-Boot has been patched (not by us), for CS4, with:
+#define
Hello Anatolij, this is our code, used at University, but again it doesn’t work…
How i told, the only information we have about that reg are:
Chip select 4 specification:
Lp_cs4
bus size: 8 bit
bus control: 2 wait state R/W ACK disabled
size allocated: 4 KByte
Our Register 8 bit LP_cs4 (we want
Hi Lorenzo,
On Tue, 19 Nov 2013 11:20:24 +0100
neorf3k neor...@gmail.com wrote:
Hello Anatolij, this is our code, used at University, but again it doesn’t
work…
How i told, the only information we have about that reg are:
Chip select 4 specification:
Lp_cs4
bus size: 8 bit
bus
Hi Lorenzo,
see my comments below.
On Fri, 15 Nov 2013 17:27:30 +0100
neorf3k neor...@gmail.com wrote:
Hello again, I’ve tried this code, but we are not able to
change cs4 reg value… what could be?
—
#define MALab_DEVICE_NAME MALab
#define MPC5xxx_MM_CS4_START (MBAR_BASE + 0x0024)
Hi Anatolij,
thank you so much for you answer… monday i’ll test…
i answer you just to complete the information:
we are using an mpc5200b and the details for that reg located at: 0x1002
are:
Chip select 4 specification:
Lp_cs4
bus size: 8 bit
bus control: 2 wait state R/W ACK disabled
size
Hello again, I’ve tried this code, but we are not able to change cs4 reg value…
what could be?
—
#define MALab_DEVICE_NAME MALab
#define MPC5xxx_MM_CS4_START(MBAR_BASE + 0x0024)
#define MPC5xxx_MM_CS4_STOP (MBAR_BASE + 0x0028)
#define MPC5xxx_MM_IPBI (MBAR_BASE + 0x0054)
#define
Thank you again…
we have checked, and the settings in Chip Select 4 Configuration, seems to be
ok…
The strange thing is the return value from ioremap(). In U-Boot return value
from address 0x1002000 is 0x45f80360… if we try to map it in our module, then
we use ioremap(), return value is
Sorry, the address is 0x1002.
I've executed this code:
/* code */
unsigned char *virt_base;
u8 regval;
/* map 4kbyte reg. space */
virt_base = ioremap(0x1002, 0x1000);
if (!virt_base) {
printk(fpga ioremap failed\n);
return;
}
regval =
Yes, that is a device on the lpb via an fpga. We have tried to configure the
chip select 4 configuration register at address MBAR + 0x0310, and it seems to
be ok. what do you mean with “chip select parameters”?
We have been able to edit it in U-BOOT, and the board (that chip) now works…
The
On Wed, 13 Nov 2013 14:48:24 +0100
neorf3k neor...@gmail.com wrote:
Yes, that is a device on the lpb via an fpga. We have tried to configure
the chip select 4 configuration register at address MBAR + 0x0310, and it
seems to be ok. what do you mean with “chip select parameters”?
I meant the
we have tried to read and program an 8bit register with 32bit address. we have
mapped it with: ioremap, kmalloc etc… and then using: outb, iowrite8 etc.. but
when we write to it, the value doesn’t change… with other memory location is ok.
That is an 8 bit register, located at 0x1002 in a
On Tue, 12 Nov 2013 20:23:20 +0100
neorf3k neor...@gmail.com wrote:
we have tried to read and program an 8bit register with 32bit address.
we have mapped it with: ioremap, kmalloc etc… and then using: outb,
iowrite8 etc.. but when we write to it, the value doesn’t change…
with other memory
12 matches
Mail list logo
