[PATCH v4 2/2] cxl: Report the tunneled operations status

Failure to synchronize the tunneled operations does not prevent the initialization of the cxl card. This patch reports the tunneled operations status via /sys. Signed-off-by: Philippe Bergheaud --- v3: Added this patch to report the tunneled operations status. v4: Updated

Re: [PATCH] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

On Friday 11 May 2018 07:13 PM, Anju T Sudhakar wrote: Currently memory is allocated for core-imc based on cpu_present_mask, which has bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) as as array index to access the memory. So in a system with guarded cores, since

[PATCH] powerpc/cpu: nr_cpu_ids should be aligned on threads_per_core

With p8 subcore mode, if nr_cpus is not aligned on threads_per_core, then we will hit the following panic: [0.310006] Unpacking initramfs... [1.105015] Freeing initrd memory: 35968K [1.105466] rtas_flash: no firmware flash support [1.105688] Unable to handle kernel paging

Re: [powerpc:merge 138/138] arch/powerpc/kernel/setup_64.c:354:2: error: implicit declaration of function 'this_cpu_enable_ftrace'; did you mean 'preempt_enable_notrace'?

kbuild test robot writes: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git > merge > head: 900be8ab1549359ba980cfb042a043128204a963 > commit: 900be8ab1549359ba980cfb042a043128204a963 [138/138] Automatic merge of > branches 'master', 'next' and

Re: [PATCH] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

On Saturday 12 May 2018 05:15 AM, Michael Neuling wrote: On Fri, 2018-05-11 at 19:13 +0530, Anju T Sudhakar wrote: Currently memory is allocated for core-imc based on cpu_present_mask, which has bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) as as array index to

Re: [PATCH 2/3] hwmon: (ibmpowernv): Add support to read 64 bit sensors

Guenter Roeck writes: > On Mon, May 07, 2018 at 03:55:37PM +0530, Shilpasri G Bhat wrote: >> The firmware has supported for reading sensor values of size u32. >> This patch adds support to use newer firmware functions which allows >> to read the sensors of size u64. >> >>

RE: [PATCH 3/9] soc: fsl: set rcpm bit for FTM

-Original Message- From: Leo Li Sent: 2018年5月12日 1:00 To: Yinbo Zhu ; Yinbo Zhu ; Rob Herring ; Mark Rutland ; Catalin Marinas ) ; Will Deacon ) ; Lorenzo

[PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

Skiboot used to set the default Tunnel BAR register value when capi mode was enabled. This approach was ok for the cxl driver, but prevented other drivers from choosing different values. Skiboot versions > 5.11 will not set the default value any longer. This patch modifies the cxl driver to

Re: [PATCH] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

Hi, On Saturday 12 May 2018 06:05 AM, Balbir Singh wrote: On Fri, May 11, 2018 at 11:43 PM, Anju T Sudhakar wrote: Currently memory is allocated for core-imc based on cpu_present_mask, which has bit 'cpu' set iff cpu is populated. We use (cpu number / threads per

Re: [PATCH v2 4/4] powerpc: Allow LD_DEAD_CODE_DATA_ELIMINATION to be selected

On Wed, May 9, 2018 at 3:00 PM, Nicholas Piggin wrote: > This requires further changes to linker script to KEEP some tables > and wildcard compiler generated sections into the right place. This > includes pp32 modifications from Christophe Leroy. > > When compiling

Re: [PATCH v3 4/4] powerpc/kbuild: move -mprofile-kernel check to Kconfig

-language/20180514-120748 base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next config: powerpc-defconfig compiler: powerpc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin

Re: [PATCH] powerpc/cpu: nr_cpu_ids should be aligned on threads_per_core

/commits/Pingfan-Liu/powerpc-cpu-nr_cpu_ids-should-be-aligned-on-threads_per_core/20180514-141629 base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next config: powerpc-allnoconfig (attached as .config) compiler: powerpc-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce

[PATCH kernel v3] powerpc/ioda: Use ibm, supported-tce-sizes for IOMMU page size mask

At the moment we assume that IODA2 and newer PHBs can always do 4K/64K/16M IOMMU pages, however this is not the case for POWER9 and now skiboot advertises the supported sizes via the device so we use that instead of hard coding the mask. Signed-off-by: Alexey Kardashevskiy ---

[PATCH 2/3] powerpc/powernv: Use __raw_[rm_]writeq_be() in pci-ioda.c

This allows us to squash some sparse warnings and also avoids having to do explicity endian conversions in the code. Signed-off-by: Michael Ellerman --- arch/powerpc/platforms/powernv/pci-ioda.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff

[RFC][PATCH bpf v3 4/5] tools: bpf: sync bpf uapi header

Syncing the bpf.h uapi header with tools so that struct bpf_prog_info has the new fields for storing the kernel symbol addresses for the JITed functions in a program. Signed-off-by: Sandipan Das --- tools/include/uapi/linux/bpf.h | 2 ++ 1 file changed, 2

Re: [PATCH v4 5/6] bus: fsl-mc: supoprt dma configure for devices on fsl-mc bus

On Mon, Apr 30, 2018 at 11:57:20AM +0530, Nipun Gupta wrote: > Signed-off-by: Nipun Gupta > --- I can't take patches without any changelog text at all, sorry. Please fix up and resend. greg k-h

[RFC][PATCH bpf v3 2/5] bpf: powerpc64: add JIT support for multi-function programs

This adds support for bpf-to-bpf function calls in the powerpc64 JIT compiler. The JIT compiler converts the bpf call instructions to native branch instructions. After a round of the usual passes, the start addresses of the JITed images for the callee functions are known. Finally, to fixup the

[PATCH 1/3] powerpc/io: Add __raw_writeq_be() __raw_rm_writeq_be()

Add byte-swapping versions of __raw_writeq() and __raw_rm_writeq(). This allows us to avoid sparse warnings caused by passing __be64 to __raw_writeq(), which takes unsigned long: arch/powerpc/platforms/powernv/pci-ioda.c:1981:38: warning: incorrect type in argument 1 (different base types)

Re: [PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

On 14/05/2018 12:51, Michael Ellerman wrote: Philippe Bergheaud writes: Skiboot used to set the default Tunnel BAR register value when capi mode was enabled. This approach was ok for the cxl driver, but prevented other drivers from choosing different values. Skiboot

[RFC][PATCH bpf v3 5/5] tools: bpftool: resolve call addresses without using imm field

Currently, we resolve the callee's address for a JITed function call by using the imm field of the call instruction as an offset from __bpf_call_base. If bpf_jit_kallsyms is enabled, we further use this address to get the callee's kernel symbol's name. For some architectures, such as powerpc64,

[PATCH 1/2] powerpc: Rename thread_struct.fs to addr_limit

It's called 'fs' for historical reasons, it's named after the x86 'FS' register. But we don't have to use that name for the member of thread_struct, and in fact arch/x86 doesn't even call it 'fs' anymore. So rename it to 'addr_limit', which better reflects what it's used for, and is also the name

Re: [PATCH 5/6 v3] bus: fsl-mc: supoprt dma configure for devices on fsl-mc bus

Hi Nipun, On 04/27/2018 01:27 PM, Nipun Gupta wrote: > Signed-off-by: Nipun Gupta > --- > drivers/bus/fsl-mc/fsl-mc-bus.c | 16 > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c

Re: [PATCH 2/3] hwmon: (ibmpowernv): Add support to read 64 bit sensors

On 05/14/2018 12:11 AM, Michael Ellerman wrote: Guenter Roeck writes: On Mon, May 07, 2018 at 03:55:37PM +0530, Shilpasri G Bhat wrote: The firmware has supported for reading sensor values of size u32. This patch adds support to use newer firmware functions which allows

Re: [PATCH] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

Anju T Sudhakar writes: > On Saturday 12 May 2018 06:05 AM, Balbir Singh wrote: >> On Fri, May 11, 2018 at 11:43 PM, Anju T Sudhakar >> wrote: >>> Currently memory is allocated for core-imc based on cpu_present_mask, which >>> has >>> bit 'cpu'

Re: [PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

Philippe Bergheaud writes: > Skiboot used to set the default Tunnel BAR register value when capi mode > was enabled. This approach was ok for the cxl driver, but prevented other > drivers from choosing different values. > > Skiboot versions > 5.11 will not set the default

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On 05/09/2018 04:41 PM, Andy Lutomirski wrote: Hmm. I can get on board with the idea that fork() / clone() / pthread_create() are all just special cases of the idea that the thread that*calls* them should have the right pkey values, and the latter is already busted given our inability to

[RFC][PATCH bpf v3 1/5] bpf: allow 64-bit offsets for bpf function calls

The imm field of a bpf instruction is a signed 32-bit integer. For JIT bpf-to-bpf function calls, it stores the offset of the start address of the callee's JITed image from __bpf_call_base. For some architectures, such as powerpc64, this offset may be as large as 64 bits and cannot be accomodated

Re: [PATCH v4 5/6] bus: fsl-mc: supoprt dma configure for devices on fsl-mc bus

When you add the changleog, please also fix the subject typo: - bus: fsl-mc: supoprt dma configure for devices on fsl-mc bus ^^^ + bus: fsl-mc: support dma configure for devices on fsl-mc bus On Mon, Apr 30, 2018 at 11:57:20AM +0530, Nipun Gupta wrote: > Signed-off-by: Nipun

[PATCH 3/3] powerpc/powernv: Use __raw_[rm_]writeq_be() in npu-dma.c

This allows us to squash some sparse warnings and also avoids having to do explicity endian conversions in the code. Signed-off-by: Michael Ellerman --- arch/powerpc/platforms/powernv/npu-dma.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git

Re: [PATCH 1/2] crypto: vmx - Remove overly verbose printk from AES init routines

Herbert Xu writes: > On Thu, May 03, 2018 at 10:29:29PM +1000, Michael Ellerman wrote: >> In the vmx AES init routines we do a printk(KERN_INFO ...) to report >> the fallback implementation we're using. >> >> However with a slow console this can significantly affect

[PATCH 2/2] powerpc: Check address limit on user-mode return (TIF_FSCHECK)

set_fs() sets the addr_limit, which is used in access_ok() to determine if an address is a user or kernel address. Some code paths use set_fs() to temporarily elevate the addr_limit so that kernel code can read/write kernel memory as if it were user memory. That is fine as long as the code can't

[PATCH 1/2] powerpc/powernv: Fix opal_event_shutdown() called with interrupts disabled

A kernel crash in process context that calls emergency_restart from panic will end up calling opal_event_shutdown with interrupts disabled but not in interrupt. This causes a sleeping function to be called which gives the following warning with sysrq+c: Rebooting in 10 seconds.. BUG:

[PATCH 16/21] i2c: pasemi: make use of i2c_8bit_addr_from_msg

Because it looks neater. Signed-off-by: Peter Rosin --- drivers/i2c/busses/i2c-pasemi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-pasemi.c b/drivers/i2c/busses/i2c-pasemi.c index df1dbc92a024..55fd5c6f3cca 100644 ---

Re: [PATCH v3 3/4] powerpc/kbuild: Use flags variables rather than overriding LD/CC/AS

On Mon, 14 May 2018 13:52:27 +1000 Nicholas Piggin wrote: > The powerpc toolchain can compile combinations of 32/64 bit and > big/little endian, so it's convenient to consider, e.g., > > `CC -m64 -mbig-endian` > > To be the C compiler for the purpose of invoking it to

[PATCH 0/2] sleeping functions in invalid context on panic fixes

Here's a couple of fixes which seem to solve a problem where panics can hang forever rather than reboot after 10 seconds. The symptoms are that a CPU calls panic(), but later it is found in idle. Nicholas Piggin (2): powerpc/powernv: Fix opal_event_shutdown() called with interrupts disabled

[PATCH 00/21] i2c: make use of i2c_8bit_addr_from_msg

Hi! The nice little inline i2c_8bit_addr_from_msg is not getting enough use. This series improves the situation and drops a bunch of lines in the process. I have only compile-tested (that part fine, at least over here). Cheers, Peter Peter Rosin (21): i2c: algo: bit: make use of

Re: [PATCH v10 02/25] x86/mm: define ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT

Laurent Dufour writes: > On 08/05/2018 13:04, Punit Agrawal wrote: >> Hi Laurent, >> >> Laurent Dufour writes: >> >>> Set ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT which turns on the >>> Speculative Page Fault handler when building for 64bit.

Re: [PATCH v10 06/25] mm: make pte_unmap_same compatible with SPF

On 10/05/2018 18:15, vinayak menon wrote: > On Tue, Apr 17, 2018 at 8:03 PM, Laurent Dufour > wrote: >> pte_unmap_same() is making the assumption that the page table are still >> around because the mmap_sem is held. >> This is no more the case when running a

Re: [PATCH v10 09/25] mm: protect VMA modifications using VMA sequence count

On 23/04/2018 09:19, Minchan Kim wrote: > On Tue, Apr 17, 2018 at 04:33:15PM +0200, Laurent Dufour wrote: >> The VMA sequence count has been introduced to allow fast detection of >> VMA modification when running a page fault handler without holding >> the mmap_sem. >> >> This patch provides

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On 05/14/2018 05:32 PM, Andy Lutomirski wrote: On May 14, 2018, at 5:01 AM, Florian Weimer wrote: One thing we could do, though: the current initual state on process creation is all access blocked on all keys. We could change it so that half the keys are fully blocked

Re: [PATCH v10 02/25] x86/mm: define ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT

On 08/05/2018 13:04, Punit Agrawal wrote: > Hi Laurent, > > Laurent Dufour writes: > >> Set ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT which turns on the >> Speculative Page Fault handler when building for 64bit. >> >> Cc: Thomas Gleixner >>

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

> On May 14, 2018, at 5:01 AM, Florian Weimer wrote: > >> One thing we could do, though: the current initual state on process >> creation is all access blocked on all keys. We could change it so that >> half the keys are fully blocked and half are read-only. Then we

[PATCH 2/2] powerpc/powernv: Fix NVRAM sleep in invalid context when crashing

Similarly to opal_event_shutdown, opal_nvram_write can be called in the crash path with irqs disabled. Special case the delay to avoid sleeping in invalid context. Cc: sta...@vger.kernel.org # v3.2 Fixes: 3b8070335f ("powerpc/powernv: Fix OPAL NVRAM driver OPAL_BUSY loops") Signed-off-by:

Re: [PATCH 00/21] i2c: make use of i2c_8bit_addr_from_msg

On Mon, 2018-05-14 at 16:53 +0200, Peter Rosin wrote: > Hi! > > The nice little inline i2c_8bit_addr_from_msg is not getting > enough use. This series improves the situation and drops a > bunch of lines in the process. Perhaps the inline should test for I2C_M_REV_DIR_ADDR as there is at least

[RFC][PATCH bpf v3 3/5] bpf: get JITed function addresses via syscall

This adds new two new fields to struct bpf_prog_info. For multi-function programs, these fields can be used to pass a list of kernel symbol addresses for all functions in a given program and to userspace using the bpf system call with the BPF_OBJ_GET_INFO_BY_FD command. When bpf_jit_kallsyms is

Re: [PATCH 4/4] powerpc: Allow LD_DEAD_CODE_DATA_ELIMINATION to be selected

On Wed, May 2, 2018 at 2:24 PM, Nicholas Piggin wrote: > On Wed, 2 May 2018 11:17:52 +0200 > Mathieu Malaterre wrote: > >> Nick, >> >> On Sat, Apr 21, 2018 at 4:48 AM, Nicholas Piggin wrote: >> > On Fri, 20 Apr 2018 22:08:27 +0200 >> >

Re: [PATCH 00/21] i2c: make use of i2c_8bit_addr_from_msg

On 2018-05-14 18:11, Joe Perches wrote: > On Mon, 2018-05-14 at 16:53 +0200, Peter Rosin wrote: >> Hi! >> >> The nice little inline i2c_8bit_addr_from_msg is not getting >> enough use. This series improves the situation and drops a >> bunch of lines in the process. > > Perhaps the inline should

[PATCH] powerpc/64: Fix for "make PACA_IRQ_HARD_DIS track MSR[EE] closely"

The patch "powerpc/64s: make PACA_IRQ_HARD_DIS track MSR[EE] closely" needs an equivalent change to the 64/e interrupt handler, to set PACA_IRQ_HARD_DIS when MSR[EE] gets cleared. Also the original patch should be named powerpc/64: rather than 64s:. Signed-off-by: Nicholas Piggin

[RFC PATCH 5/5] powerpc/powernv: export /proc/opaldump for analysing opal crashes

From: Hari Bathini Export /proc/opaldump file to analyze opal crashes Signed-off-by: Hari Bathini --- arch/powerpc/platforms/powernv/Makefile |2 arch/powerpc/platforms/powernv/opalcore.c | 282

[RFC PATCH 0/5] Add FADump support on PowerNV platform

Firmware-Assisted Dump (FADump) is currently supported only on pseries platform. This patch series adds support for powernv platform too. The first two patches refactor the FADump code to make use of common code across multiple platforms. The third patch adds basic FADump support to powernv

[RFC PATCH 3/5] powerpc/fadump: enable fadump support on powernv platform

From: Hari Bathini Firmware-assisted dump support is enabled for POWERNV platform in P9 firmware. Make the corresponding updates in kernel to enable fadump support on POWERNV platform. Signed-off-by: Hari Bathini ---

[RFC PATCH 4/5] powerpc/fadump: process architected register state data provided by firmware

From: Hari Bathini Firmware provides architected register state data at the time of crash. This data contains PIR value. Need to store the logical CPUs PIR values to match the data provided by f/w with the corresponding logical CPU. Signed-off-by: Hari Bathini

Re: [PATCH v3 3/4] powerpc/kbuild: Use flags variables rather than overriding LD/CC/AS

Steven Rostedt writes: > On Mon, 14 May 2018 13:52:27 +1000 > Nicholas Piggin wrote: >> The powerpc toolchain can compile combinations of 32/64 bit and >> big/little endian, so it's convenient to consider, e.g., >> >> `CC -m64 -mbig-endian` >> >> To be

Re: [PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

Philippe Bergheaud writes: > On 14/05/2018 12:51, Michael Ellerman wrote: >> Philippe Bergheaud writes: >> >>> Skiboot used to set the default Tunnel BAR register value when capi mode >>> was enabled. This approach was ok for the cxl driver, but

[RFC PATCH 2/5] pseries/fadump: move out platform specific support from generic code

Introduce callbacks for platform specific operations like register, unregister, invalidate & such, and move pseries specific code into platform code. Signed-off-by: Hari Bathini --- arch/powerpc/include/asm/fadump.h | 71 --- arch/powerpc/kernel/fadump.c

[RFC PATCH 1/5] powerpc/fadump: move internal fadump code to a new file

Refactoring fadump code means internal fadump code is referenced from different places. For ease, move internal code to a new file. Signed-off-by: Hari Bathini --- arch/powerpc/include/asm/fadump.h | 114 --- arch/powerpc/kernel/Makefile |