-20200717
i386 randconfig-a004-20200717
i386 randconfig-a001-20200719
i386 randconfig-a006-20200719
i386 randconfig-a002-20200719
i386 randconfig-a005-20200719
i386 randconfig-a003-20200719
i386
onfig-r024-20200719 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
ed6b578040a85977026c93bf4188f996148f3218)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am:
> Replace the variable name from using "pnv_first_spr_loss_level" to
> "pnv_first_fullstate_loss_level".
>
> As pnv_first_spr_loss_level is supposed to be the earliest state that
> has OPAL_PM_LOSE_FULL_CONTEXT set, however as
Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am:
> As the idle framework's architecture is incomplete, hence instead of
> checking for just the processor type advertised in the device tree CPU
> features; check for the Processor Version Register (PVR) so that finer
> granulari
Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am:
> POWER9 onwards the support for the registers HID1, HID4, HID5 has been
> receded.
> Although mfspr on the above registers worked in Power9, In Power10
> simulator is unrecognized. Moving their assignment under the
> check for
When I last looked at this (predating io_uring), as far as I remember it was
not permitted to actually switch to (use_mm) an mm user context that was
pinned with mmget_not_zero. Those pins were only allowed to look at page
tables, vmas, etc., but not actually run the CPU in that mm context.
spa
On Sun, Jul 19, 2020 at 5:13 AM Greg Thelen wrote:
>
> Oliver O'Halloran wrote:
>
> > On Mon, Jun 15, 2020 at 9:33 AM Greg Thelen wrote:
> >>
> >> Commit dc3d8f85bb57 ("powerpc/powernv/pci: Re-work bus PE
> >> configuration") removed a couple pnv_ioda_setup_bus_dma() calls. The
> >> only remain
On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria
wrote:
>
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Host generally uses "cpu-features",
> which masks "pa-features". But "cp
On Sun, 24 Nov 2019, Masahiro Yamada wrote:
> Collect the ignored patterns to is_ignored_symbol().
>
> Signed-off-by: Masahiro Yamada
This commit (887df76de67f5) caused a regression in my powerpc builds as it
causes symbol names to disappear from backtraces:
[ cut here ]--
On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria
wrote:
>
> Current H_SET_MODE hcall macro name for setting/resetting DAWR0 is
> H_SET_MODE_RESOURCE_SET_DAWR. Add suffix 0 to macro name as well.
>
> Signed-off-by: Ravi Bangoria
Reviewed-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/hvcall.h
> +static int vmap_pages_range_noflush(unsigned long start, unsigned long end,
> + pgprot_t prot, struct page **pages,
> + unsigned int page_shift)
> +{
> + if (page_shift == PAGE_SIZE) {
Is this a typo of PAGE_SHIFT?
> +
Excerpts from Zefan Li's message of July 20, 2020 12:02 pm:
>> +static int vmap_pages_range_noflush(unsigned long start, unsigned long end,
>> +pgprot_t prot, struct page **pages,
>> +unsigned int page_shift)
>> +{
>> +if (page_shi
Excerpts from Mathieu Desnoyers's message of July 17, 2020 11:42 pm:
> - On Jul 16, 2020, at 7:26 PM, Nicholas Piggin npig...@gmail.com wrote:
> [...]
>>
>> membarrier does replace barrier instructions on remote CPUs, which do
>> order accesses performed by the kernel on the user address space
On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria
wrote:
>
> So far Book3S Powerpc supported only one watchpoint. Power10 is
> introducing 2nd DAWR. Enable 2nd DAWR support for Power10.
> Availability of 2nd DAWR will depend on CPU_FTR_DAWR1.
>
> Signed-off-by: Ravi Bangoria
> ---
> arch/powerpc/inc
Hi Pratik,
On 7/10/20 10:52 AM, Pratik Rajesh Sampat wrote:
Additional registers DAWR0, DAWRX0 may be lost on Power 10 for
stop levels < 4.
p10 has one more pair DAWR1/DAWRX1. Please include that as well.
Ravi
Hi Nick,
On 7/13/20 11:22 AM, Nicholas Piggin wrote:
Excerpts from Pratik Rajesh Sampat's message of July 10, 2020 3:22 pm:
Additional registers DAWR0, DAWRX0 may be lost on Power 10 for
stop levels < 4.
Therefore save the values of these SPRs before entering a "stop"
state and restore their v
From: Nicholas Piggin
When '029ab30b4c0a ("powerpc/mm: Enable radix GTSE only if supported.")'
made GTSE an MMU feature, it was enabled by default in
powerpc-cpu-features but was missed in pa-features. This causes
random memory corruption during boot of PowerNV kernels where
CONFIG_PPC_DT_CPU_FTR
On Fri, Jul 17, 2020 at 02:48:00PM +0530, Pratik Rajesh Sampat wrote:
> Fire directed smp_call_function_single IPIs from a specified source
> CPU to the specified target CPU to reduce the noise we have to wade
> through in the trace log.
> The module is based on the idea written by Srivatsa Bhat an
On Mon, Jul 20, 2020 at 10:46 AM Finn Thain wrote:
>
> On Sun, 24 Nov 2019, Masahiro Yamada wrote:
>
> > Collect the ignored patterns to is_ignored_symbol().
> >
> > Signed-off-by: Masahiro Yamada
>
> This commit (887df76de67f5) caused a regression in my powerpc builds as it
> causes symbol names
Excerpts from Bharata B Rao's message of July 20, 2020 2:42 pm:
> From: Nicholas Piggin
>
> When '029ab30b4c0a ("powerpc/mm: Enable radix GTSE only if supported.")'
> made GTSE an MMU feature, it was enabled by default in
> powerpc-cpu-features but was missed in pa-features. This causes
> random
* Gautham R Shenoy [2020-07-17 13:56:53]:
> On Tue, Jul 14, 2020 at 10:06:23AM +0530, Srikar Dronamraju wrote:
> > Lookup the coregroup id from the associativity array.
> >
> > If unable to detect the coregroup id, fallback on the core id.
> > This way, ensure sched_domain degenerates and an ext
* Gautham R Shenoy [2020-07-07 16:41:34]:
> From: "Gautham R. Shenoy"
>
> Hi,
>
> On pseries Dedicated Linux LPARs, apart from the polling snooze idle
> state, we currently have the CEDE idle state which cedes the CPU to
> the hypervisor with latency-hint = 0.
>
> However, the PowerVM hypervi
Hi Pratik,
On Fri, Jul 17, 2020 at 02:48:01PM +0530, Pratik Rajesh Sampat wrote:
> This patch adds support to trace IPI based and timer based wakeup
> latency from idle states
>
> Latches onto the test-cpuidle_latency kernel module using the debugfs
> interface to send IPIs or schedule a timer b
* Gautham R Shenoy [2020-07-07 16:41:35]:
> From: "Gautham R. Shenoy"
>
> As per the PAPR, each H_CEDE call is associated with a latency-hint to
> be passed in the VPA field "cede_latency_hint". The CEDE states that
> we were implicitly entering so far is CEDE with latency-hint = 0.
>
> This p
* Gautham R Shenoy [2020-07-17 13:49:26]:
> On Tue, Jul 14, 2020 at 10:06:22AM +0530, Srikar Dronamraju wrote:
> > Add percpu coregroup maps and masks to create coregroup domain.
> > If a coregroup doesn't exist, the coregroup domain will be degenerated
> > in favour of SMT/CACHE domain.
> >
> >
"Aneesh Kumar K.V" writes:
> Move them to hash specific file and add BUG() for radix path.
> ---
> .../powerpc/include/asm/book3s/64/hash-pkey.h | 32
> arch/powerpc/include/asm/book3s/64/pkeys.h| 25 +
> arch/powerpc/include/asm/pkeys.h | 37
* Gautham R Shenoy [2020-07-07 16:41:36]:
> From: "Gautham R. Shenoy"
>
> Currently we use CEDE with latency-hint 0 as the only other idle state
> on a dedicated LPAR apart from the polling "snooze" state.
>
> The platform might support additional extended CEDE idle states, which
> can be disc
On 7/20/20 11:35 AM, Michael Ellerman wrote:
"Aneesh Kumar K.V" writes:
Move them to hash specific file and add BUG() for radix path.
---
.../powerpc/include/asm/book3s/64/hash-pkey.h | 32
arch/powerpc/include/asm/book3s/64/pkeys.h| 25 +
arch/powerpc/inclu
On Mon, Jul 20, 2020 at 03:38:29PM +1000, Nicholas Piggin wrote:
> Excerpts from Bharata B Rao's message of July 20, 2020 2:42 pm:
> > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
> > index 9cc49f265c86..a9594bad572a 100644
> > --- a/arch/powerpc/kernel/prom.c
> > +++ b/arch
* Gautham R Shenoy [2020-07-17 12:07:55]:
> On Tue, Jul 14, 2020 at 10:06:19AM +0530, Srikar Dronamraju wrote:
> > Currently "CACHE" domain happens to be the 2nd sched domain as per
> > powerpc_topology. This domain will collapse if cpumask of l2-cache is
> > same as SMT domain. However we could
On Sat, Jul 18, 2020 at 10:17:14AM -0700, Guenter Roeck wrote:
> On Wed, Jul 08, 2020 at 05:24:47PM +0200, Christoph Hellwig wrote:
> > Avoid the overhead of the dma ops support for tiny builds that only
> > use the direct mapping.
> >
> > Signed-off-by: Christoph Hellwig
>
> For ppc:pmac32_defc
* Gautham R Shenoy [2020-07-07 16:41:37]:
> From: "Gautham R. Shenoy"
>
> We are currently assuming that CEDE(0) has exit latency 10us, since
> there is no way for us to query from the platform. However, if the
> wakeup latency of an Extended CEDE state is smaller than 10us, then we
> can be s
* Gautham R Shenoy [2020-07-07 16:41:38]:
> From: "Gautham R. Shenoy"
>
> This patch exposes those extended CEDE states to the cpuidle framework
> which are responsive to external interrupts and do not need an H_PROD.
>
> Since as per the PAPR, all the extended CEDE states are non-responsive
>
* Gautham R Shenoy [2020-07-07 16:41:39]:
> From: "Gautham R. Shenoy"
>
> The Extended CEDE state with latency-hint = 1 is only different from
> normal CEDE (with latency-hint = 0) in that a CPU in Extended CEDE(1)
> does not wakeup on timer events. Both CEDE and Extended CEDE(1) map to
> the s
* Gautham R Shenoy [2020-07-17 11:30:11]:
> Hi Srikar,
>
> On Tue, Jul 14, 2020 at 10:06:18AM +0530, Srikar Dronamraju wrote:
> > Current code assumes that cpumask of cpus sharing a l2-cache mask will
> > always be a superset of cpu_sibling_mask.
> >
> > Lets stop that assumption.
> >
> > Cc:
On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria
wrote:
>
> Power10 has removed 512 bytes boundary from match criteria. i.e. The watch
> range can cross 512 bytes boundary.
It looks like this change is not mentioned in ISA v3.1 Book III 9.4
Data Address Watchpoint. It could be useful to mention that
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