Excerpts from christophe lombard's message of 2016-02-16 07:53:54 +1100:
+void cxl_guest_reload_module(struct cxl *adapter)
+{
+struct platform_device *pdev;
+int afu;
+
+for (afu = 0; afu < adapter->slices; afu++)
+cxl_guest_remove_afu(adapter->afu[afu]);
Should we possibly
se of this patch is to interact with the external driver
(where the AFU is shown) even if no action is required. A kernel thread
is needed to check every x seconds the current state of the AFU to see
if we need to enter an error recovery path.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/
On 19/04/2016 04:40, Andrew Donnellan wrote:
On 18/04/16 23:05, Christophe Lombard wrote:
In the POWERVM environement, the PHYP CoherentAccel component manages
environment
the state of the Coherant Accelerator Processor Interface adapter and
Coherent
virtualizes CAPI resources, handles
if we need to enter an error
recovery path.
Signed-off-by: Christophe Lombard
---
change from V1:
* Improved comments.
* Use a delayed queue work instead of our own kthread.
---
drivers/misc/cxl/cxl.h | 4 +++-
drivers/misc/cxl/guest.c | 57 +-
This moves the initialisation of the num_procs to before the SPA
allocation.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/native.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index b37f2e8..d2e75c8 100644
hanks
On 06/10/2015 08:19, Michael Ellerman wrote:
On Fri, 2015-10-02 at 16:01 +0200, Christophe Lombard wrote:
This moves the initialisation of the num_procs to before the SPA
allocation.
Why? What does it fix? I can't tell from the diff or the chan
lled).
The number of allocates pages depends on the max number of processes.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/native.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index b37f2e8..d2e75c8 100644
--- a/dr
@mpe since this patch introduces a new user API I'd appreciate it if you
could give this a bit extra scrutiny.
Excerpts from Frederic Barrat's message of 2016-02-07 00:29:01 +1100:
+Starts and controls flashing a new FPGA image. Partial
+reconfiguration is not supported (yet), so the ima
the pnv_ocxl_ API for the
bare-metal environment.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/Makefile| 2 +
drivers/misc/ocxl/config.c| 7 ++-
drivers/misc/ocxl/link.c | 31 +--
drivers/misc/ocxl/main.c | 5 ++
drivers/misc/ocxl
Fix up the pci config size of the OpenCAPI PCIe devices in the pseries
environment.
Most of OpenCAPI PCIe devices have 4096 bytes of configuration space.
Signed-off-by: Christophe Lombard
---
arch/powerpc/platforms/pseries/pci.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch
describe
their own definition. See struct ocxl_backend_ops.
It has been tested in a bare-metal and QEMU environment using the memcpy and
the AFP AFUs.
christophe lombard (3):
ocxl: Introduce implementation-specific API
ocxl: Add pseries-specific code
powerpc/pseries: Fixup config space size of
meters are common to all hcalls (buid and config_addr) that will
be used to allow QEMU to recover the PCI device.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/Makefile| 1 +
drivers/misc/ocxl/main.c | 4 +
drivers/misc/ocxl/ocxl_internal.h | 1 +
drivers/misc/ocxl
ch is common for each
devices sharing the same domain, same bus and same slot.
Signed-off-by: Christophe Lombard
---
arch/powerpc/platforms/powernv/ocxl.c | 164 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 19 ++-
arch/powerpc/platforms/powernv/pci.h | 13 ++
3
=0007:00:00.0,addr=2.0 -device
vfio-pci,multifunction=on,host=0007:00:00.1,addr=2.1
It has been tested in a bare-metal and QEMU environment using the memcpy
and the AFP AFUs.
christophe lombard (2):
powerpc/powernv: Register IOMMU group for OpenCAPI devices
vfio/pci: Introduce OpenCAPI devices s
value, requested to configure the process element in the
Scheduled Process Area, is not available in the QEMU environment.
This implies getting it from the host through the iommu group.
Signed-off-by: Christophe Lombard
---
drivers/vfio/pci/Kconfig | 7 +
drivers/vfio/pci/Makefile
On 22/10/2019 09:52, christophe lombard wrote:
pseries.c implements the guest-specific callbacks for the backend API.
The hypervisor calls provide an interface to configure and interact with
OpenCAPI devices. It matches the last version of the 'PAPR changes'
document.
The following
On 05/11/2019 06:01, Andrew Donnellan wrote:
On 22/10/19 6:52 pm, christophe lombard wrote:
Fix up the pci config size of the OpenCAPI PCIe devices in the pseries
environment.
Most of OpenCAPI PCIe devices have 4096 bytes of configuration space.
It's not "most of", it's
From: Christophe Lombard
The AFU Information DVSEC capability is a means to extract common,
general information about all of the AFUs associated with a Function
independent of the specific functionality that each AFU provides.
This patch fixes the access to the AFU Descriptor Data indexed by
Le 13/08/2018 à 11:48, Andrew Donnellan a écrit :
On 13/08/18 19:01, Christophe Lombard wrote:
From: Christophe Lombard
Your git committer email should probably match your sign-off email.
The AFU Information DVSEC capability is a means to extract common,
general information about all of
.
Fixes: 5ef3166e8a32 ("ocxl: Driver code for 'generic' opencapi devices")
Cc: stable # 4.16
Signed-off-by: Christophe Lombard
---
Changelog[v2]
- Rebase to latest upstream.
- Use pci_write_config_byte instead of pci_write_config_word
---
drivers/misc/ocxl/config.c | 4 +++
Le 14/08/2018 à 05:26, Michael Ellerman a écrit :
Hi Christophe,
The patch looks fine, just a nit about the change log:
Christophe Lombard writes:
The AFU Information DVSEC capability is a means to extract common,
general information about all of the AFUs associated with a Function
the access to the AFU Descriptor Data indexed by the
AFU Info Index field.
Fixes: 5ef3166e8a32 ("ocxl: Driver code for 'generic' opencapi devices")
Cc: stable # 4.16
Signed-off-by: Christophe Lombard
Acked-by: Frederic Barrat
Acked-by: Andrew Donnellan
---
Changelog[
tch sounds good. Thanks.
Reviewed-by: Christophe Lombard
On 25/01/2019 06:11, Vaibhav Jain wrote:
Recent updates to OPAL [1] have provided support for new CXL modes on
PHB that need to force a cold reset on the bridge (CRESET). However
PHB CRESET is a multi step process and cannot be completed
synchronously as expected by current kernel implementation
branch that
checks for not null AFU pointer in 'adapter->slices' [Fred]
* Removed a misleading comment in code.
---
Thanks
Acked-by: Christophe Lombard
metal environment using the memcpy and
the AFP AFUs.
christophe lombard (2):
powerpc/powernv: ocxl move SPA definition
powerpc/powernv: ocxl move TL definition
arch/powerpc/include/asm/pnv-ocxl.h | 30 +-
arch/powerpc/platforms/powernv/ocxl.c | 378 +++---
drivers/misc
create new few platform-specific calls which can be used by
drivers.
No functional change.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 25 +-
arch/powerpc/platforms/powernv/ocxl.c | 275 ++--
drivers/misc/ocxl/afu_irq.c | 1 -
drivers
: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 5 +-
arch/powerpc/platforms/powernv/ocxl.c | 103 --
drivers/misc/ocxl/config.c| 89 +-
3 files changed, 99 insertions(+), 98 deletions(-)
diff --git a/arch/powerpc/include/asm
On 11/10/2019 00:34, Andrew Donnellan wrote:
On 10/10/19 2:11 am, christophe lombard wrote:
This series moves the definition and the management of scheduled
process area
(SPA) and of the templates (Transaction Layer) for an ocxl card, using
the
OCAPI interface. The code is now located in the
On 11/10/2019 10:06, christophe lombard wrote:
On 11/10/2019 00:34, Andrew Donnellan wrote:
On 10/10/19 2:11 am, christophe lombard wrote:
This series moves the definition and the management of scheduled
process area
(SPA) and of the templates (Transaction Layer) for an ocxl card,
using the
On 14/10/2019 12:17, Frederic Barrat wrote:
diff --git a/arch/powerpc/platforms/powernv/ocxl.c
b/arch/powerpc/platforms/powernv/ocxl.c
index 8c65aacda9c8..4d26cba12b63 100644
--- a/arch/powerpc/platforms/powernv/ocxl.c
+++ b/arch/powerpc/platforms/powernv/ocxl.c
@@ -12,11 +12,54 @@
#define P
On 14/10/2019 12:21, Frederic Barrat wrote:
Le 09/10/2019 à 17:11, christophe lombard a écrit :
Specifies the templates in the Transaction Layer that the OpenCAPI
device/host
support when transmitting/receiving DL/DLX frames to or from the OpenCAPI
device/host.
Update, rename and create new
d the
entry in the SPA. (Fred)
christophe lombard (2):
powerpc/powernv: ocxl move SPA definition
powerpc/powernv: ocxl move TL definition
arch/powerpc/include/asm/pnv-ocxl.h | 46 +--
arch/powerpc/platforms/powernv/ocxl.c | 400 +++---
drivers/misc/ocxl/afu_
: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 6 +-
arch/powerpc/platforms/powernv/ocxl.c | 103 --
drivers/misc/ocxl/config.c| 89 +-
3 files changed, 99 insertions(+), 99 deletions(-)
diff --git a/arch/powerpc/include/asm
.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 46 ++--
arch/powerpc/platforms/powernv/ocxl.c | 297 +---
drivers/misc/ocxl/afu_irq.c | 1 -
drivers/misc/ocxl/link.c | 383 +++---
drivers/misc/ocxl
commands from the PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 2 +
arch/powerpc/platforms/powernv/ocxl.c | 19 +++
drivers/misc/ocxl/link.c
r the time being, the ATSD0 set of registers is used by default.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 3 ++
arch/powerpc/platforms/powernv/ocxl.c | 48 +++
2 files changed, 51 insertions(+)
diff --git a/arch/powerpc/include/asm/pnv
PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
Changelog[v2]
- Rebase to latest upstream.
- Create a set of smaller patches
- Move the device tree parsing and ioremap() for the
Reserved
6
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/context.c | 4 +++-
drivers/misc/ocxl/link.c | 4 +++-
drivers/misc/ocxl/ocxl_internal.h | 4 +++-
drivers/scsi/cxlflash/ocxl_hw.c | 6 --
include/misc/ocxl.h | 2
up to match the BDF/PASID of the AFU.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 58 +++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
index 20444db8a2bb..100bdfe9ec37
Add specific kernel traces which provide information on mmu notifier and on
pages range.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 4 +++
drivers/misc/ocxl/trace.h | 64 +++
2 files changed, 68 insertions(+)
diff --git a/drivers/misc
determine when the TLB Invalidate
has been completed.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 50
arch/powerpc/platforms/powernv/ocxl.c | 55 +++
2 files changed, 105 insertions(+)
diff --git a/arch
Reserved
6
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/context.c | 4 +++-
drivers/misc/ocxl/link.c | 4 +++-
drivers/misc/ocxl/ocxl_internal.h | 9 ++---
drivers/scsi/cxlflash/ocxl_hw.c | 6 --
include/misc/ocxl.h | 2
up to match the BDF/PASID of the AFU.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 62 +++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
index 77381dda2c45..129d4eddc4d2
determine when the TLB Invalidate
has been completed.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 51 +++
arch/powerpc/platforms/powernv/ocxl.c | 70 +++
2 files changed, 121 insertions(+)
diff --git a/arch/powerpc
PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
Changelog[v3]
- Rebase to latest upstream.
- Add page_size argument in pnv_ocxl_tlb_invalidate()
- Remove double pointer
Changelog[v2
r the time being, the ATSD0 set of registers is used by default.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 3 ++
arch/powerpc/platforms/powernv/ocxl.c | 45 +++
2 files changed, 48 insertions(+)
diff --git a/arch/powerpc/include/asm/pnv
Add specific kernel traces which provide information on mmu notifier and on
pages range.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 4 +++
drivers/misc/ocxl/trace.h | 64 +++
2 files changed, 68 insertions(+)
diff --git a/drivers/misc
Le 24/11/2020 à 14:45, Jason Gunthorpe a écrit :
On Tue, Nov 24, 2020 at 09:17:38AM +, Christoph Hellwig wrote:
@@ -470,6 +487,26 @@ void ocxl_link_release(struct pci_dev *dev, void
*link_handle)
}
EXPORT_SYMBOL_GPL(ocxl_link_release);
+static void invalidate_range(struct mmu_notif
PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
Changelog[v4]
- Rebase to latest upstream.
- Correct a typo in page size
Changelog[v3]
- Rebase to latest upstream.
- Add page_size
Reserved
6
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/context.c | 4 +++-
drivers/misc/ocxl/link.c | 4 +++-
drivers/misc/ocxl/ocxl_internal.h | 9 ++---
drivers/scsi/cxlflash/ocxl_hw.c | 6 --
include
r the time being, the ATSD0 set of registers is used by default.
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 3 ++
arch/powerpc/platforms/powernv/ocxl.c | 45 +++
2 files changed, 48 insertions(+)
diff --git a/ar
Add specific kernel traces which provide information on mmu notifier and on
pages range.
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 4 +++
drivers/misc/ocxl/trace.h | 64 +++
2 files changed, 68 insertions
determine when the TLB Invalidate
has been completed.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 51
arch/powerpc/platforms/powernv/ocxl.c | 69 +++
2 files changed, 120 insertions(+)
diff --git a/arch/powerpc
up to match the BDF/PASID of the AFU.
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 62 +++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
index
only.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/native.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 7ae7105..7257e8b 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -859,8 +859,6 @@ s
adapter and the afu.
- Traces.
Each environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxl.h | 34 ++-
drivers/misc/cxl/debugfs.c
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl/cxl.h | 35
nts from Andrew Donnellan and Frederic Barrat
Christophe Lombard (6):
cxl: Remove unused values in bare-metal environment.
cxl: Keep track of mm struct associated with a context
cxl: Update implementation service layer
cxl: Rename some psl8 specific functions
cxl: Isolate few psl8 speci
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard
---
drivers/mis
valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 13 +++
drivers/misc/cxl/cxl.h | 124
ll be released when the context is detached.
The reference (use count) on the struct mm is not kept to avoid a
circular dependency if the process mmaps its cxl mmio and forget to
unmap before exiting.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/api.c | 17 --
drivers/mis
Le 20/03/2017 à 17:26, Frederic Barrat a écrit :
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementati
Le 21/03/2017 à 03:47, Andrew Donnellan a écrit :
On 14/03/17 22:08, Christophe Lombard wrote:
The first 3 patches are mostly cleanup and fixes, separating the
psl8-specific code from the code which will also be used for psl9.
Patches 4 restructure existing code, to easily add the psl
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl/cxl.h | 35
cess and Thread Identification Register (CXL_PSL_PID_TID_An)
is only used when attaching a dedicated process for PSL8 only. This
register goes away in CAIA2.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxl.h| 13 +++--
drivers/misc/cxl/hcalls.c | 4 ++--
drivers/misc/cx
: Christophe Lombard
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 91f6459..e82a207 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1332,6 +1332,7 @@ static int cxl_read_vsec(struct cxl *adapter
ll be released when the context is detached.
A reference on mm_users is not kept to avoid a circular dependency if
the process mmaps its cxl mmio and forget to unmap before exiting.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/api.c | 17 +--
drivers/misc/cxl/context.c
ative_register_serr_irq().
- ASB_Notify messages and Non-Blocking queues not supported
on DD1.
- Change the allocation of the apc machines.
Changelog[v2]
- Rebase to latest upstream.
- Integrate comments from Andrew Donnellan and Frederic Barrat.
Christophe Lombard (7):
cxl: Rea
adapter and the afu.
- Traces.
Each environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxl.h | 40 ---
drivers/misc/cxl/debugfs.c
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard
---
drivers/mis
valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 16 ++-
drivers/misc/cxl/cxl.h | 137
Le 29/03/2017 à 02:21, Andrew Donnellan a écrit :
On 29/03/17 02:14, Christophe Lombard wrote:
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment. Thes
Le 30/03/2017 à 06:44, Andrew Donnellan a écrit :
On 29/03/17 02:14, Christophe Lombard wrote:
This series adds support for a cxl card which supports the Coherent
Accelerator Interface Architecture 2.0.
It requires IBM Power9 system and the Power Service Layer, version 9.
The PSL provides the
Le 03/04/2017 à 14:27, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment.
Le 03/04/2017 à 14:39, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL:
- Init implementation for the adapter and the afu.
- Invalidate TLB/SLB
Le 03/04/2017 à 15:05, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
ion of the apc machines.
Changelog[v2]
- Rebase to latest upstream.
- Integrate comments from Andrew Donnellan and Frederic Barrat.
Christophe Lombard (7):
cxl: Read vsec perst load image
cxl: Remove unused values in bare-metal environment.
cxl: Keep track of mm struct associated with a context
cxl
's no longer useful.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/api.c | 17 +--
drivers/misc/cxl/context.c | 21 +++--
drivers/misc/cxl/cxl.h | 10 --
drivers/misc/cxl/fault.c | 76 --
drivers/misc/cxl/file
-metal. The PSL Process and Thread Identification Register
(CXL_PSL_PID_TID_An) is only used when attaching a dedicated process
for PSL8 only. This register goes away in CAIA2.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxl.h| 20
drivers/misc/cxl/hcalls.c | 6
: Christophe Lombard
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index b27ea98..1f4c351 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1332,6 +1332,7 @@ static int cxl_read_vsec(struct cxl *adapter
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard
---
drivers/mis
valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard
---
Documentation/powerpc/cxl.txt | 11 +-
drivers/misc/cxl/context.c
adapter and the afu.
- Traces.
Each environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxl.h | 40 +++--
drivers/misc/cxl/debugfs.c
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl/cxl.h | 35
Le 12/04/2017 à 04:11, Michael Ellerman a écrit :
Frederic Barrat writes:
Le 07/04/2017 à 16:11, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
From: Christophe Lombard
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL on a POWER9 system.
The XSL (Translation Service Layer) is a stripped down version of the
PSL (Power Service Layer) used in some cards s
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards. These patches have been tested on Simulation environment and
quite a bit of them have been tested on real hardware.
This patch brings new fixes after a
Reviewed-by: christophe lombard
Le 06/06/2017 à 11:43, Frederic Barrat a écrit :
Fix error path if we can't copy user structure on CXL_IOCTL_START_WORK
ioctl. We shouldn't unlock the context status mutex as it was not
locked (yet).
Signed-off-by: Frederic Barrat
Cc: sta...@vger.
Le 09/06/2017 à 18:12, Frederic Barrat a écrit :
Salut Christophe,
It looks pretty good, but checkpatch complains about 1 or 2 items
worth fixing.
2 small remarks below.
Le 09/06/2017 à 12:09, Christophe Lombard a écrit :
A previous set of patches "cxl: Add support for Coh
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards. These patches have been tested on Simulation environment and
quite a bit of them have been tested on real hardware.
This patch brings new fixes after a
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 6 +++---
drivers/misc/cxl/cxl.h | 18 +-
drivers/misc/cxl/fault.c | 23 +++
drivers/misc/cxl/main.c| 17 +
drivers/misc/cxl/native.c | 29 +
d
-EFAULT in case of NULL pointer in cxllib_handle_fault().
- Reverse parameters when copro_handle_mm_fault() is called.
Signed-off-by: Christophe Lombard
---
This applies on top of this patch:
http://patchwork.ozlabs.org/patch/775322/
---
arch/powerpc/include/asm/opal-api.h | 1 +
drivers/m
Le 14/06/2017 à 07:01, Michael Ellerman a écrit :
Christophe Lombard writes:
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards.
Which commit is that?
cheers
Here are the commit
Le 15/06/2017 à 14:36, Frederic Barrat a écrit :
Salut Christophe,
A few comments below, nothing major...
Le 14/06/2017 à 15:29, Christophe Lombard a écrit :
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL o
he PSL, it implements the CAIA architecture, but has a number
of differences, mostly in it's implementation dependent registers.
The XSL also uses a special DMA cxl mode, which uses a slightly
different init sequence for the CAPP and PHB.
Signed-off-by: Christophe Lombard
---
Changelog[v
he PSL, it implements the CAIA architecture, but has a number
of differences, mostly in it's implementation dependent registers.
The XSL also uses a special DMA cxl mode, which uses a slightly
different init sequence for the CAPP and PHB.
Signed-off-by: Christophe Lombard
---
Changelog[v
Le 22/06/2017 à 13:20, Michael Ellerman a écrit :
Christophe Lombard writes:
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL on a POWER9 system.
The XSL (Translation Service Layer) is a stripped down version
he PSL, it implements the CAIA architecture, but has a number
of differences, mostly in it's implementation dependent registers.
The XSL also uses a special DMA cxl mode, which uses a slightly
different init sequence for the CAPP and PHB.
Signed-off-by: Andrew Donnellan
Signed-off-by: Chr
From: Christophe Lombard
The function is_page_fault(), for POWER9, lists the Translation Checkout
Responses where the page fault will be handled by copro_handle_mm_fault().
This list is too restrictive and not necessary.
This patches removes this restriction and all page faults, whatever the
1 - 100 of 165 matches
Mail list logo
