In message <20030403145906.GA3867 at ip68-0-152-218.tc.ph.cox.net> you wrote:
>
> > It might have been me. We had problems on the first prototypes of
> > TQM8260 boards; the board configuration with L2 cache would only work
> > with DC turned off. The problem disappeared with later silicon, s
On Wed, Apr 02, 2003 at 10:19:09PM +0200, Wolfgang Denk wrote:
>
> In message <20030402194622.GA30107 at ip68-0-152-218.tc.ph.cox.net> you wrote:
> >
> > > It was orginally done for 8xx processors. I suspect someone (I don't
> > > think it was me) :-) tried to consolidate 8xx and 82xx CPM configu
In message <20030402194622.GA30107 at ip68-0-152-218.tc.ph.cox.net> you wrote:
>
> > It was orginally done for 8xx processors. I suspect someone (I don't
> > think it was me) :-) tried to consolidate 8xx and 82xx CPM configurations
> > and messed it up.
>
> My guess and recollection is that the 8
Tom Rini wrote:
> My guess and recollection is that the 8260 version of this was to
> disable the DCACHE in a certain manner, because of buggy silicon on a
> specific board. Someone unmerged this bit of code later I think.
HmmOK. FYI, on any processor core except 8xx you can't disable
the
Matt Porter wrote:
> On Wed, Apr 02, 2003 at 09:28:21AM -0500, Jean-Denis Boyer wrote:
>
>>There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
>>In the kernel configuration UI, look into the section 'MPC8260 CPM Options'.
>
>
> There is no code backing that option in linuxppc_
On Wed, Apr 02, 2003 at 02:23:01PM -0500, Dan Malek wrote:
>
> Matt Porter wrote:
>
> >On Wed, Apr 02, 2003 at 09:28:21AM -0500, Jean-Denis Boyer wrote:
> >
> >>There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
> >>In the kernel configuration UI, look into the section 'MPC826
Yes, I gave it a breif test and it did not work and I did not have time to
debug it.
Chip
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
On Wed, Apr 02, 2003 at 09:28:21AM -0500, Jean-Denis Boyer wrote:
>
> There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
> In the kernel configuration UI, look into the section 'MPC8260 CPM Options'.
There is no code backing that option in linuxppc_2_4_devel, it is useless.
C
There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
In the kernel configuration UI, look into the section 'MPC8260 CPM Options'.
Regards,
Jean-Denis Boyer, B.Eng., Technical Leader
Mediatrix Telecom Inc.
4229 Garlock Street
Sher
On Tue, Apr 01, 2003 at 05:34:34PM -0800, kas turi wrote:
>
> Hi
> We have a custom made board and we are running 8250
> processor. We are using DMA to transmit and receive
> data between peripheral and memory. The data is
> getting corrupted while transmitting and receiving. We
> are suspecting
Hi
We have a custom made board and we are running 8250
processor. We are using DMA to transmit and receive
data between peripheral and memory. The data is
getting corrupted while transmitting and receiving. We
are suspecting it might be due to data cache being
enabled. So I disabled data cache i
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