Hi Richard,
Unfortunately the fixed configuration doesn't work in mixed networks, as I
already said.
An AES67 network with Dante and some other AES67 manufacturer equipment
(Ravenna, Archwave or other) is a very common use case. AES67 is all about
interoperability of different vendors and Dante
Dear Mr. Cochran,
I've finally got back to my plan (ext.PPS to 2-4 i210 chips for
tcpdump timestamping) and I'm reviewing your proggie.
Yes the code is pretty self-explanatory :-) and packed with gems.
If I understand correctly, setting up the SDP0 GPIO for external
PPS input (which takes two
Dear everyone (maybe Mr. Cochran especially),
my setup with external PPS has started showing basic signs of life.
Interestingly, my two i210 cards seem to be throwing an event on both
PPS edges, rising and falling :-) They're spaced 200 ms apart.
And, somehow the system converges to the "wrong"
Ohh... excellent, that answers a question from my next message :-)
In fact I don't mind if I see the falling edges as well - only I
should detect them somehow, by timing calculation if there's no other
way, and ignore them in the servo policing loop.
As my application is tcpdump timestamping
On Tue, Feb 13, 2018 at 10:50:23AM +0100, brain wrote:
> Dante sends ts=8 and other manufacturers send ts=0. Unless Linuxptp
> properly implements the ts handling (i.e. ignoring bits 1-3) it
> cannot work in such networks. Simply because fix-configuring to one
> value (Dante or non-Dante) filters
On Tue, Feb 13, 2018 at 07:01:22PM +0100, Oliver Westermann wrote:
> The issue is that the PHY only has two slots for timestamps, one for
> outgoing packages and one for incoming packages. If the device in question
> is a ptp master and has multiple slave, it sometimes happen that both
> DELAY_REQ
On Tue, Feb 13, 2018 at 07:01:22PM +0100, Oliver Westermann wrote:
> Is there a reason not to do this or a better idea to use linuxptp on
> systems with similar hardware constraints?
I have had such HW, and I usually just set "fault_reset_interval ASAP"
in the configuration.
> Are there design
I've a setup of multiple devices with a ARM CPU using a Marvell PHY with
hardware timestamping capabilitys for networking.
These Marvell PHYs analyse incoming and outgoing packages for PTP packages,
saves a hardware timestamp and issues a interrupt.
The PHY driver catches the interrupt, gets the
Hi Richard,
On 13/02/18 17:27, Richard Cochran wrote:
On Tue, Feb 13, 2018 at 10:50:23AM +0100, brain wrote:
Dante sends ts=8 and other manufacturers send ts=0. Unless Linuxptp
properly implements the ts handling (i.e. ignoring bits 1-3) it
cannot work in such networks. Simply because
Just for the record:
On 13 Feb 2018 at 8:05, Richard Cochran wrote:
>
> The reason for this is that that the i210 latches the time on both
> rising and falling edges of the input signal. You can't program it
> for rising edge only, for example.
>
I've checked the datasheet again and you're
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