On Thu, May 19, 2022 at 10:57:06AM +0530, Devasish Dey wrote:
> We are in the process of making the changes in small multiple patches so
> that they can be easily acceptable by the community.
I suggest starting with the easy stuff:
4. Delay mechanism
As per IEEE1588-2019, Table 21 adding
Hi Petr,
Seems it was misinterpreted, it was just a suggestion from our end if the
patch can be taken as a full for G.8275.2 functionality.
We are in the process of making the changes in small multiple patches so
that they can be easily acceptable by the community.
Thanks,
Devasish
On Wed, 18 May
On Wed, May 18, 2022 at 11:27:08AM +0530, Devasish Dey wrote:
> That's why we have added, "> + * @note Copyright (C) 2022 SyncMonk
> Technologies " in all the files modified by SyncMonk
> Technologies. And we recommend that this practice should be adopted by
> community members.
Good luck with
On Wed, May 18, 2022 at 11:27:08AM +0530, Devasish Dey wrote:
> 1. We have invested time in development and have been verified by the team
> as a complete solution which is addressing the requirements of G.8275.2
> Breaking the changes into small patches may lead to intermediate
> functionality
Hi Richard,
Thanks for your response. We have reviewed the patch again as per your
suggestion.
1. We have invested time in development and have been verified by the team
as a complete solution which is addressing the requirements of G.8275.2
Breaking the changes into small patches may lead to
On Mon, May 16, 2022 at 02:08:06PM +0530, SyncMonk Technologies wrote:
> From: SyncMonk
>
> 1. Inclusion of virtual PTP port on a PTP clock. (G.8275 Annex B)
> 2. Alternate master support (G.8275.2 Section 6.9 and G.8275.2 Appendix III)
> 3. TLV support for interface rate (G.8275.2 Annex D)
>
