In case of Linux and Android we are using the qRegisterInfo packet and
lldb-server fills it in based on the register definitions inside LLDB so
for those targets it would be important to have all of the alias registers
available.
I don't have an AArch64-BE target at hand but I am pretty sure you
But if I attach to an arm64 core file, where lldb is using it's own register
definitions, then lldb has no idea what s0 is.
My concern about defining these subset registers in RegisterInfos_arm64.h is
that the offsets are in a target-endian register context buffer. My example
below was
Yeah, it's incorrectly grabbing the stack pointer reg number (31) from the Rn
bits and using that as the register # being saved, instead of the Rt and Rt2
register numbers, and saying that v31 is being pushed twice. It's an easy bug
in EmulateInstructionARM64::EmulateLDPSTP but fixing that
Hi Tamas, sorry for that last email being a mess, I was doing something else
while writing it and only saw how unclear it was after I sent it. You
understood everything I was trying to say.
I looked at the AAPCS64 again. It says v8-v15 are callee saved, but says,
"Additionally, only the
Hi Jason,
Thank you for adding unit test for this code. I think the current
implementation doesn't fail terribly on 16 vs 32 byte stack alignment
because we use the "opc" from the instruction to calculate the write back
address (to adjust the SP) so having the wrong size of the register won't
