[llvm-branch-commits] [clang] [llvm] [mlir] [OpenMPIRBuilder] Introduce OMPRegionInfo managing the stack of OpenMP region constructs. (PR #130135)

https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/130135 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

@@ -0,0 +1,263 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+dynamic-vgpr < %s | FileCheck -check-prefix=CHECK %s + +; Make sure we use a stack pointer and allo

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

@@ -455,6 +455,10 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction, unsigned NumSpilledSGPRs = 0; unsigned NumSpilledVGPRs = 0; + // The size of the scratch space reserved for the CWSR trap handler to spill + // some of the dynamic VGPRs. + unsigned

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

@@ -0,0 +1,263 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+dynamic-vgpr < %s | FileCheck -check-prefix=CHECK %s + +; Make sure we use a stack pointer and allo

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

@@ -691,17 +691,61 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, } assert(ScratchWaveOffsetReg || !PreloadedScratchWaveOffsetReg); - if (hasFP(MF)) { + unsigned Offset = FrameInfo.getStackSize() * getScratchScaleFactor(ST); + if (!mayReserveSc

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

@@ -552,6 +552,7 @@ enum Id { // HwRegCode, (6) [5:0] enum Offset : unsigned { // Offset, (5) [10:6] OFFSET_MEM_VIOL = 8, + OFFSET_ME_ID = 8, perlfu wrote: It's slightly confusing that this enumeration of offsets applies to multiple registers. Perhaps com

[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix hvx-isel for extract_subvector op (#129672) (PR #130215)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/130215 Backport 29d3fc3f11d272a72ac255af9277c740f26c3dfc Requested by: @androm3da >From 3c9189006713fbabe08a02e1d8fee0d79d7647a2 Mon Sep 17 00:00:00 2001 From: aankit-ca Date: Thu, 6 Mar 2025 15:02:10 -0800 Subject:

[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix hvx-isel for extract_subvector op (#129672) (PR #130215)

https://github.com/iajbar approved this pull request. https://github.com/llvm/llvm-project/pull/130215 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix hvx-isel for extract_subvector op (#129672) (PR #130215)

llvmbot wrote: @iajbar What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/130215 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listin

[llvm-branch-commits] [llvm] [AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR mode (PR #130037)

https://github.com/rovka updated https://github.com/llvm/llvm-project/pull/130037 >From c29d8202c06488a9466aea49dda4cf2b4663236e Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Mon, 23 Oct 2023 11:46:19 +0200 Subject: [PATCH 1/2] [AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR mode

[llvm-branch-commits] [flang] [flang][OpenMP] Accept old FLUSH syntax in METADIRECTIVE (PR #130122)

https://github.com/kparzysz updated https://github.com/llvm/llvm-project/pull/130122 >From bf56b8c80a0f1a7e06dcd3e898172c27e5afabf5 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 5 Mar 2025 08:24:30 -0600 Subject: [PATCH 1/3] [flang][OpenMP] Accept old FLUSH syntax in METADIRECTI

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for bitcast (PR #130086)

arsenm wrote: ### Merge activity * **Mar 6, 7:26 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/130086). https://github.com/llvm/llvm-project/pull/130086 __

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for insert_subreg (PR #130085)

arsenm wrote: ### Merge activity * **Mar 6, 7:26 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/130085). https://github.com/llvm/llvm-project/pull/130085 __

[llvm-branch-commits] [llvm] [AMDGPU] Add SubtargetFeature for dynamic VGPR mode (PR #130030)

@@ -1239,6 +1239,12 @@ def FeatureXF32Insts : SubtargetFeature<"xf32-insts", "v_mfma_f32_16x16x8_xf32 and v_mfma_f32_32x32x4_xf32" >; +def FeatureDynamicVGPR : SubtargetFeature <"dynamic-vgpr", shiltian wrote: Where is this target feature enabled? https:

[llvm-branch-commits] [llvm] [DirectX] Updating DXContainer documentation to add Root Descriptors (PR #129759)

https://github.com/joaosaffran edited https://github.com/llvm/llvm-project/pull/129759 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Port SIInsertWaitcnts to NPM (PR #130061)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130061 None >From 10605a79e1d1c6d1c227b98019fd4a4c568345b8 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 04:41:08 + Subject: [PATCH] [AMDGPU][NPM] Port SIInsertWaitcnts to NPM --- llvm/lib/Ta

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for bitcast (PR #130086)

https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/130086 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Implement bitcode autoupgrade for old style enqueue blocks (PR #128520)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/128520 >From d2479a3b4f3613a01fb62658b6fd67d28561fd55 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 17 Nov 2023 14:21:52 +0900 Subject: [PATCH] AMDGPU: Implement bitcode autoupgrade for old style enqueue blo

[llvm-branch-commits] [flang] [flang][OpenMP] Accept old FLUSH syntax in METADIRECTIVE (PR #130122)

https://github.com/kparzysz updated https://github.com/llvm/llvm-project/pull/130122 >From bf56b8c80a0f1a7e06dcd3e898172c27e5afabf5 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 5 Mar 2025 08:24:30 -0600 Subject: [PATCH 1/2] [flang][OpenMP] Accept old FLUSH syntax in METADIRECTI

[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse cancel-directive-name as clause (PR #130146)

https://github.com/kiranchandramohan approved this pull request. LG. https://github.com/llvm/llvm-project/pull/130146 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse cancel-directive-name as clause (PR #130146)

https://github.com/kparzysz updated https://github.com/llvm/llvm-project/pull/130146 >From 98df18461bb06afa06b8968b157a3c5a5cf50324 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 6 Mar 2025 08:51:34 -0600 Subject: [PATCH 1/2] [flang][OpenMP] Parse cancel-directive-name as clause

[llvm-branch-commits] [llvm] [DirectX] Updating Root Signature documentation with Descriptor table description (PR #129797)

https://github.com/joaosaffran updated https://github.com/llvm/llvm-project/pull/129797 >From 82a7de3b1a22eb7f7630d5b2d6998916ede45a8c Mon Sep 17 00:00:00 2001 From: joaosaffran <126493771+joaosaff...@users.noreply.github.com> Date: Tue, 4 Mar 2025 14:32:03 -0800 Subject: [PATCH 1/2] Updating Ro

[llvm-branch-commits] [clang] [CUDA][HIP] fix virtual dtor host/device attr (PR #130126)

https://github.com/yxsamliu edited https://github.com/llvm/llvm-project/pull/130126 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Implement bitcode autoupgrade for old style enqueue blocks (PR #128520)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/128520 >From d2479a3b4f3613a01fb62658b6fd67d28561fd55 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 17 Nov 2023 14:21:52 +0900 Subject: [PATCH] AMDGPU: Implement bitcode autoupgrade for old style enqueue blo

[llvm-branch-commits] [flang] [flang][OpenMP] Map simple `do concurrent` loops to OpenMP host constructs (PR #127633)

ergawy wrote: Ping! Please have a look when you have time. https://github.com/llvm/llvm-project/pull/127633 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR mode (PR #130037)

@@ -0,0 +1,356 @@ +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -run-pass=si-insert-waitcnts -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=CHECK,DEFAULT +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -mattr=+dynamic-vgpr -run-pass=si-insert-waitcnts -verify-machineinst

[llvm-branch-commits] [llvm] [AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (PR #130047)

https://github.com/kerbowa commented: Is there any test for the revert scheduling portion of the change? https://github.com/llvm/llvm-project/pull/130047 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi

[llvm-branch-commits] [llvm] [AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (PR #130047)

@@ -1452,6 +1452,16 @@ bool GCNSchedStage::shouldRevertScheduling(unsigned WavesAfter) { if (WavesAfter < DAG.MinOccupancy) return true; + // For dynamic VGPR mode, we don't want to waste any VGPR blocks. + if (ST.isDynamicVGPREnabled()) { kerbowa wro

[llvm-branch-commits] [llvm] [AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (PR #130047)

https://github.com/kerbowa edited https://github.com/llvm/llvm-project/pull/130047 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 76911bf - Revert "Revert "[LTO][Pipelines][Coro] De-duplicate Coro passes" (#129977)"

Author: Vitaly Buka Date: 2025-03-06T07:57:35-08:00 New Revision: 76911bfffd150a5c5ef0f8ec54ba526ffc09cafb URL: https://github.com/llvm/llvm-project/commit/76911bfffd150a5c5ef0f8ec54ba526ffc09cafb DIFF: https://github.com/llvm/llvm-project/commit/76911bfffd150a5c5ef0f8ec54ba526ffc09cafb.diff L

[llvm-branch-commits] [mlir] 1d72977 - Revert "[mlir][ODS] Add a generated builder that takes the Properties struct …"

Author: Benjamin Chetioui Date: 2025-03-06T16:26:44+01:00 New Revision: 1d72977e0198033e8ae7f7317abec09d59b330de URL: https://github.com/llvm/llvm-project/commit/1d72977e0198033e8ae7f7317abec09d59b330de DIFF: https://github.com/llvm/llvm-project/commit/1d72977e0198033e8ae7f7317abec09d59b330de.d

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Update divergence lowering tests (PR #128702)

https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/128702 >From c844e3ac372ec27d57c6d5aad3567426a460936f Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Fri, 28 Feb 2025 15:54:55 +0100 Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests I

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Update divergence lowering tests (PR #128702)

https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/128702 >From c844e3ac372ec27d57c6d5aad3567426a460936f Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Fri, 28 Feb 2025 15:54:55 +0100 Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests I

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (PR #124298)

https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/124298 >From f084882197a92f537c38ec19dfabdafdd9f15d09 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Fri, 28 Feb 2025 15:56:04 +0100 Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Port SIPreEmitPeephole to NPM (PR #130065)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130065?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Port SIInsertHardClauses to NPM (PR #130062)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130062 None >From 88d2174897b3a23ea0a7d8b1e915eb99c0992696 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 04:52:38 + Subject: [PATCH] [AMDGPU][NPM] Port SIInsertHardClauses to NPM --- llvm/lib

[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)

@@ -112,21 +117,52 @@ bool StaticDataSplitter::runOnMachineFunction(MachineFunction &MF) { return Changed; } +const Constant * +StaticDataSplitter::getConstant(const MachineOperand &Op, +const TargetMachine &TM, +

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for bitcast (PR #130086)

llvmbot wrote: @llvm/pr-subscribers-backend-x86 Author: Matt Arsenault (arsenm) Changes Subregister defs are illegal in SSA. Surprisingly this enables folding into subregister insert patterns in one test. --- Full diff: https://github.com/llvm/llvm-project/pull/130086.diff 2 Files Affec

[llvm-branch-commits] [llvm] [AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (PR #130047)

https://github.com/rovka edited https://github.com/llvm/llvm-project/pull/130047 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)

@@ -148,17 +184,9 @@ bool StaticDataSplitter::partitionStaticDataWithProfiles(MachineFunction &MF) { if (MJTI->updateJumpTableEntryHotness(JTI, Hotness)) ++NumChangedJumpTables; -} else { - // Find global variables with local linkage. -

[llvm-branch-commits] [llvm] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (PR #130094)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Diana Picus (rovka) Changes The llvm.amdgcn.cs.chain intrinsic has a 'flags' operand which may indicate that we want to reallocate the VGPRs before performing the call. A call with the following arguments: ``` llvm.amdgcn.cs.chai

[llvm-branch-commits] [llvm] [BOLT] Skip out-of-range pending relocations (PR #116964)

paschalis-mpeis wrote: Hey Maksim, Extending Relocations is even better. Thanks for the suggestion and the review. Before proceeding, and regarding the size overheads, I want to highlight an inconsistency with LLVM’s ObjectFile, where the type is 64 bits ([see here](https://github.com/llvm/ll

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for insert_subreg (PR #130085)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/130085 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for bitcast (PR #130086)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/130086 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for bitcast (PR #130086)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130086?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for insert_subreg (PR #130085)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130085?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for bitcast (PR #130086)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/130086 Subregister defs are illegal in SSA. Surprisingly this enables folding into subregister insert patterns in one test. >From c7d08110c29c0c37c198fa02b953767eaf68a3be Mon Sep 17 00:00:00 2001 From: Matt Arsenault D

[llvm-branch-commits] [llvm] [AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR mode (PR #130037)

@@ -0,0 +1,356 @@ +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -run-pass=si-insert-waitcnts -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=CHECK,DEFAULT +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -mattr=+dynamic-vgpr -run-pass=si-insert-waitcnts -verify-machineinst

[llvm-branch-commits] [llvm] [AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR mode (PR #130037)

@@ -0,0 +1,356 @@ +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -run-pass=si-insert-waitcnts -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=CHECK,DEFAULT +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -mattr=+dynamic-vgpr -run-pass=si-insert-waitcnts -verify-machineinst

[llvm-branch-commits] [llvm] [AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR mode (PR #130037)

@@ -0,0 +1,356 @@ +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -run-pass=si-insert-waitcnts -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=CHECK,DEFAULT +# RUN: llc -O2 -march=amdgcn -mcpu=gfx1200 -mattr=+dynamic-vgpr -run-pass=si-insert-waitcnts -verify-machineinst

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def (PR #130071)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/130071 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def (PR #130071)

https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/130071 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port BranchRelaxation to NPM (PR #130067)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130067?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port StackFrameLayoutAnalysisPass to NPM (PR #130070)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130070?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port PostRAHazardRecognizer to NPM (PR #130066)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130066?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def (PR #130071)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130071?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port MachineSanitizerBinaryMetadata to NPM (PR #130069)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130069?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Port GCNCreateVOPD to NPM (PR #130059)

optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/130059?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port StackFrameLayoutAnalysisPass to NPM (PR #130070)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130070 None >From 578b467fb9a8338e84833f6596768b8048bbd531 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 10:45:25 + Subject: [PATCH] [CodeGen][NPM] Port StackFrameLayoutAnalysisPass to NPM ---

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Port SILateBranchLowering to NPM (PR #130063)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130063 None >From 5f050b8e6b439c534cbbfe36305560b7fa2c5cfa Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 05:26:49 + Subject: [PATCH] [AMDGPU][NPM] Port SILateBranchLowering to NPM --- llvm/li

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM (PR #130068)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130068 None >From e9865932db7cff474a1df1d71f9a01b2d6bec47f Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 09:30:37 + Subject: [PATCH] [CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM --- ...

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port MachineSanitizerBinaryMetadata to NPM (PR #130069)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130069 None >From 003ff875ebf977ef373e8d039a31a5cbb3f8c853 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 10:20:36 + Subject: [PATCH] [CodeGen][NPM] Port MachineSanitizerBinaryMetadata to NPM -

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def (PR #130071)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130071 None >From 462a05548fb65f3f8cf1310edd064ee1483c1c43 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 10:56:28 + Subject: [PATCH] [AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def --- llvm/lib/

[llvm-branch-commits] [llvm] [CodeGen][NPM] Port PostRAHazardRecognizer to NPM (PR #130066)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130066 None >From 0a495b860dfd609179c655c87c2146c6aba3c7f1 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Thu, 6 Mar 2025 06:42:54 + Subject: [PATCH] [CodeGen][NPM] Port PostRAHazardRecognizer to NPM --- .../

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Port GCNCreateVOPD to NPM (PR #130059)

https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/130059 None >From d82b6dd57dcae61ba7790c7681dc5ae3a5d7fbbd Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Wed, 5 Mar 2025 10:52:00 + Subject: [PATCH] [AMDGPU][NPM] Port GCNCreateVOPD to NPM --- llvm/lib/Targe

[llvm-branch-commits] [llvm] [AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (PR #130047)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Diana Picus (rovka) Changes In dynamic VGPR mode, we can allocate up to 8 blocks of either 16 or 32 VGPRs (based on a chip-wide setting which we can model with a Subtarget feature). Update some of the subtarget helpers to reflect

[llvm-branch-commits] [llvm] [AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (PR #130047)

https://github.com/rovka created https://github.com/llvm/llvm-project/pull/130047 In dynamic VGPR mode, we can allocate up to 8 blocks of either 16 or 32 VGPRs (based on a chip-wide setting which we can model with a Subtarget feature). Update some of the subtarget helpers to reflect this. In

[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

llvmbot wrote: @llvm/pr-subscribers-llvm-ir Author: Mariusz Sikora (mariusz-sikora-at-amd) Changes --- Patch is 23.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130041.diff 12 Files Affected: - (modified) llvm/include/llvm/IR/Intrinsic

[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Mariusz Sikora (mariusz-sikora-at-amd) Changes --- Patch is 23.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130041.diff 12 Files Affected: - (modified) llvm/include/llvm/IR/In

[llvm-branch-commits] [llvm] release/20.x: [AArch64] Fix SVE scalar fcopysign lowering without neon. (#129787) (PR #129997)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/129997 Backport 4c2d1b4c53de d4ab3df320f9 Requested by: @davemgreen >From e9619c1c70840718b0a59901d2da788b176597ee Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 4 Mar 2025 21:46:55 + Subject: [PATCH 1/2]

[llvm-branch-commits] [llvm] [AMDGPU] Add SubtargetFeature for dynamic VGPR mode (PR #130030)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Diana Picus (rovka) Changes This represents a hardware mode supported only for wave32 compute shaders. When enabled, we set the `.dynamic_vgpr_en` field of `.compute_registers` to true in the PAL metadata. --- Full diff: https:/

[llvm-branch-commits] [llvm] [AMDGPU] Add SubtargetFeature for dynamic VGPR mode (PR #130030)

https://github.com/rovka created https://github.com/llvm/llvm-project/pull/130030 This represents a hardware mode supported only for wave32 compute shaders. When enabled, we set the `.dynamic_vgpr_en` field of `.compute_registers` to true in the PAL metadata. >From b2a7bdc3954d2bf72e99d730ce0

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Relax the restrictions of inlineasm operand modifier 'u' and 'w' (#129864) (PR #130009)

https://github.com/heiher approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/130009 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libclc] release/20.x: [libclc] Stop installing CLC headers (#126908) (PR #130017)

arsenm wrote: Given the release is already out, I don't think it makes sense to pull this from the install in the release branch https://github.com/llvm/llvm-project/pull/130017 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [libclc] release/20.x: [libclc] Stop installing CLC headers (#126908) (PR #130017)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/130017 Backport a2b05761724e5243056988d9d6bf1a5a94715b74 Requested by: @frasercrmck >From 11b893892cd56d43420bde2d4de9038479cf Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Thu, 6 Mar 2025 08:52:23 + Su

[llvm-branch-commits] [libclc] release/20.x: [libclc] Stop installing CLC headers (#126908) (PR #130017)

llvmbot wrote: @arsenm What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/130017 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listin

[llvm-branch-commits] [libclc] release/20.x: [libclc] Stop installing CLC headers (#126908) (PR #130017)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/130017 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Relax the restrictions of inlineasm operand modifier 'u' and 'w' (#129864) (PR #130009)

llvmbot wrote: @llvm/pr-subscribers-backend-loongarch Author: None (llvmbot) Changes Backport bae6644e1227b2555f92b1962dac6c2444eaaaf2 Requested by: @SixWeining --- Full diff: https://github.com/llvm/llvm-project/pull/130009.diff 3 Files Affected: - (modified) llvm/docs/LangRef.rst (+

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Relax the restrictions of inlineasm operand modifier 'u' and 'w' (#129864) (PR #130009)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/130009 Backport bae6644e1227b2555f92b1962dac6c2444eaaaf2 Requested by: @SixWeining >From 82c916a7f9fa7110cb38da56fdeb5aeb2edad8ab Mon Sep 17 00:00:00 2001 From: Lu Weining Date: Thu, 6 Mar 2025 16:17:12 +0800 Subject

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Relax the restrictions of inlineasm operand modifier 'u' and 'w' (#129864) (PR #130009)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/130009 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits