[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-11 Thread Sergey Kachkov via llvm-branch-commits
@@ -8430,6 +8479,46 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes( // bring the VPlan to its final state. // --- + // Adjust the recipes for any monotonic phis. + for (VPRecipe

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-11 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc edited https://github.com/llvm/llvm-project/pull/140723 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-11 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc edited https://github.com/llvm/llvm-project/pull/140723 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [VPlan] Implement compressed widening of memory instructions (PR #166956)

2025-11-10 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc edited https://github.com/llvm/llvm-project/pull/166956 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [VPlan] Implement compressed widening of memory instructions (PR #166956)

2025-11-10 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc updated https://github.com/llvm/llvm-project/pull/166956 >From 92342e03b192d37370c9160b13ce1048501eb079 Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date: Fri, 7 Nov 2025 18:09:56 +0300 Subject: [PATCH] [VPlan] Implement compressed widening of memory instructions

[llvm-branch-commits] [llvm] [LoopVectorize][NFC] Refactor widening decision logic (PR #140722)

2025-11-10 Thread Sergey Kachkov via llvm-branch-commits
skachkov-sc wrote: @david-arm addressed, but I've left memoryInstructionCanBeWidened as a separate function for now (it contains some early exits so I think the code will be harder to read after its substitution) https://github.com/llvm/llvm-project/pull/140722

[llvm-branch-commits] [llvm] [LoopVectorize][NFC] Refactor widening decision logic (PR #140722)

2025-11-10 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc edited https://github.com/llvm/llvm-project/pull/140722 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoopVectorize][NFC] Refactor widening decision logic (PR #140722)

2025-11-10 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc updated https://github.com/llvm/llvm-project/pull/140722 >From b08f1f89c1e8b8dd2acb0662fa1da021f27d9ab9 Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date: Mon, 10 Nov 2025 16:35:23 +0300 Subject: [PATCH 1/2] [IVDescriptors] Add unit tests for MonotonicDescriptor

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
@@ -3193,6 +3239,9 @@ class LLVM_ABI_FOR_TEST VPWidenMemoryRecipe : public VPRecipeBase, /// Whether the consecutive accessed addresses are in reverse order. bool Reverse; + /// Whether the consecutive accessed addresses are compressed with mask value. + bool Compresse

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc edited https://github.com/llvm/llvm-project/pull/140723 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc updated https://github.com/llvm/llvm-project/pull/140723 >From 9697cd806947ab6ebd021cb7919acd62cc2e29a0 Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date: Fri, 7 Nov 2025 18:09:56 +0300 Subject: [PATCH 1/3] [VPlan] Implement compressed widening of memory instruc

[llvm-branch-commits] [llvm] [VPlan] Implement compressed widening of memory instructions (PR #166956)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc created https://github.com/llvm/llvm-project/pull/166956 RFC link: https://discourse.llvm.org/t/rfc-loop-vectorization-of-compress-store-expand-load-patterns/86442 >From 9697cd806947ab6ebd021cb7919acd62cc2e29a0 Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date:

[llvm-branch-commits] [llvm] [LoopVectorize][NFC] Refactor widening decision logic (PR #140722)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc updated https://github.com/llvm/llvm-project/pull/140722 >From 3bb26adeaf0ddd4b826aac751fdbb70d00da3089 Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date: Wed, 22 Nov 2023 17:24:08 +0300 Subject: [PATCH] [LoopVectorize][NFC] Refactor widening decision logic ---

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
@@ -4442,6 +4495,29 @@ void VPReductionPHIRecipe::print(raw_ostream &O, const Twine &Indent, } #endif +void VPMonotonicPHIRecipe::execute(VPTransformState &State) { + assert(getParent()->getPlan()->getUF() == 1 && "Expected unroll factor 1."); + Value *Start = getStartValue

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
@@ -3193,6 +3239,9 @@ class LLVM_ABI_FOR_TEST VPWidenMemoryRecipe : public VPRecipeBase, /// Whether the consecutive accessed addresses are in reverse order. bool Reverse; + /// Whether the consecutive accessed addresses are compressed with mask value. + bool Compresse

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
skachkov-sc wrote: > I think you can probably make this independent of #140721 by first just > supporting cases where to compressed store does not alias any of the other > memory accesses? Yes, the changes in LAA are fully independent, we can skip them for now. > Curious if you already have a

[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns in VPlan (PR #140723)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc updated https://github.com/llvm/llvm-project/pull/140723 >From 2f9baaf83b414b8d2cad73a4ada7efe800a02809 Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date: Wed, 15 Jan 2025 16:09:16 +0300 Subject: [PATCH 1/2] [LoopVectorize][NFC] Add pre-commit tests --- .../Loo

[llvm-branch-commits] [llvm] [LoopVectorize][NFC] Refactor widening decision logic (PR #140722)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc updated https://github.com/llvm/llvm-project/pull/140722 >From 9ae9f1d152b47f6fbf920a7e932b491521b5471d Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date: Wed, 22 Nov 2023 17:24:08 +0300 Subject: [PATCH] [LoopVectorize][NFC] Refactor widening decision logic ---

[llvm-branch-commits] [llvm] [LAA] Support monotonic pointers in LoopAccessAnalysis (PR #140721)

2025-11-07 Thread Sergey Kachkov via llvm-branch-commits
https://github.com/skachkov-sc updated https://github.com/llvm/llvm-project/pull/140721 >From 64a329ce099a2db1e5404a461069a7ce6827f57b Mon Sep 17 00:00:00 2001 From: Sergey Kachkov Date: Thu, 23 Jan 2025 16:16:40 +0300 Subject: [PATCH 1/2] [LAA] Add pre-commit test --- .../LoopAccessAnalysis/

[llvm-branch-commits] [llvm] [LAA] Support monotonic pointers in LoopAccessAnalysis (PR #140721)

2025-05-27 Thread Sergey Kachkov via llvm-branch-commits
skachkov-sc wrote: Gentle ping https://github.com/llvm/llvm-project/pull/140721 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits