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https://github.com/llvm/llvm-project/pull/90049
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@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store(
%passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64)
define @vpmerge_vleff( %passthru, ptr %p,
%m, i32 zeroext %vl) {
; CHECK-LABEL: vpmerge_vleff:
; CHECK: # %bb.0:
-; CHECK-NEXT:vsetvli zero,
https://github.com/lukel97 approved this pull request.
https://github.com/llvm/llvm-project/pull/90049
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https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/90049
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@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store(
%passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64)
define @vpmerge_vleff( %passthru, ptr %p,
%m, i32 zeroext %vl) {
; CHECK-LABEL: vpmerge_vleff:
; CHECK: # %bb.0:
-; CHECK-NEXT:vsetvli zero,
wangpc-pp wrote:
According to `Target.td`:
```c
// Does the instruction have side effects that are not captured by any
// operands of the instruction or other flags?
bit hasSideEffects = ?;
```
It seems we don't need to set `hasSideEffects` for vleNff since we have
modelled `vl` as an output
wangpc-pp wrote:
> > For saturating instructions, they may write vxsat. This is like
> > floating-point instructions that may write fflags, but we don't
> > model floating-point instructions as hasSideEffects=1.
>
> That's because floating point instructions use mayRaiseFPExceptions=1. And
>
topperc wrote:
> For saturating instructions, they may write vxsat. This is like
floating-point instructions that may write fflags, but we don't
model floating-point instructions as hasSideEffects=1.
That's because floating point instructions use mayRaiseFPExceptions=1. And
STRICT_* nodes set
https://github.com/lukel97 edited
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https://github.com/lukel97 commented:
Removing it from vleNff sense to me. As long as we have the implicit-def $vl on
the pseudo to prevent it being moved between vsetvlis I think it should be ok.
https://github.com/llvm/llvm-project/pull/90049
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llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
Masking them as `hasSideEffects=1` stops some optimizations.
For saturating instructions, they may write `vxsat`. This is like
floating-point instructions that may write `fflags`, but we don't
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: Pengcheng Wang (wangpc-pp)
Changes
Masking them as `hasSideEffects=1` stops some optimizations.
For saturating instructions, they may write `vxsat`. This is like
floating-point instructions that may write `fflags`, but we don't
model
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/90049
Masking them as `hasSideEffects=1` stops some optimizations.
For saturating instructions, they may write `vxsat`. This is like
floating-point instructions that may write `fflags`, but we don't
model
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