[llvm-branch-commits] [llvm-branch] r293317 - Merging r292472:

Author: arsenm Date: Fri Jan 27 12:31:33 2017 New Revision: 293317 URL: http://llvm.org/viewvc/llvm-project?rev=293317=rev Log: Merging r292472: r292472 | arsenm | 2017-01-18 22:04:12 -0800 (Wed, 18 Jan 2017) | 5 lines

[llvm-branch-commits] [llvm-branch] r293329 - Merging r293310:

Author: arsenm Date: Fri Jan 27 14:21:31 2017 New Revision: 293329 URL: http://llvm.org/viewvc/llvm-project?rev=293329=rev Log: Merging r293310: r293310 | arsenm | 2017-01-27 09:42:26 -0800 (Fri, 27 Jan 2017) | 8 lines

[llvm-branch-commits] [llvm-branch] r309157 - Merging rr308903:

Author: arsenm Date: Wed Jul 26 11:59:42 2017 New Revision: 309157 URL: http://llvm.org/viewvc/llvm-project?rev=309157=rev Log: Merging rr308903: r308903 | arsenm | 2017-07-24 11:06:15 -0700 (Mon, 24 Jul 2017) | 5 lines

[llvm-branch-commits] [llvm-branch] r308482 - Add some 5.0 release notes

Author: arsenm Date: Wed Jul 19 07:56:08 2017 New Revision: 308482 URL: http://llvm.org/viewvc/llvm-project?rev=308482=rev Log: Add some 5.0 release notes Note speculatable and alloca address space change. Modified: llvm/branches/release_50/docs/ReleaseNotes.rst Modified:

[llvm-branch-commits] [llvm-branch] r362161 - Merging r359883:

Author: arsenm Date: Thu May 30 14:54:55 2019 New Revision: 362161 URL: http://llvm.org/viewvc/llvm-project?rev=362161=rev Log: Merging r359883: r359883 | arsenm | 2019-05-03 06:42:56 -0700 (Fri, 03 May 2019) | 6 lines

[llvm-branch-commits] [llvm-branch] r362634 - Merging r359891:

Author: arsenm Date: Wed Jun 5 12:06:41 2019 New Revision: 362634 URL: http://llvm.org/viewvc/llvm-project?rev=362634=rev Log: Merging r359891: r359891 | arsenm | 2019-05-03 07:40:10 -0700 (Fri, 03 May 2019) | 9 lines

[llvm-branch-commits] [llvm-branch] r362635 - Correct test in r362634

Author: arsenm Date: Wed Jun 5 12:42:03 2019 New Revision: 362635 URL: http://llvm.org/viewvc/llvm-project?rev=362635=rev Log: Correct test in r362634 Modified: llvm/branches/release_80/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir Modified:

[llvm-branch-commits] [llvm-branch] r362648 - Merging r359898:

Author: arsenm Date: Wed Jun 5 14:02:10 2019 New Revision: 362648 URL: http://llvm.org/viewvc/llvm-project?rev=362648=rev Log: Merging r359898: r359898 | arsenm | 2019-05-03 08:21:53 -0700 (Fri, 03 May 2019) | 3 lines

[llvm-branch-commits] [llvm-branch] r362654 - Merging r359899:

Author: arsenm Date: Wed Jun 5 14:23:44 2019 New Revision: 362654 URL: http://llvm.org/viewvc/llvm-project?rev=362654=rev Log: Merging r359899: r359899 | arsenm | 2019-05-03 08:37:07 -0700 (Fri, 03 May 2019) | 7 lines

[llvm-branch-commits] [llvm-branch] r362658 - Merging r360293:

Author: arsenm Date: Wed Jun 5 14:43:28 2019 New Revision: 362658 URL: http://llvm.org/viewvc/llvm-project?rev=362658=rev Log: Merging r360293: r360293 | arsenm | 2019-05-08 15:09:57 -0700 (Wed, 08 May 2019) | 21 lines

[llvm-branch-commits] [llvm] 3d39709 - AMDGPU: Remove wrapper only call limitation

Author: Matt Arsenault Date: 2021-01-12T17:12:49-05:00 New Revision: 3d397091591fca4aa16153bba22f031218bee47d URL: https://github.com/llvm/llvm-project/commit/3d397091591fca4aa16153bba22f031218bee47d DIFF:

[llvm-branch-commits] [llvm] 2cbbc6e - GlobalISel: Fail legalization on narrowing extload below memory size

Author: Matt Arsenault Date: 2021-01-07T17:40:34-05:00 New Revision: 2cbbc6e87c4b565a54c9bb85e34d464acb608f16 URL: https://github.com/llvm/llvm-project/commit/2cbbc6e87c4b565a54c9bb85e34d464acb608f16 DIFF:

[llvm-branch-commits] [llvm] 1f9b6ef - GlobalISel: Add combine for G_UREM by power of 2

Author: Matt Arsenault Date: 2021-01-07T16:36:35-05:00 New Revision: 1f9b6ef91ffd8ea487aa083d146c7568e7243457 URL: https://github.com/llvm/llvm-project/commit/1f9b6ef91ffd8ea487aa083d146c7568e7243457 DIFF:

[llvm-branch-commits] [llvm] 6b7d5a9 - AMDGPU/GlobalISel: Start cleaning up calling convention lowering

Author: Matt Arsenault Date: 2021-01-07T10:36:45-05:00 New Revision: 6b7d5a928f5e0d5321b641909f84cb238e8194b8 URL: https://github.com/llvm/llvm-project/commit/6b7d5a928f5e0d5321b641909f84cb238e8194b8 DIFF:

[llvm-branch-commits] [llvm] 29bd651 - SplitKit: Use Register

Author: Matt Arsenault Date: 2020-11-30T15:09:33-05:00 New Revision: 29bd6519d2e220f6a0ab27efd0adbe16ac01a7ef URL: https://github.com/llvm/llvm-project/commit/29bd6519d2e220f6a0ab27efd0adbe16ac01a7ef DIFF:

[llvm-branch-commits] [llvm] 36a23b3 - X86: Correcting X86OutgoingValueHandler typo (NFC)

Author: Chris Sears Date: 2020-12-12T20:28:37-05:00 New Revision: 36a23b33aa5ef2600e53772680fc14b4e5c676f0 URL: https://github.com/llvm/llvm-project/commit/36a23b33aa5ef2600e53772680fc14b4e5c676f0 DIFF: https://github.com/llvm/llvm-project/commit/36a23b33aa5ef2600e53772680fc14b4e5c676f0.diff

[llvm-branch-commits] [llvm] f3e0431 - LangRef: Update byval/sret description for required types

Author: Matt Arsenault Date: 2020-12-16T10:25:36-05:00 New Revision: f3e0431b763979c373258f7222668e87bb5d28cb URL: https://github.com/llvm/llvm-project/commit/f3e0431b763979c373258f7222668e87bb5d28cb DIFF:

[llvm-branch-commits] [llvm] 60eba81 - RegisterCoalescer: Remove phi-only subranges when erasing identity copies

Author: Matt Arsenault Date: 2020-12-15T17:36:32-05:00 New Revision: 60eba8161bd314eaf02952deaa023c334fcca080 URL: https://github.com/llvm/llvm-project/commit/60eba8161bd314eaf02952deaa023c334fcca080 DIFF:

[llvm-branch-commits] [llvm] 97f51f0 - AMDGPU: Remove redundant CCAction for i1

Author: Matt Arsenault Date: 2020-12-15T17:00:27-05:00 New Revision: 97f51f0489e55ec73efd8d1623d19b3455f39878 URL: https://github.com/llvm/llvm-project/commit/97f51f0489e55ec73efd8d1623d19b3455f39878 DIFF:

[llvm-branch-commits] [llvm] e7e7d37 - GlobalISel: Fix generic handling of single outgoing call arguments

Author: Matt Arsenault Date: 2020-12-15T17:00:27-05:00 New Revision: e7e7d371fd871c9976bd2c7bbb9be60fe37c6d28 URL: https://github.com/llvm/llvm-project/commit/e7e7d371fd871c9976bd2c7bbb9be60fe37c6d28 DIFF:

[llvm-branch-commits] [llvm] 5bec082 - VirtRegMap: Use Register

Author: Matt Arsenault Date: 2020-12-22T20:56:14-05:00 New Revision: 5bec0828347893544ab863ddf4caa2f0b5ef79dd URL: https://github.com/llvm/llvm-project/commit/5bec0828347893544ab863ddf4caa2f0b5ef79dd DIFF:

[llvm-branch-commits] [llvm] 29ed846 - AMDGPU: Fix assert when checking for implicit operand legality

Author: Matt Arsenault Date: 2020-12-22T20:56:24-05:00 New Revision: 29ed846d671117b9a635767dac43cb19fb5ce11f URL: https://github.com/llvm/llvm-project/commit/29ed846d671117b9a635767dac43cb19fb5ce11f DIFF:

[llvm-branch-commits] [llvm] bac5463 - AMDGPU: Add spilled CSR SGPRs to entry block live ins

Author: Matt Arsenault Date: 2020-12-22T21:55:59-05:00 New Revision: bac54639c7be602cabffcc3b801316f784f1c4b1 URL: https://github.com/llvm/llvm-project/commit/bac54639c7be602cabffcc3b801316f784f1c4b1 DIFF:

[llvm-branch-commits] [llvm] 8bf9cde - AMDGPU: Use Register

Author: Matt Arsenault Date: 2020-12-22T21:55:59-05:00 New Revision: 8bf9cdeaee4834bcba35322f1d84c57c691d2244 URL: https://github.com/llvm/llvm-project/commit/8bf9cdeaee4834bcba35322f1d84c57c691d2244 DIFF:

[llvm-branch-commits] [llvm] 581d13f - GlobalISel: Return APInt from getConstantVRegVal

Author: Matt Arsenault Date: 2020-12-22T22:23:58-05:00 New Revision: 581d13f8aeb66c040d5ea69ad4385f766e1f97c9 URL: https://github.com/llvm/llvm-project/commit/581d13f8aeb66c040d5ea69ad4385f766e1f97c9 DIFF:

[llvm-branch-commits] [clang] ef4da3c - clang: Add byval on x86_intrcc parameter 0

Author: Matt Arsenault Date: 2020-12-14T16:34:37-05:00 New Revision: ef4da3c2ba8a812a695361d786e3de8a8b2cd482 URL: https://github.com/llvm/llvm-project/commit/ef4da3c2ba8a812a695361d786e3de8a8b2cd482 DIFF:

[llvm-branch-commits] [llvm] 2e0e03c - OpaquePtr: Require byval on x86_intrcc parameter 0

Author: Matt Arsenault Date: 2020-12-14T16:34:37-05:00 New Revision: 2e0e03c6a089da39039ec3f464f7cee5df86646b URL: https://github.com/llvm/llvm-project/commit/2e0e03c6a089da39039ec3f464f7cee5df86646b DIFF:

[llvm-branch-commits] [llvm] f333736 - AMDGPU: Remove SGPRSpillVGPRDefinedSet hack

Author: Matt Arsenault Date: 2020-12-16T21:33:35-05:00 New Revision: f333736757e9df318b2c3490c61341966024561b URL: https://github.com/llvm/llvm-project/commit/f333736757e9df318b2c3490c61341966024561b DIFF:

[llvm-branch-commits] [llvm] fd0f5fb - PEI: Only call updateLiveness once per function

Author: Matt Arsenault Date: 2020-12-18T11:02:28-05:00 New Revision: fd0f5fb8de26230cbb0eeedaef58036ddede4c63 URL: https://github.com/llvm/llvm-project/commit/fd0f5fb8de26230cbb0eeedaef58036ddede4c63 DIFF:

[llvm-branch-commits] [llvm] a427f15 - GlobalISel: Add isKnownToBeAPowerOfTwo helper function

Author: Matt Arsenault Date: 2021-01-05T12:59:08-05:00 New Revision: a427f15d6070fd50457c553a097e031139b40886 URL: https://github.com/llvm/llvm-project/commit/a427f15d6070fd50457c553a097e031139b40886 DIFF:

[llvm-branch-commits] [llvm] 136f498 - AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests

Author: Matt Arsenault Date: 2021-01-06T11:37:00-05:00 New Revision: 136f49891953ce232be2f4a8bc98e83bb2cd6462 URL: https://github.com/llvm/llvm-project/commit/136f49891953ce232be2f4a8bc98e83bb2cd6462 DIFF:

[llvm-branch-commits] [llvm] ab3a3f5 - AMDGPU/GlobalISel: Update fdiv lowering for denormal/ulp interaction

Author: Matt Arsenault Date: 2021-01-06T12:32:01-05:00 New Revision: ab3a3f543b18d36cec98faa9ca2a68cc9a6ecc65 URL: https://github.com/llvm/llvm-project/commit/ab3a3f543b18d36cec98faa9ca2a68cc9a6ecc65 DIFF:

[llvm-branch-commits] [llvm] 35c535a - AArch64/GlobalISel: Factor out parametersInCSRMatch

Author: Matt Arsenault Date: 2021-01-21T10:32:48-05:00 New Revision: 35c535a7df3c392389de434fc47ec3c47c46537a URL: https://github.com/llvm/llvm-project/commit/35c535a7df3c392389de434fc47ec3c47c46537a DIFF:

[llvm-branch-commits] [llvm] 2a0db8d - AMDGPU: Use more accurate fast f64 fdiv

Author: Matt Arsenault Date: 2021-01-21T10:51:36-05:00 New Revision: 2a0db8d70eeb0c4c09e4c91b365630eefbbf3993 URL: https://github.com/llvm/llvm-project/commit/2a0db8d70eeb0c4c09e4c91b365630eefbbf3993 DIFF:

[llvm-branch-commits] [llvm] 94375d1 - AMDGPU: Remove v_rsq_f64 patterns

Author: Matt Arsenault Date: 2021-01-21T10:51:36-05:00 New Revision: 94375d1083ccc9187c2502894f1dad62d9dd92b9 URL: https://github.com/llvm/llvm-project/commit/94375d1083ccc9187c2502894f1dad62d9dd92b9 DIFF:

[llvm-branch-commits] [llvm] 20566a2 - AMDGPU: Add occupancy to serialized MachineFunctionInfo

Author: Matt Arsenault Date: 2021-01-21T09:21:00-05:00 New Revision: 20566a2ed825c05d56708552d33d95ee12255f46 URL: https://github.com/llvm/llvm-project/commit/20566a2ed825c05d56708552d33d95ee12255f46 DIFF:

[llvm-branch-commits] [llvm] d55d592 - GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper

Author: Matt Arsenault Date: 2021-01-13T10:44:31-05:00 New Revision: d55d592a921f1cd6a922bfff6662f8722d9c URL: https://github.com/llvm/llvm-project/commit/d55d592a921f1cd6a922bfff6662f8722d9c DIFF:

[llvm-branch-commits] [llvm] d8938c8 - CodeGen: Use Register

Author: Matt Arsenault Date: 2021-01-04T12:53:06-05:00 New Revision: d8938c8bb5479b168d27d3e161cb3a53e8ff09f0 URL: https://github.com/llvm/llvm-project/commit/d8938c8bb5479b168d27d3e161cb3a53e8ff09f0 DIFF:

[llvm-branch-commits] [llvm] c9122dd - CodeGen: Refactor regallocator command line and target selection

Author: Matt Arsenault Date: 2021-01-07T13:13:25-05:00 New Revision: c9122ddef5213fbdd2d82c473a74e1742010f62f URL: https://github.com/llvm/llvm-project/commit/c9122ddef5213fbdd2d82c473a74e1742010f62f DIFF:

[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISel] Don't pointlessly lower G_TRUNC (#81479) (PR #81581)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/81581 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79718 (PR #81241)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/81241 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 5e94080 - AMDGPU: Regenerate test checks

Author: Matt Arsenault Date: 2023-12-02T21:42:05+07:00 New Revision: 5e94080fc7cd920107d3d2291c872b510b6ab017 URL: https://github.com/llvm/llvm-project/commit/5e94080fc7cd920107d3d2291c872b510b6ab017 DIFF:

[llvm-branch-commits] [llvm] 3c86bc0 - AMDGPU: Add more tests for rootn libcall handling

Author: Matt Arsenault Date: 2023-12-02T21:53:31+07:00 New Revision: 3c86bc0ae9b3df289ca005d3c451512f01be6d61 URL: https://github.com/llvm/llvm-project/commit/3c86bc0ae9b3df289ca005d3c451512f01be6d61 DIFF:

[llvm-branch-commits] [llvm] Fill 17.x/ReleaseNotes with my works (PR #73461)

arsenm wrote: > Oh, this is 1st time pull request to me. For release branches, I think you are still supposed to use https://github.com/llvm/llvm-project-release-prs https://github.com/llvm/llvm-project/pull/73461 ___ llvm-branch-commits mailing

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79451 (PR #79457)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79457 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Backport 45d2d7757feb386186f69af6ef57bde7b5adc2db to release/18.x (PR #79839)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/79839 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Backport 45d2d7757feb386186f69af6ef57bde7b5adc2db to release/18.x (PR #79839)

@@ -6883,6 +6883,23 @@ bool AMDGPULegalizerInfo::legalizeStackSave(MachineInstr , return true; } +bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr , + MachineIRBuilder ) const { + // With architected SGPRs, waveIDinGroup is in

[llvm-branch-commits] [llvm] Backport 45d2d7757feb386186f69af6ef57bde7b5adc2db to release/18.x (PR #79839)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79839 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [mlir] [llvm] PR for llvm/llvm-project#79293 (PR #79461)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79461 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79420 (PR #79595)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79595 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [TableGen] Fix wrong codegen of BothFusionPredicateWithMCInstPredicate (#83990) (PR #83999)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/83999 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [IR] Introduce `llvm.experimental.hot()` (PR #84850)

@@ -7276,6 +7276,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst , setValue(, getValue(I.getArgOperand(0))); return; + case Intrinsic::experimental_hot: +// Default lowering to false. It's intended to be lowered as soon as profile +// is

[llvm-branch-commits] [IR] Introduce `llvm.experimental.hot()` (PR #84850)

@@ -7276,6 +7276,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst , setValue(, getValue(I.getArgOperand(0))); return; + case Intrinsic::experimental_hot: +// Default lowering to false. It's intended to be lowered as soon as profile +// is

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CostModel] No cost for llvm.allow.{runtime, ubsan}.check() (PR #86064)

@@ -714,6 +714,8 @@ class TargetTransformInfoImplBase { switch (ICA.getID()) { default: break; +case Intrinsic::allow_runtime_check: arsenm wrote: This whole function seems to be reinventing isAssumeLikeIntrinsic

[llvm-branch-commits] [CodeGen] Add default lowering for llvm.allow.{runtime, ubsan}.check() (PR #86049)

@@ -0,0 +1,30 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=aarch64 | FileCheck %s arsenm wrote: Should use explicit -global-isel=0 for the dag test

[llvm-branch-commits] [llvm] release/18.x: Convert many LivePhysRegs uses to LiveRegUnits (PR #84118)

arsenm wrote: I don't think this should be rushed to the release branch. In particular patches should not deviate from the original main version in exceptional circumstances, but mostly this isn't fixing any known correctness issue https://github.com/llvm/llvm-project/pull/84118

[llvm-branch-commits] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

@@ -2220,6 +2220,14 @@ CGObjCCommonMac::EmitMessageSend(CodeGen::CodeGenFunction , RValue rvalue = CGF.EmitCall(MSI.CallInfo, Callee, Return, ActualArgs, ); + // Set type identifier metadata of indirect calls for call graph section. + if

[llvm-branch-commits] [TableGen][InstrInfoEmitter] Count sub-operands on def operands (PR #88972)

@@ -1181,9 +1181,15 @@ void InstrInfoEmitter::emitRecord( // Each logical operand can be multiple MI operands. MinOperands = Inst.Operands.back().MIOperandNo + Inst.Operands.back().MINumOperands; + // Even the logical output operand may be multiple MI

[llvm-branch-commits] [TableGen][InstrInfoEmitter] Count sub-operands on def operands (PR #88972)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/88972 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [Sparc] Fix instr desc of special register stores (PR #88971)

https://github.com/arsenm approved this pull request. Knowing nothing about SPARC, I don't see how having the address to a store in the output made sense https://github.com/llvm/llvm-project/pull/88971 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [llvm] release/18.x: [GlobalISel] Fix fewerElementsVectorPhi to insert after G_PHIs (#87927) (PR #89240)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/89240 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [GlobalISel] Fix fewerElementsVectorPhi to insert after G_PHIs (#87927) (PR #89240)

https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89240 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArch64] Remove invalid uabdl patterns. (#89272) (PR #89380)

https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89380 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [TableGen] Fix ReplaceRegAction RTTI Kind (PR #89790)

https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89790 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x [SelectionDAG] Prevent combination on inconsistent type in 'carryDiamond' (PR #86697)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/86697 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/90204 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

@@ -5687,6 +5688,39 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo , AllocAlignAttrEmitter AllocAlignAttrEmitter(*this, TargetDecl, CallArgs); Attrs = AllocAlignAttrEmitter.TryEmitAsCallSiteAttribute(Attrs); + if (CGM.getCodeGenOpts().CallGraphSection) { +

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] Fix miscompile bug in combineShiftOfShiftedLogic (#89616) (PR #89766)

=?utf-8?q?Björn?= Pettersson Message-ID: In-Reply-To: https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89766 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] [CodeGen] Add default lowering for llvm.allow.{runtime, ubsan}.check() (PR #86049)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/86049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Mark frame index as "aliased" at argument copy elison (PR #91035)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91035 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91126)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91126 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91580 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

@@ -187,8 +187,12 @@ VmemType getVmemType(const MachineInstr ) { const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode()); const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo = AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); - return BaseInfo->BVH ? VMEM_BVH -

[llvm-branch-commits] [clang] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/87573 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

@@ -5693,6 +5699,36 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo , AllocAlignAttrEmitter AllocAlignAttrEmitter(*this, TargetDecl, CallArgs); Attrs = AllocAlignAttrEmitter.TryEmitAsCallSiteAttribute(Attrs); + if (CGM.getCodeGenOpts().CallGraphSection) { +

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} + +/// Extracts the numeric type id from the CallBase's type operand bundle, +/// and sets TypeId. This is used as

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} + +/// Extracts the numeric type id from the CallBase's type operand bundle, +/// and sets TypeId. This is used as

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} + +/// Extracts the numeric type id from the CallBase's type operand bundle, +/// and sets TypeId. This is used as

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} arsenm wrote: ```suggestion CallSiteInfo() = default; ```

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -7922,6 +7923,10 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo , *DAG.getContext()); RetCCInfo.AnalyzeCallResult(Ins, RetCC); + // Set type id for call site info. + if (MF.getTarget().Options.EmitCallGraphSection && CB &&

[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits