https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/94313
According to RVV spec:
> In general, the requirement is to support LMUL ≥ SEWMIN/ELEN,
> where SEWMIN is the narrowest supported SEW value and ELEN is
> the widest supported SEW value.
>
> For a given supported
@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
vsetvli a2, a0, e32, mf2, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible
with all RVV implementations{{$}}
# CHECK-ENCODING: [0x57,0x76,0x75
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/94313
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wangpc-pp wrote:
We may need it in binutils too. cc @kito-cheng
https://github.com/llvm/llvm-project/pull/94313
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>From 6e3d6329300e27a23481df3e6e01b9763a34d9d2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 6 Jun 2024 15:05:20 +0800
Subject: [PATCH] Address comments
Created using spr 1.3.6-beta.1
---
.../Targe
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/94313
>From 6e3d6329300e27a23481df3e6e01b9763a34d9d2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 6 Jun 2024 15:05:20 +0800
Subject: [PATCH 1/2] Address comments
Created using spr 1.3.6-beta.1
---
.../T
@@ -2211,6 +,16 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector
&Operands) {
if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
+if (Fractional) {
+ unsigned E
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/94313
>From 6e3d6329300e27a23481df3e6e01b9763a34d9d2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 6 Jun 2024 15:05:20 +0800
Subject: [PATCH 1/2] Address comments
Created using spr 1.3.6-beta.1
---
.../T
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/94313
>From 6e3d6329300e27a23481df3e6e01b9763a34d9d2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 6 Jun 2024 15:05:20 +0800
Subject: [PATCH 1/2] Address comments
Created using spr 1.3.6-beta.1
---
.../T
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/97383
The format of dynamic linker is `ld-linux-{arch}-{abi}.so.1`, so
we can just get the arch name from arch type.
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>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/80124
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wangpc-pp wrote:
Ping.
I'd like to push this forward because we don't take branch probabilities into
consideration now.
Example: https://godbolt.org/z/doGhYadKM
We should use branches instead of selects in this case and this patch (the
enabling of SelectOpt) will optimize this.
`clang -O3 -marc
wangpc-pp wrote:
https://github.com/llvm/llvm-project/pull/97708 is splitted out for adding
`FeaturePredictableSelectIsExpensive`.
https://github.com/llvm/llvm-project/pull/80124
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>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/97799
To enhance debugging.
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>From 32227cf222e28b6dc2a514aabfaff1a579f51668 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 5 Jul 2024 18:19:58 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?
wangpc-pp wrote:
> > [EarlyIfCvt] Take branch probablities into consideration
>
> It looks like this MR is only adding a target hook, so this title doesn't
> make sense to me
I was planning to add support to RISCV target, but it depends on your early
if-conversion patch. I will hold this PR u
@@ -913,6 +913,10 @@ class TargetInstrInfo : public MCInstrInfo {
return false;
}
+ /// Return true if the target will always try to convert predictable branches
+ /// to selects.
+ virtual bool shouldConvertPredictableBranches() const { return true; }
+
-
https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/100306
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/100843
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wangpc-pp wrote:
Ping. Are there any more comments?
https://github.com/llvm/llvm-project/pull/84455
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https://github.com/llvm/llvm-project/pull/84455
>From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 17:31:47 +0800
Subject: [PATCH 1/6] Reduce copies
Created using spr 1.3.4
---
llvm/lib/Targe
@@ -212,19 +185,13 @@ body: |
; CHECK-NEXT: $v7 = VMV1R_V $v14
; CHECK-NEXT: $v8 = VMV1R_V $v15
; CHECK-NEXT: $v9 = VMV1R_V $v16
-; CHECK-NEXT: $v4 = VMV1R_V $v10
-; CHECK-NEXT: $v5 = VMV1R_V $v11
-; CHECK-NEXT: $v6 = VMV1R_V $v12
-; CHEC
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84455
>From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 17:31:47 +0800
Subject: [PATCH 1/9] Reduce copies
Created using spr 1.3.4
---
llvm/lib/Targe
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84455
>From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 17:31:47 +0800
Subject: [PATCH 1/9] Reduce copies
Created using spr 1.3.4
---
llvm/lib/Targe
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84894
>From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 18:41:50 +0800
Subject: [PATCH 1/2] Fix wrong arguments
Created using spr 1.3.4
---
llvm/lib
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84894
>From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 18:41:50 +0800
Subject: [PATCH 1/2] Fix wrong arguments
Created using spr 1.3.4
---
llvm/lib
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84455
>From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 17:31:47 +0800
Subject: [PATCH 01/10] Reduce copies
Created using spr 1.3.4
---
llvm/lib/Tar
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84894
>From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 18:41:50 +0800
Subject: [PATCH 1/2] Fix wrong arguments
Created using spr 1.3.4
---
llvm/lib
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84894
>From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 18:41:50 +0800
Subject: [PATCH 1/2] Fix wrong arguments
Created using spr 1.3.4
---
llvm/lib
wangpc-pp wrote:
> Hi @wangpc-pp (or anyone else). If you would like to add a note about this
> fix in the release notes (completely optional). Please reply to this comment
> with a one or two sentence description of the fix.
Yeah, the description can be:
```
Save/restore routines for RV32E/RV6
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/88496
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/90049
Masking them as `hasSideEffects=1` stops some optimizations.
For saturating instructions, they may write `vxsat`. This is like
floating-point instructions that may write `fflags`, but we don't
model floating-po
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/90053
This PR includes:
* vsadd.vv/vsaddu.vv
* vaadd.vv/vaaddu.vv
* vsmul.vv
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wangpc-pp wrote:
Sorry for bothering, I just ran spr on a non-spr branch.
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wangpc-pp wrote:
> > For saturating instructions, they may write vxsat. This is like
> > floating-point instructions that may write fflags, but we don't
> > model floating-point instructions as hasSideEffects=1.
>
> That's because floating point instructions use mayRaiseFPExceptions=1. And
> ST
wangpc-pp wrote:
According to `Target.td`:
```c
// Does the instruction have side effects that are not captured by any
// operands of the instruction or other flags?
bit hasSideEffects = ?;
```
It seems we don't need to set `hasSideEffects` for vleNff since we have
modelled `vl` as an output ope
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/84877
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>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/90187
So we can only mantain one place.
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>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84877
>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90187
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@@ -51,6 +51,14 @@ def Feature64Bit
def FeatureDummy
: SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
+class RISCVProfile features>
+: SubtargetFeature;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
+def RVI20U64 : RISCVProfile<"rvi2
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84877
>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/6] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90187
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>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90187
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/90372
This PR includes:
* vsadd.vv/vsaddu.vv
* vaadd.vv/vaaddu.vv
* vsmul.vv
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This doesn't take effect as we have overrided `enablePostRAScheduler`
and we should use the `FeaturePostRAScheduler` feature in processor
definitions.
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wangpc-pp wrote:
> Submit your PRs to `main` branch
I used [spr](https://getcord.github.io/spr/) to create this PR, so I think it's
OK.
https://github.com/llvm/llvm-project/pull/92871
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wangpc-pp wrote:
> > > Submit your PRs to `main` branch
> >
> >
> > I used [spr](https://getcord.github.io/spr/) to create this PR, so I think
> > it's OK.
>
> No, your target branch is wrong. Either you should want to merge into `main`
> or into a branch for another PR created by `spr`. How
https://github.com/wangpc-pp updated
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wangpc-pp wrote:
These branches are created by `spr`, which is out of my control, and we can
merge it into `main` branch via `spr land`. These branches are just magics
behind `spr`, please don't obsess over this. `spr` is a tool that the community
suggests, I have used it for a long time and I
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>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -0,0 +1,932 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -O2 | FileCheck %s
--check-prefix=CHECK-ALIGNED-RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
}
return Considerable;
}
+
+RISCVTTIImpl::TTI::MemCmpExpansionOptions
+RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
+ TTI::MemCmpExpansionOptions Options;
+ // FIXME
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
}
return Considerable;
}
+
+RISCVTTIImpl::TTI::MemCmpExpansionOptions
+RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
+ TTI::MemCmpExpansionOptions Options;
+ // FIXME
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
wangpc-pp wrote:
> This is perhaps more of a comment for #107824 than for this one, but I think
> we'd benefit from some level of test coverage for OptForSize to demonstrate
> that we stick with the libcall in cases where expanding increases code size.
Thanks! Done!
https://github.com/llvm/ll
wangpc-pp wrote:
> I'm working on getting some runtime numbers now, sorry for the delay.
No need to say sorry, I really appreciate your help! 😃
https://github.com/llvm/llvm-project/pull/107548
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https://github.com/wangpc-pp approved this pull request.
LGTM.
This fixes a bug that exists for a long time.
https://github.com/llvm/llvm-project/pull/108288
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https://lists.llvm.org
wangpc-pp wrote:
> The run just finished, I'm seeing a 0.75% improvement on 500.perlbench_r on
> the BPI F3 (-O3 -mcpu=spacemit-x60), no regressions or improvements on the
> other benchmarks as far as I can see. Seems to check out with the number of
> memcmps inlined reported for perlbench!
T
wangpc-pp wrote:
> > The run just finished, I'm seeing a 0.75% improvement on 500.perlbench_r on
> > the BPI F3 (-O3 -mcpu=spacemit-x60), no regressions or improvements on the
> > other benchmarks as far as I can see. Seems to check out with the number of
> > memcmps inlined reported for perlb
wangpc-pp wrote:
> > > > The run just finished, I'm seeing a 0.75% improvement on
> > > > 500.perlbench_r on the BPI F3 (-O3 -mcpu=spacemit-x60), no regressions
> > > > or improvements on the other benchmarks as far as I can see. Seems to
> > > > check out with the number of memcmps inlined re
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
wangpc-pp wrote:
> Hi, since we are wrapping up LLVM 19.1.0 we are very strict with the fixes we
> pick at this point. Can you please respond to the following questions to help
> me understand if this has to be included in the final release or not.
>
> Is this PR a fix for a regression or a cr
wangpc-pp wrote:
Ping.
And some updates on vector support: currently, `ExpandMemCmp` will only
generate integer types (`i128`, `i256`) and so on. So, if we simply add `128`,
`256`, `vlen` to `LoadSizes`, the LLVM IR will use i128/i256/... and then they
are expanded to legal scalar types as we
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -1144,42 +2872,116 @@ entry:
define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind {
; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -112,42 +104,46 @@ entry:
define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize {
; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -1144,42 +2872,116 @@ entry:
define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind {
; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/107548
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -112,42 +104,46 @@ entry:
define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize {
; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
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