[llvm-branch-commits] [SPARC][IAS] Add support for %uhi and %ulo extensions (PR #94246)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94246 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add aliases for %asr20-21 as defined in JPS1 (PR #94247)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94247 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov commented: Please add testcases for the remaining tags https://github.com/llvm/llvm-project/pull/94249 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listi

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/94249 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
@@ -537,16 +537,26 @@ ! V9: stxa %g0, [%g2+%i5] #ASI_SNF ! encoding: [0xc0,0xf0,0x90,0x7d] stxa %g0, [%g2 + %i5] #ASI_SNF -! V8: error: instruction requires a CPU feature not currently enabled +! V8: error: invalid operand for instr

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
@@ -1088,6 +1115,34 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector &Operands) { return ParseStatus::Success; } +ParseStatus SparcAsmParser::parsePrefetchTag(OperandVector &Operands) { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = Parser.getTok().getEndLoc();

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: The error

[llvm-branch-commits] [SPARC][IAS] Handle the case of non-4-byte aligned writeNopData (PR #94251)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94251 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
@@ -1088,6 +1115,34 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector &Operands) { return ParseStatus::Success; } +ParseStatus SparcAsmParser::parsePrefetchTag(OperandVector &Operands) { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = Parser.getTok().getEndLoc();

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: It is beca

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

2024-06-03 Thread Sergei Barannikov via llvm-branch-commits
@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: With the a

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

2024-06-04 Thread Sergei Barannikov via llvm-branch-commits
@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: I hoped a

[llvm-branch-commits] [llvm] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

2024-06-04 Thread Sergei Barannikov via llvm-branch-commits
@@ -537,16 +537,26 @@ ! V9: stxa %g0, [%g2+%i5] #ASI_SNF ! encoding: [0xc0,0xf0,0x90,0x7d] stxa %g0, [%g2 + %i5] #ASI_SNF -! V8: error: instruction requires a CPU feature not currently enabled +! V8: error: invalid operand for instr

[llvm-branch-commits] [llvm] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

2024-06-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94249 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

2024-06-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94250 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add movr(n)e alias for movr(n)z (PR #94252)

2024-06-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/94252 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

2024-06-19 Thread Sergei Barannikov via llvm-branch-commits
@@ -11,7 +11,7 @@ ! V9: unknown membar tag membar #BadTag -! V8: instruction requires a CPU feature not currently enabled +! V8: unexpected token ! V9: invalid membar mask number membar -127 s-barannikov wrote:

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

2024-06-19 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

2024-06-19 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

2024-06-19 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

2024-06-19 Thread Sergei Barannikov via llvm-branch-commits
@@ -1085,13 +1085,24 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector &Operands) { SMLoc E = Parser.getTok().getEndLoc(); int64_t ASIVal = 0; - if (is64Bit() && (getLexer().getKind() == AsmToken::Hash)) { + switch (getLexer().getKind()) { + case AsmToken::LPare

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

2024-06-19 Thread Sergei Barannikov via llvm-branch-commits
@@ -11,7 +11,7 @@ ! V9: unknown membar tag membar #BadTag -! V8: instruction requires a CPU feature not currently enabled +! V8: unexpected token ! V9: invalid membar mask number membar -127 s-barannikov wrote:

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

2024-06-21 Thread Sergei Barannikov via llvm-branch-commits
@@ -1085,13 +1085,24 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector &Operands) { SMLoc E = Parser.getTok().getEndLoc(); int64_t ASIVal = 0; - if (is64Bit() && (getLexer().getKind() == AsmToken::Hash)) { + switch (getLexer().getKind()) { + case AsmToken::LPare

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

2024-06-23 Thread Sergei Barannikov via llvm-branch-commits
@@ -1360,6 +1372,16 @@ ParseStatus SparcAsmParser::parseBranchModifiers(OperandVector &Operands) { return ParseStatus::Success; } +ParseStatus SparcAsmParser::parseExpression(OperandVector &Operands, s-barannikov wrote: Can you use this method in `parsePre

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

2024-06-23 Thread Sergei Barannikov via llvm-branch-commits
@@ -107,10 +107,15 @@ class SparcAsmParser : public MCTargetAsmParser { ParseStatus parseBranchModifiers(OperandVector &Operands); + ParseStatus parseExpression(OperandVector &Operands, int64_t &Val); + // Helper function for dealing with %lo / %hi in PIC mode. const

[llvm-branch-commits] [llvm] [SPARC][IAS] Rework ASI/Prefetch tag matching in prep for `ParseForAllFeatures` (PR #96020)

2024-06-25 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/96020 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][IAS] Reject unknown/unavailable mnemonics early in ParseInstruction (PR #96021)

2024-07-10 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. The downside of this approach is that you lose the ability to report the missing features (unless you implement it yourself, which would be a code duplication), that would allow to produce instead better diagnostics like "instruction

[llvm-branch-commits] [llvm] [SPARC][IAS] Reject unknown/unavailable mnemonics early in ParseInstruction (PR #96021)

2024-07-10 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AsmPrinter: Avoid use of MachineFunction::getMMI (PR #99751)

2024-07-20 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/99751 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] CodeGen: Remove MachineModuleInfo reference from MachineFunction (PR #100357)

2024-07-24 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/100357 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] CodeGen: Remove MachineModuleInfo reference from MachineFunction (PR #100357)

2024-07-24 Thread Sergei Barannikov via llvm-branch-commits
@@ -8619,21 +8619,21 @@ SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain, const BasicBlock *EHPadBB, MCSymbol *&BeginLabel) { MachineFunction &MF = DAG.getMachineFunction(); - MachineM

[llvm-branch-commits] [llvm] CodeGen: Move current call site out of MachineModuleInfo (PR #100369)

2024-07-26 Thread Sergei Barannikov via llvm-branch-commits
@@ -188,6 +188,14 @@ class FunctionLoweringInfo { /// SelectionDAGISel::PrepareEHLandingPad(). unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg; + /// The current call site index being processed, if any. 0 if none. + unsigned CurCallSite = 0; + // TODO: Ideall

[llvm-branch-commits] [llvm] DebugInfo: Avoid some MMI::hasDebugInfo checks (PR #100333)

2024-07-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/100333 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DebugInfo: Avoid some MMI::hasDebugInfo checks (PR #100333)

2024-07-26 Thread Sergei Barannikov via llvm-branch-commits
@@ -1148,14 +1148,15 @@ sortGlobalExprs(SmallVectorImpl &GVEs) { void DwarfDebug::beginModule(Module *M) { DebugHandlerBase::beginModule(M); - if (!Asm || !MMI->hasDebugInfo()) + if (!Asm) return; unsigned NumDebugCUs = std::distance(M->debug_compile_units_begin

[llvm-branch-commits] [compiler-rt] release/19.x: [builtins] Fix divtc3.c etc. compilation on Solaris/SPARC with gcc (#101662) (PR #101847)

2024-08-14 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov requested changes to this pull request. See https://github.com/llvm/llvm-project/pull/101662#issuecomment-2289589525 https://github.com/llvm/llvm-project/pull/101847 ___ llvm-branch-commits mailing list llvm-branch-commi

[llvm-branch-commits] [llvm] release/19.x: [SPARC] Remove assertions in printOperand for inline asm operands (#104692) (PR #105096)

2024-08-20 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > LGTM. This is the backport to 19 right? Yes https://github.com/llvm/llvm-project/pull/105096 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-comm

[llvm-branch-commits] [llvm] release/19.x: [SPARC] Remove assertions in printOperand for inline asm operands (#104692) (PR #105096)

2024-08-20 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/105096 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [clang] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-08 Thread Sergei Barannikov via llvm-branch-commits
@@ -0,0 +1,18 @@ +; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=CALL %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 -mcpu=ultrasparc | FileCheck --check-prefix=CALL %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileChe

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-08 Thread Sergei Barannikov via llvm-branch-commits
@@ -234,8 +244,15 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // add , %o7, s-barannikov wrote: Please update the comment to include the rdpc case. https://github.com/llvm/llvm-project/pull/77196 ___

[llvm-branch-commits] [llvm] [clang] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-08 Thread Sergei Barannikov via llvm-branch-commits
@@ -118,9 +126,11 @@ def : Proc<"ma2480", [FeatureLeon, LeonCASA]>; def : Proc<"ma2485", [FeatureLeon, LeonCASA]>; def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; def : Proc<"v9", [FeatureV9]>; -def : Proc<"ultrasparc", [FeatureV9, Fe

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-08 Thread Sergei Barannikov via llvm-branch-commits
@@ -234,8 +244,15 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // add , %o7, OutStreamer->emitLabel(StartLabel); - MCOperand Callee = createPCXCallOP(EndLabel, OutContext); - EmitCall(*OutStreamer, Callee, STI); + if (!STI.getTargetTri

[llvm-branch-commits] [llvm] [clang] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-08 Thread Sergei Barannikov via llvm-branch-commits
@@ -118,9 +126,11 @@ def : Proc<"ma2480", [FeatureLeon, LeonCASA]>; def : Proc<"ma2485", [FeatureLeon, LeonCASA]>; def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; def : Proc<"v9", [FeatureV9]>; -def : Proc<"ultrasparc", [FeatureV9, Fe

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-12 Thread Sergei Barannikov via llvm-branch-commits
@@ -0,0 +1,59 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=SPARC %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64 %s

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-12 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/77196 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-12 Thread Sergei Barannikov via llvm-branch-commits
@@ -234,8 +244,15 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // add , %o7, OutStreamer->emitLabel(StartLabel); - MCOperand Callee = createPCXCallOP(EndLabel, OutContext); - EmitCall(*OutStreamer, Callee, STI); + if (!STI.getTargetTri

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-13 Thread Sergei Barannikov via llvm-branch-commits
@@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=SPARC %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64 %s

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-13 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/77196 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

2024-01-15 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: Yes, sure https://github.com/llvm/llvm-project/pull/77196 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/106538 This is a simple change to show how easy it can be to support unusual byte widths in the middle end. >From 3b86337919c0f518c133f09787ddc0518ede4821 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fr

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/106537 This patch changes the type of the value argument of @llvm.memset and similar intrinsics from i8 to iN, where N is the byte width specified in data layout string. Note that the argument still has fixed type

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/106539 The change requires DataLayout instance to be available, which, in turn, requires insertion point to be set. In-tree tests detected only one case when the function was called without setting an insertion poi

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/106538?utm_source=stack-comment-downstack-mergeability-warn

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/106537?utm_source=stack-comment-downstack-mergeability-warn

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/106540 The method has few uses yet, so just pass DL argument to it. The change follows m_PtrToIntSameSize, and I don't see a better way of delivering the byte width to the method. >From 7cca42199cf0bae1b5648ff6b1d

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/106539?utm_source=stack-comment-downstack-mergeability-warn

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/106541 The method assumes that host chars and target chars have the same width. Add a CharWidth argument so that it can bail out if the requested char width differs from the host char width. Alternatively, the che

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/106540?utm_source=stack-comment-downstack-mergeability-warn

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/106542 The patch makes CharWidth argument of `getStringLength` mandatory and ensures the correct values are passed in most cases. This is *not* a complete support for unusual byte widths in SimplifyLibCalls since `

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/106541?utm_source=stack-comment-downstack-mergeability-warn

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/106542?utm_source=stack-comment-downstack-mergeability-warn

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

2024-08-29 Thread Sergei Barannikov via llvm-branch-commits
s-barannikov wrote: > I don't think this is the right direction for memset. I would prefer actually > overloading it and making the memset/memset.pattern distinction redundant. > See also [#97583 > (comment)](https://github.com/llvm/llvm-project/pull/97583#issuecomment-2288302946) > and follo

[llvm-branch-commits] [llvm] [ADT] Use range-based helper functions in SmallSet (PR #108585)

2024-09-14 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov commented: I'm slightly opposed to this change because it pulls in STLExtras.h. Yes, it is already included, but it would be better to avoid including it. https://github.com/llvm/llvm-project/pull/108585 ___ llvm-branch

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2024-11-03 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 9859c07861131607e36d3de2ee0d2a9980b8d6da Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From baf49339251099659d0d78881147c3a1f0407402 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From deca69bea2a9624ba5d12515f2919d88200a5eee Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From 9a1fad3a367f1ee9f26fc0792d3f8e63ae2d7aef Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106537 >From 4cee8631bc6b584e999190966360d7abfb74e84a Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 1 Aug 2024 23:47:25 +0300 Subject: [PATCH] [IR] Make @llvm.memset prototype byte width dependent T

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 699b2bc1c010a39ed5a2a9020b6322f77ca9f6d4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106539 >From ccdc8a112b2d65023c29556910423ae4ba3c6e9e Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 22 Aug 2024 15:10:58 +0300 Subject: [PATCH] [IRBuilder] Add getByteTy and use it in CreatePtrAdd T

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 14e8b418ab296a5c1d8f3103ef95653b995edd3c Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From cdb7292f6ce3f4afc8bf9ac1e3e3942d23c8dce3 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106537 >From edcea1ef65bc4124e58cd493f6206a1ff15bb714 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 1 Aug 2024 23:47:25 +0300 Subject: [PATCH] [IR] Make @llvm.memset prototype byte width dependent T

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From a0d5c61b0f6ac8cb9c9b82ca454034b23f1cdcb2 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From c640baf7c091c9142983c2785ded7ba8ce3cbe46 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From d27bc3081184f9cb967c74abea62b696347f1fa5 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 61be980d13607425cfb38a3ad73ae36dc794bde2 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106539 >From 4d3f0b61baf383759ea5379b57d3f5a1923deee4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 22 Aug 2024 15:10:58 +0300 Subject: [PATCH] [IRBuilder] Add getByteTy and use it in CreatePtrAdd T

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

2024-10-26 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 222a3b7f2ea2d730fdfb9b35a392af5078a17ad4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

2025-02-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106537 >From 65a421f56e7e7bb9a72d0b5cc70f8cc7b4348c9b Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 1 Aug 2024 23:47:25 +0300 Subject: [PATCH] [IR] Make @llvm.memset prototype byte width dependent T

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

2025-02-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From 67765a6e3e4c8e0475cd6baccb801cad1498b36e Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

2025-02-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From 57104d137fdb6e7c9add7ed3fcff37f1dcf56a7f Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

2025-02-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 26dc400bb3e62f33c245082b9d29811d1444560c Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

2025-02-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106539 >From 6d95f98f2de990ff8971400966de74f62ef339bb Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 22 Aug 2024 15:10:58 +0300 Subject: [PATCH] [IRBuilder] Add getByteTy and use it in CreatePtrAdd T

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2025-02-04 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 931d15e69f7c57a7c0a0708853ee50be1e27c769 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

2025-02-01 Thread Sergei Barannikov via llvm-branch-commits
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

2025-02-01 Thread Sergei Barannikov via llvm-branch-commits
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

2025-02-01 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/125150 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

2025-02-01 Thread Sergei Barannikov via llvm-branch-commits
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

2025-01-31 Thread Sergei Barannikov via llvm-branch-commits
@@ -450,6 +450,10 @@ def : InstAlias<"save", (SAVErr G0, G0, G0)>; // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">; +// setsw value, rd +// (tu

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

2025-01-31 Thread Sergei Barannikov via llvm-branch-commits
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

2025-03-22 Thread Sergei Barannikov via llvm-branch-commits
@@ -7,76 +7,96 @@ //===--===// // // This file contains instruction formats, definitions and patterns needed for -// VIS, VIS II, VIS II instructions on SPARC. +// VIS, VIS II, VIS III instructions on SPARC.

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

2025-03-22 Thread Sergei Barannikov via llvm-branch-commits
@@ -82,6 +82,8 @@ def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">; // Instruction Pattern Stuff //===--===// +def siam_mode : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

2025-03-22 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/130967 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

2025-03-22 Thread Sergei Barannikov via llvm-branch-commits
@@ -7,76 +7,96 @@ //===--===// // // This file contains instruction formats, definitions and patterns needed for -// VIS, VIS II, VIS II instructions on SPARC. +// VIS, VIS II, VIS III instructions on SPARC.

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

2025-04-05 Thread Sergei Barannikov via llvm-branch-commits
@@ -0,0 +1,55 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS2 +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis2 -show-encoding | FileCheck %s --check-prefixes=VIS2 + +!! VIS 2 instructions. + +! NO-VIS2: error: instruction requ

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

2025-04-06 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 76b45538d3117532e74dedd9bb2c4e75261702e0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

2025-04-06 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From fe95d6435fd4b964f96351c6fc564cbd853ae8f0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

2025-04-06 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106537 >From 97cce999ea0e569bbf7863316d8fc3e9c653041e Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 1 Aug 2024 23:47:25 +0300 Subject: [PATCH] [IR] Make @llvm.memset prototype byte width dependent T

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

2025-04-06 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From 555e531fdeb40bd54d6eecfed41421546ba9025b Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

2025-04-06 Thread Sergei Barannikov via llvm-branch-commits
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From e75ad5f9a08f81feecf19f0f1c6f0067c24f2faf Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

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