Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.167 - 1.168
---
Log message:
Save/restore VRSAVE once per function, not once per block.
---
Diffs of the changes: (+52 -39)
PPCISelDAGToDAG.cpp | 91 +---
1 files
Changes in directory llvm/test/Regression/CFrontend:
2006-03-16-VectorCtor.c added (r1.1)
---
Log message:
New testcase, the new CFE compiles this into insertelement instructions, the
old one crashes.
---
Diffs of the changes: (+11 -0)
2006-03-16-VectorCtor.c | 11 +++
1 files
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.70 - 1.71
---
Log message:
Another case we could do better on.
---
Diffs of the changes: (+11 -0)
README.txt | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u
Changes in directory llvm-www:
Features.html updated: 1.15 - 1.16
OpenProjects.html updated: 1.11 - 1.12
Oversight.html updated: 1.4 - 1.5
header.incl updated: 1.44 - 1.45
---
Log message:
llvm.cs - llvm.org
---
Diffs of the changes: (+0 -0)
0 files changed
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.46 - 1.47
---
Log message:
set TransformToType correctly for vector types.
---
Diffs of the changes: (+8 -0)
TargetLowering.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.189 - 1.190
---
Log message:
Teach CreateRegForValue how to handle vector types.
---
Diffs of the changes: (+53 -23)
SelectionDAGISel.cpp | 76 +++
1 files
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.190 - 1.191
---
Log message:
Add support for CopyFromReg from vector values. Note: this doesn't support
illegal vector types yet!
---
Diffs of the changes: (+119 -104)
SelectionDAGISel.cpp | 223
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.17 - 1.18
PPCInstrInfo.td updated: 1.183 - 1.184
PPCRegisterInfo.cpp updated: 1.44 - 1.45
---
Log message:
Add support for copying registers. still needed: spilling and reloading them
---
Diffs of the changes: (+7 -1)
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.45 - 1.46
---
Log message:
in functions that use a lot of callee saved regs, this can be more than
5 instructions away.
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.60 - 1.61
---
Log message:
Added a way for TargetLowering to specify what values can be used as the
scale component of the target addressing mode.
---
Diffs of the changes: (+28 -9)
TargetLowering.h | 37
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.105 - 1.106
X86TargetMachine.cpp updated: 1.107 - 1.108
---
Log message:
Added a way for TargetLowering to specify what values can be used as the
scale component of the target addressing mode.
---
Diffs of the changes:
Changes in directory llvm/include/llvm/Transforms:
Scalar.h updated: 1.61 - 1.62
---
Log message:
For each loop, keep track of all the IV expressions inserted indexed by
stride. For a set of uses of the IV of a stride which is a multiple
of another stride, do not insert a new IV expression.
Changes in directory llvm/lib/Transforms/Scalar:
LoopStrengthReduce.cpp updated: 1.76 - 1.77
---
Log message:
For each loop, keep track of all the IV expressions inserted indexed by
stride. For a set of uses of the IV of a stride which is a multiple
of another stride, do not insert a new IV
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.106 - 1.107
---
Log message:
Bug fix: condition inverted.
---
Diffs of the changes: (+1 -1)
X86ISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPC.td updated: 1.14 - 1.15
---
Log message:
add callee saved vector regs
---
Diffs of the changes: (+2 -1)
PPC.td |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPC.td
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.18 - 1.19
PPCRegisterInfo.cpp updated: 1.46 - 1.47
---
Log message:
teach the ppc backend how to spill/reload vector regs
---
Diffs of the changes: (+21 -1)
PPCInstrInfo.cpp|2 +-
PPCRegisterInfo.cpp | 20
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.71 - 1.72
---
Log message:
add a note
---
Diffs of the changes: (+8 -1)
README.txt |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.184 - 1.185
---
Log message:
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
---
Diffs of the changes: (+1 -0)
PPCInstrInfo.td |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.65 - 1.66
---
Log message:
A new entry.
---
Diffs of the changes: (+45 -0)
README.txt | 45 +
1 files changed, 45 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.191 - 1.192
---
Log message:
Fix a problem fully scalarizing values.
---
Diffs of the changes: (+4 -1)
SelectionDAGISel.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/tools/bugpoint:
CrashDebugger.cpp updated: 1.46 - 1.47
---
Log message:
add an assert to get a slightly better msg about this problem
---
Diffs of the changes: (+3 -0)
CrashDebugger.cpp |3 +++
1 files changed, 3 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.47 - 1.48
---
Log message:
remove dead variable
---
Diffs of the changes: (+0 -2)
PPCRegisterInfo.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u
Changes in directory llvm/lib/Target:
README.txt updated: 1.21 - 1.22
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
---
Diffs of the changes: (+5 -1)
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.35 - 1.36
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
---
Diffs of the changes:
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.110 - 1.111
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
---
Diffs of the
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.126 - 1.127
LegalizeDAG.cpp updated: 1.315 - 1.316
SelectionDAG.cpp updated: 1.270 - 1.271
SelectionDAGISel.cpp updated: 1.192 - 1.193
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.40 - 1.41
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
---
Diffs of the changes:
Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.21 - 1.22
PPCISelDAGToDAG.cpp updated: 1.168 - 1.169
PPCISelLowering.cpp updated: 1.96 - 1.97
PPCInstrInfo.td updated: 1.185 - 1.186
README.txt updated: 1.73 - 1.74
---
Log message:
Remove BRTWOWAY*
Make the PPC
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.253 - 1.254
---
Log message:
- Nuke 16-bit SBB instructions. We'll never use them.
- Nuke a bogus comment.
---
Diffs of the changes: (+0 -21)
X86InstrInfo.td | 21 -
1 files changed, 21 deletions(-)
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.127 - 1.128
---
Log message:
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
ADD32ri8.
---
Diffs of the changes: (+18 -6)
X86RegisterInfo.cpp | 24 ++--
1 files changed,
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.128 - 1.129
---
Log message:
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
---
Diffs of the changes: (+9 -0)
X86RegisterInfo.cpp |9 +
1 files changed, 9 insertions(+)
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.108 - 1.109
---
Log message:
Parameterize the number of integer arguments to pass in registers
---
Diffs of the changes: (+27 -17)
X86ISelLowering.cpp | 44 +++-
1 files
Changes in directory llvm/lib/VMCore:
Makefile updated: 1.11 - 1.12
---
Log message:
Two fixes:
1. Allow building of Intrinsics.gen to work for srcdir != objdir
2. Add a rule for installation of Intrinsics.gen.
---
Diffs of the changes: (+5 -1)
Makefile |6 +-
1 files changed, 5
Changes in directory llvm/lib/VMCore:
Makefile updated: 1.12 - 1.13
---
Log message:
Fix use of LEVEL.
---
Diffs of the changes: (+1 -1)
Makefile |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/VMCore/Makefile
diff -u llvm/lib/VMCore/Makefile:1.12
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