[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachOWriterInfo.h
Changes in directory llvm/include/llvm/Target:
TargetMachOWriterInfo.h added (r1.1)
---
Log message:
New TargetMachOWriterInfo class. It holds target-specific information
that the MachOWriter needs in order to do its writing stuff 'n things.
---
Diffs of the changes: (+103 -0)
TargetMachOWriterInfo.h | 103
1 files changed, 103 insertions(+)
Index: llvm/include/llvm/Target/TargetMachOWriterInfo.h
diff -c /dev/null llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.1
*** /dev/null Tue Jan 23 21:36:15 2007
--- llvm/include/llvm/Target/TargetMachOWriterInfo.hTue Jan 23 21:36:05 2007
***
*** 0
--- 1,103
+ //===-- llvm/Target/TargetMachOWriterInfo.h - MachO Writer Info--*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Bill Wendling and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file defines the TargetMachOWriterInfo class.
+ //
+
//===--===//
+
+ #ifndef LLVM_TARGET_TARGETMACHOWRITERINFO_H
+ #define LLVM_TARGET_TARGETMACHOWRITERINFO_H
+
+ #include llvm/CodeGen/MachineRelocation.h
+
+ namespace llvm {
+
+ class MachineBasicBlock;
+
+
//======//
+ //TargetMachOWriterInfo
+
//======//
+
+ struct TargetMachOWriterInfo {
+ uint32_t CPUType; // CPU specifier
+ uint32_t CPUSubType; // Machine specifier
+
+ // The various CPU_TYPE_* constants are already defined by at least one
+ // system header file and create compilation errors if not respected.
+ #if !defined(CPU_TYPE_I386)
+ #define CPU_TYPE_I386 7
+ #endif
+ #if !defined(CPU_TYPE_X86_64)
+ #define CPU_TYPE_X86_64 (CPU_TYPE_I386 | 0x100)
+ #endif
+ #if !defined(CPU_TYPE_ARM)
+ #define CPU_TYPE_ARM12
+ #endif
+ #if !defined(CPU_TYPE_SPARC)
+ #define CPU_TYPE_SPARC 14
+ #endif
+ #if !defined(CPU_TYPE_POWERPC)
+ #define CPU_TYPE_POWERPC18
+ #endif
+ #if !defined(CPU_TYPE_POWERPC64)
+ #define CPU_TYPE_POWERPC64 (CPU_TYPE_POWERPC | 0x100)
+ #endif
+
+ // Constants for the cputype field
+ // see mach/machine.h
+ enum {
+ HDR_CPU_TYPE_I386 = CPU_TYPE_I386,
+ HDR_CPU_TYPE_X86_64= CPU_TYPE_X86_64,
+ HDR_CPU_TYPE_ARM = CPU_TYPE_ARM,
+ HDR_CPU_TYPE_SPARC = CPU_TYPE_SPARC,
+ HDR_CPU_TYPE_POWERPC = CPU_TYPE_POWERPC,
+ HDR_CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC64
+ };
+
+ #if !defined(CPU_SUBTYPE_I386_ALL)
+ #define CPU_SUBTYPE_I386_ALL3
+ #endif
+ #if !defined(CPU_SUBTYPE_X86_64_ALL)
+ #define CPU_SUBTYPE_X86_64_ALL 3
+ #endif
+ #if !defined(CPU_SUBTYPE_ARM_ALL)
+ #define CPU_SUBTYPE_ARM_ALL 0
+ #endif
+ #if !defined(CPU_SUBTYPE_SPARC_ALL)
+ #define CPU_SUBTYPE_SPARC_ALL 0
+ #endif
+ #if !defined(CPU_SUBTYPE_POWERPC_ALL)
+ #define CPU_SUBTYPE_POWERPC_ALL 0
+ #endif
+
+ // Constants for the cpusubtype field
+ // see mach/machine.h
+ enum {
+ HDR_CPU_SUBTYPE_I386_ALL= CPU_SUBTYPE_I386_ALL,
+ HDR_CPU_SUBTYPE_X86_64_ALL = CPU_SUBTYPE_X86_64_ALL,
+ HDR_CPU_SUBTYPE_ARM_ALL = CPU_SUBTYPE_ARM_ALL,
+ HDR_CPU_SUBTYPE_SPARC_ALL = CPU_SUBTYPE_SPARC_ALL,
+ HDR_CPU_SUBTYPE_POWERPC_ALL = CPU_SUBTYPE_POWERPC_ALL
+ };
+
+ TargetMachOWriterInfo(uint32_t cputype, uint32_t cpusubtype)
+ : CPUType(cputype), CPUSubType(cpusubtype) {}
+ virtual ~TargetMachOWriterInfo() {}
+
+ virtual MachineRelocation GetJTRelocation(unsigned Offset,
+ MachineBasicBlock *MBB) const;
+
+ virtual const char *getPassName() const {
+ return Mach-O Writer;
+ }
+ };
+
+ } // end llvm namespace
+
+ #endif // LLVM_TARGET_TARGETMACHOWRITERINFO_H
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachOWriter.h
Changes in directory llvm/include/llvm/CodeGen:
MachOWriter.h updated: 1.14 - 1.15
---
Log message:
Moved target-specific information to the TargetMachOWriterInfo obj.
---
Diffs of the changes: (+7 -62)
MachOWriter.h | 69 +-
1 files changed, 7 insertions(+), 62 deletions(-)
Index: llvm/include/llvm/CodeGen/MachOWriter.h
diff -u llvm/include/llvm/CodeGen/MachOWriter.h:1.14
llvm/include/llvm/CodeGen/MachOWriter.h:1.15
--- llvm/include/llvm/CodeGen/MachOWriter.h:1.14Wed Jan 17 16:22:31 2007
+++ llvm/include/llvm/CodeGen/MachOWriter.h Tue Jan 23 21:37:18 2007
@@ -19,6 +19,7 @@
#include llvm/CodeGen/MachineRelocation.h
#include llvm/Target/TargetData.h
#include llvm/Target/TargetMachine.h
+#include llvm/Target/TargetMachOWriterInfo.h
namespace llvm {
class GlobalVariable;
@@ -126,8 +127,6 @@
/// specific architecture type/subtype pair that is emitted to the file.
struct MachOHeader {
uint32_t magic; // mach magic number identifier
- uint32_t cputype;// cpu specifier
- uint32_t cpusubtype; // machine specifier
uint32_t filetype; // type of file
uint32_t ncmds; // number of load commands
uint32_t sizeofcmds; // the size of all the load commands
@@ -138,62 +137,6 @@
/// up for emission to the file.
DataBuffer HeaderData;
- // The various CPU_TYPE_* constants are already defined by at least one
- // system header file and create compilation errors if not respected.
-#if !defined(CPU_TYPE_I386)
-#define CPU_TYPE_I386 7
-#endif
-#if !defined(CPU_TYPE_X86_64)
-#define CPU_TYPE_X86_64(CPU_TYPE_I386 | 0x100)
-#endif
-#if !defined(CPU_TYPE_ARM)
-#define CPU_TYPE_ARM 12
-#endif
-#if !defined(CPU_TYPE_SPARC)
-#define CPU_TYPE_SPARC 14
-#endif
-#if !defined(CPU_TYPE_POWERPC)
-#define CPU_TYPE_POWERPC 18
-#endif
-#if !defined(CPU_TYPE_POWERPC64)
-#define CPU_TYPE_POWERPC64 (CPU_TYPE_POWERPC | 0x100)
-#endif
-
- // Constants for the cputype field
- // see mach/machine.h
- enum { HDR_CPU_TYPE_I386 = CPU_TYPE_I386,
- HDR_CPU_TYPE_X86_64= CPU_TYPE_X86_64,
- HDR_CPU_TYPE_ARM = CPU_TYPE_ARM,
- HDR_CPU_TYPE_SPARC = CPU_TYPE_SPARC,
- HDR_CPU_TYPE_POWERPC = CPU_TYPE_POWERPC,
- HDR_CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC64
- };
-
-#if !defined(CPU_SUBTYPE_I386_ALL)
-#define CPU_SUBTYPE_I386_ALL 3
-#endif
-#if !defined(CPU_SUBTYPE_X86_64_ALL)
-#define CPU_SUBTYPE_X86_64_ALL 3
-#endif
-#if !defined(CPU_SUBTYPE_ARM_ALL)
-#define CPU_SUBTYPE_ARM_ALL0
-#endif
-#if !defined(CPU_SUBTYPE_SPARC_ALL)
-#define CPU_SUBTYPE_SPARC_ALL 0
-#endif
-#if !defined(CPU_SUBTYPE_POWERPC_ALL)
-#define CPU_SUBTYPE_POWERPC_ALL0
-
-#endif
- // Constants for the cpusubtype field
- // see mach/machine.h
- enum { HDR_CPU_SUBTYPE_I386_ALL = CPU_SUBTYPE_I386_ALL,
- HDR_CPU_SUBTYPE_X86_64_ALL = CPU_SUBTYPE_X86_64_ALL,
- HDR_CPU_SUBTYPE_ARM_ALL = CPU_SUBTYPE_ARM_ALL,
- HDR_CPU_SUBTYPE_SPARC_ALL = CPU_SUBTYPE_SPARC_ALL,
- HDR_CPU_SUBTYPE_POWERPC_ALL = CPU_SUBTYPE_POWERPC_ALL
- };
-
// Constants for the filetype field
// see mach-o/loader.h for additional info on the various types
enum { MH_OBJECT = 1, // relocatable object file
@@ -261,8 +204,8 @@
// stack execution privilege. Only used in MH_EXECUTE filetype
};
- MachOHeader() : magic(0), cputype(0), cpusubtype(0), filetype(0),
- ncmds(0), sizeofcmds(0), flags(0), reserved(0) { }
+ MachOHeader() : magic(0), filetype(0), ncmds(0), sizeofcmds(0), flags(0),
+ reserved(0) { }
/// cmdSize - This routine returns the size of the MachOSection as
written
/// to disk, depending on whether the destination is a 64 bit Mach-O
file.
@@ -671,8 +614,10 @@
void BufferSymbolAndStringTable();
void CalculateRelocations(MachOSection MOS);
-virtual MachineRelocation GetJTRelocation(unsigned Offset,
- MachineBasicBlock *MBB) = 0;
+MachineRelocation GetJTRelocation(unsigned Offset,
+ MachineBasicBlock *MBB) const {
+ return TM.getMachOWriterInfo()-GetJTRelocation(Offset, MBB);
+}
virtual void GetTargetRelocation(MachineRelocation MR, MachOSection From,
MachOSection To) = 0;
};
___
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h
Changes in directory llvm/include/llvm/Target:
TargetMachine.h updated: 1.73 - 1.74
---
Log message:
A virtual method to return the TargetMachOWriterInfo object. This returns
a real value in derived classes, of course.
---
Diffs of the changes: (+6 -0)
TargetMachine.h |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.73
llvm/include/llvm/Target/TargetMachine.h:1.74
--- llvm/include/llvm/Target/TargetMachine.h:1.73 Wed Jan 17 03:06:13 2007
+++ llvm/include/llvm/Target/TargetMachine.hTue Jan 23 21:38:14 2007
@@ -34,6 +34,7 @@
class FunctionPassManager;
class PassManager;
class Pass;
+struct TargetMachOWriterInfo;
// Relocation model types.
namespace Reloc {
@@ -143,6 +144,11 @@
return InstrItineraryData();
}
+ /// getMachOWriterInfo - If this target supports a Mach-O writer, return
+ /// information for it, otherwise return null.
+ ///
+ virtual const TargetMachOWriterInfo *getMachOWriterInfo() const { return 0; }
+
/// getRelocationModel - Returns the code generation relocation model. The
/// choices are static, PIC, and dynamic-no-pic, and target default.
static Reloc::Model getRelocationModel();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/MachOWriter.cpp
Changes in directory llvm/lib/CodeGen: MachOWriter.cpp updated: 1.17 - 1.18 --- Log message: Use the TargetMachOWriterInfo class to get this information. --- Diffs of the changes: (+2 -2) MachOWriter.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/MachOWriter.cpp diff -u llvm/lib/CodeGen/MachOWriter.cpp:1.17 llvm/lib/CodeGen/MachOWriter.cpp:1.18 --- llvm/lib/CodeGen/MachOWriter.cpp:1.17 Sat Jan 20 16:35:55 2007 +++ llvm/lib/CodeGen/MachOWriter.cppTue Jan 23 21:38:47 2007 @@ -461,8 +461,8 @@ OutputBuffer FHOut(FH, is64Bit, isLittleEndian); FHOut.outword(Header.magic); - FHOut.outword(Header.cputype); - FHOut.outword(Header.cpusubtype); + FHOut.outword(TM.getMachOWriterInfo()-CPUType); + FHOut.outword(TM.getMachOWriterInfo()-CPUSubType); FHOut.outword(Header.filetype); FHOut.outword(Header.ncmds); FHOut.outword(Header.sizeofcmds); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCMachOWriter.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCMachOWriter.cpp updated: 1.13 - 1.14
---
Log message:
Move the getJTRelocation method out of here.
---
Diffs of the changes: (+7 -26)
PPCMachOWriter.cpp | 33 +++--
1 files changed, 7 insertions(+), 26 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCMachOWriter.cpp
diff -u llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.13
llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.14
--- llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.13 Wed Jan 17 19:23:11 2007
+++ llvm/lib/Target/PowerPC/PPCMachOWriter.cpp Tue Jan 23 21:40:33 2007
@@ -23,23 +23,11 @@
namespace {
class VISIBILITY_HIDDEN PPCMachOWriter : public MachOWriter {
public:
-PPCMachOWriter(std::ostream O, PPCTargetMachine TM) : MachOWriter(O, TM)
{
- if (TM.getTargetData()-getPointerSizeInBits() == 64) {
-Header.cputype = MachOHeader::HDR_CPU_TYPE_POWERPC64;
- } else {
-Header.cputype = MachOHeader::HDR_CPU_TYPE_POWERPC;
- }
- Header.cpusubtype = MachOHeader::HDR_CPU_SUBTYPE_POWERPC_ALL;
-}
+PPCMachOWriter(std::ostream O, PPCTargetMachine TM)
+ : MachOWriter(O, TM) {}
virtual void GetTargetRelocation(MachineRelocation MR, MachOSection From,
MachOSection To);
-virtual MachineRelocation GetJTRelocation(unsigned Offset,
- MachineBasicBlock *MBB);
-
-virtual const char *getPassName() const {
- return PowerPC Mach-O Writer;
-}
// Constants for the relocation r_type field.
// see mach-o/ppc/reloc.h
@@ -67,20 +55,20 @@
/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
/// more PowerPC MachORelocation(s), add the new relocations to the
-/// MachOSection, and rewrite the instruction at the section offset if
required
+/// MachOSection, and rewrite the instruction at the section offset if required
/// by that relocation type.
void PPCMachOWriter::GetTargetRelocation(MachineRelocation MR,
MachOSection From,
MachOSection To) {
uint64_t Addr = 0;
-
+
// Keep track of whether or not this is an externally defined relocation.
bool isExtern = false;
-
+
// Get the address of whatever it is we're relocating, if possible.
if (!isExtern)
Addr = (uintptr_t)MR.getResultPointer() + To.addr;
-
+
switch ((PPC::RelocationType)MR.getRelocationType()) {
default: assert(0 Unknown PPC relocation type!);
case PPC::reloc_absolute_low_ix:
@@ -89,7 +77,7 @@
case PPC::reloc_vanilla:
{
// FIXME: need to handle 64 bit vanilla relocs
- MachORelocation VANILLA(MR.getMachineCodeOffset(), To.Index, false, 2,
+ MachORelocation VANILLA(MR.getMachineCodeOffset(), To.Index, false, 2,
isExtern, PPC_RELOC_VANILLA);
++From.nreloc;
@@ -165,10 +153,3 @@
}
}
}
-
-MachineRelocation PPCMachOWriter::GetJTRelocation(unsigned Offset,
- MachineBasicBlock *MBB) {
- // FIXME: do something about PIC
- return MachineRelocation::getBB(Offset, PPC::reloc_vanilla, MBB);
-}
-
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp PPCTargetMachine.h
Changes in directory llvm/lib/Target/PowerPC:
PPCTargetMachine.cpp updated: 1.114 - 1.115
PPCTargetMachine.h updated: 1.27 - 1.28
---
Log message:
Add a field for and construction of the PPCMachOWriterInfo object.
---
Diffs of the changes: (+7 -2)
PPCTargetMachine.cpp |2 +-
PPCTargetMachine.h |7 ++-
2 files changed, 7 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.114
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.115
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.114 Wed Jan 17 03:06:13 2007
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cppTue Jan 23 21:41:36 2007
@@ -87,7 +87,7 @@
: Subtarget(*this, M, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
-InstrItins(Subtarget.getInstrItineraryData()) {
+InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
if (getRelocationModel() == Reloc::Default)
if (Subtarget.isDarwin())
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.27
llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.28
--- llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.27 Wed Jan 17 03:06:13 2007
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.h Tue Jan 23 21:41:36 2007
@@ -19,6 +19,7 @@
#include PPCJITInfo.h
#include PPCInstrInfo.h
#include PPCISelLowering.h
+#include PPCMachOWriterInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetData.h
@@ -36,7 +37,8 @@
PPCJITInfo JITInfo;
PPCTargetLowering TLInfo;
InstrItineraryData InstrItins;
-
+ PPCMachOWriterInfo MachOWriterInfo;
+
protected:
virtual const TargetAsmInfo *createTargetAsmInfo() const;
@@ -58,6 +60,9 @@
virtual const InstrItineraryData getInstrItineraryData() const {
return InstrItins;
}
+ virtual const PPCMachOWriterInfo *getMachOWriterInfo() const {
+return MachOWriterInfo;
+ }
// Pass Pipeline Configuration
virtual bool addInstSelector(FunctionPassManager PM, bool Fast);
___
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[llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
Changes in directory llvm/Xcode/LLVM.xcodeproj:
project.pbxproj updated: 1.28 - 1.29
---
Log message:
Added new files.
---
Diffs of the changes: (+11 -0)
project.pbxproj | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.28
llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.29
--- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.28 Mon Jan 22 08:13:45 2007
+++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj Tue Jan 23 21:42:03 2007
@@ -65,6 +65,10 @@
/* End PBXContainerItemProxy section */
/* Begin PBXFileReference section */
+ 84115FFE0B66D87400E1293E /* TargetMachOWriterInfo.cpp */ = {isa
= PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp;
path = TargetMachOWriterInfo.cpp; sourceTree = group; };
+ 84115FFF0B66D89B00E1293E /* PPCMachOWriterInfo.cpp */ = {isa =
PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp;
path = PPCMachOWriterInfo.cpp; sourceTree = group; };
+ 84116B66D8AC00E1293E /* PPCMachOWriterInfo.h */ = {isa =
PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path =
PPCMachOWriterInfo.h; sourceTree = group; };
+ 8443EF210B66B62D00959964 /* TargetMachOWriterInfo.h */ = {isa =
PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path =
TargetMachOWriterInfo.h; sourceTree = group; };
CF1ACC9709C9DE4400D3C5EB /* IntrinsicInst.cpp */ = {isa =
PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp;
name = IntrinsicInst.cpp; path = ../lib/VMCore/IntrinsicInst.cpp; sourceTree =
group; };
CF26835B09178F5500C5F253 /* TargetInstrItineraries.h */ = {isa
= PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path
= TargetInstrItineraries.h; sourceTree = group; };
CF32AF5C0AEE6A4E00D24CD4 /* LLVMTargetMachine.cpp */ = {isa =
PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp;
path = LLVMTargetMachine.cpp; sourceTree = group; };
@@ -1479,6 +1483,7 @@
DE66EE9608ABEE5D00323D32 /* lib/Target */ = {
isa = PBXGroup;
children = (
+ 84115FFE0B66D87400E1293E /*
TargetMachOWriterInfo.cpp */,
DE66EE9708ABEE5D00323D32 /* Alpha */,
CF8F1BCF0B64FC8A00BB4199 /* ARM */,
DE66EEC908ABEE5E00323D32 /* CBackend */,
@@ -1592,6 +1597,8 @@
DE66EF1108ABEE5E00323D32 /* PowerPC */ = {
isa = PBXGroup;
children = (
+ 84116B66D8AC00E1293E /*
PPCMachOWriterInfo.h */,
+ 84115FFF0B66D89B00E1293E /*
PPCMachOWriterInfo.cpp */,
CFA702CB0A6FA8AD0006009A /* PPCGenAsmWriter.inc
*/,
CFA702CC0A6FA8AD0006009A /*
PPCGenCodeEmitter.inc */,
CFA702CD0A6FA8AD0006009A /* PPCGenDAGISel.inc
*/,
@@ -2151,6 +2158,7 @@
DE66F29F08ABF03200323D32 /* Target */ = {
isa = PBXGroup;
children = (
+ 8443EF210B66B62D00959964 /*
TargetMachOWriterInfo.h */,
DE66F2A008ABF03200323D32 /* MRegisterInfo.h */,
CF9BCD0808C74DE0001E7011 /* SubtargetFeature.h
*/,
CF47BD380AAF40BC00A8B13E /* TargetAsmInfo.h */,
@@ -2535,9 +2543,12 @@
08FB7793FE84155DC02AAC07 /* Project object */ = {
isa = PBXProject;
buildConfigurationList = DE66EC5008ABE78900323D32 /*
Build configuration list for PBXProject LLVM */;
+ compatibilityVersion = Xcode 2.4;
hasScannedForEncodings = 1;
mainGroup = 08FB7794FE84155DC02AAC07 /* LLVM */;
projectDirPath = ;
+ projectRoot = ;
+ shouldCheckCompatibility = 1;
targets = (
D28A88AD04BDD90700651E21 /* LLVM */,
CF0329B608D1BE110030FD33 /* LLVM lib */,
___
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[llvm-commits] CVS: llvm/lib/CodeGen/MachOWriter.cpp
Changes in directory llvm/lib/CodeGen: MachOWriter.cpp updated: 1.18 - 1.19 --- Log message: Make ivars private and use getters. Have the MachOWriter return Mach-O Writer for the pass name. --- Diffs of the changes: (+2 -2) MachOWriter.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/MachOWriter.cpp diff -u llvm/lib/CodeGen/MachOWriter.cpp:1.18 llvm/lib/CodeGen/MachOWriter.cpp:1.19 --- llvm/lib/CodeGen/MachOWriter.cpp:1.18 Tue Jan 23 21:38:47 2007 +++ llvm/lib/CodeGen/MachOWriter.cppWed Jan 24 01:13:56 2007 @@ -461,8 +461,8 @@ OutputBuffer FHOut(FH, is64Bit, isLittleEndian); FHOut.outword(Header.magic); - FHOut.outword(TM.getMachOWriterInfo()-CPUType); - FHOut.outword(TM.getMachOWriterInfo()-CPUSubType); + FHOut.outword(TM.getMachOWriterInfo()-getCPUType()); + FHOut.outword(TM.getMachOWriterInfo()-getCPUSubType()); FHOut.outword(Header.filetype); FHOut.outword(Header.ncmds); FHOut.outword(Header.sizeofcmds); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachOWriter.h
Changes in directory llvm/include/llvm/CodeGen:
MachOWriter.h updated: 1.15 - 1.16
---
Log message:
Make ivars private and use getters. Have the MachOWriter return Mach-O
Writer for the pass name.
---
Diffs of the changes: (+4 -2)
MachOWriter.h |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/CodeGen/MachOWriter.h
diff -u llvm/include/llvm/CodeGen/MachOWriter.h:1.15
llvm/include/llvm/CodeGen/MachOWriter.h:1.16
--- llvm/include/llvm/CodeGen/MachOWriter.h:1.15Tue Jan 23 21:37:18 2007
+++ llvm/include/llvm/CodeGen/MachOWriter.h Wed Jan 24 01:13:55 2007
@@ -85,11 +85,13 @@
MachineCodeEmitter getMachineCodeEmitter() const {
return *(MachineCodeEmitter*)MCE;
}
+virtual ~MachOWriter();
-~MachOWriter();
+virtual const char *getPassName() const {
+ return Mach-O Writer;
+}
typedef std::vectorunsigned char DataBuffer;
-
protected:
MachOWriter(std::ostream O, TargetMachine TM);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCMachOWriterInfo.h updated: 1.1 - 1.2
---
Log message:
Make ivars private and use getters. Have the MachOWriter return Mach-O
Writer for the pass name.
---
Diffs of the changes: (+2 -5)
PPCMachOWriterInfo.h |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h:1.1
llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h:1.2
--- llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h:1.1Tue Jan 23 21:36:05 2007
+++ llvm/lib/Target/PowerPC/PPCMachOWriterInfo.hWed Jan 24 01:13:56 2007
@@ -21,13 +21,10 @@
// Forward declarations
class PPCTargetMachine;
- struct PPCMachOWriterInfo : public TargetMachOWriterInfo {
+ class PPCMachOWriterInfo : public TargetMachOWriterInfo {
+ public:
PPCMachOWriterInfo(const PPCTargetMachine TM);
virtual ~PPCMachOWriterInfo() {}
-
-virtual const char *getPassName() const {
- return PowerPC Mach-O Writer;
-}
};
} // end llvm namespace
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachOWriterInfo.h
Changes in directory llvm/include/llvm/Target:
TargetMachOWriterInfo.h updated: 1.1 - 1.2
---
Log message:
Make ivars private and use getters. Have the MachOWriter return Mach-O
Writer for the pass name.
---
Diffs of the changes: (+4 -5)
TargetMachOWriterInfo.h |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
Index: llvm/include/llvm/Target/TargetMachOWriterInfo.h
diff -u llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.1
llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.2
--- llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.1Tue Jan 23
21:36:05 2007
+++ llvm/include/llvm/Target/TargetMachOWriterInfo.hWed Jan 24 01:13:55 2007
@@ -24,10 +24,10 @@
//TargetMachOWriterInfo
//======//
- struct TargetMachOWriterInfo {
+ class TargetMachOWriterInfo {
uint32_t CPUType; // CPU specifier
uint32_t CPUSubType; // Machine specifier
-
+ public:
// The various CPU_TYPE_* constants are already defined by at least one
// system header file and create compilation errors if not respected.
#if !defined(CPU_TYPE_I386)
@@ -93,9 +93,8 @@
virtual MachineRelocation GetJTRelocation(unsigned Offset,
MachineBasicBlock *MBB) const;
-virtual const char *getPassName() const {
- return Mach-O Writer;
-}
+uint32_t getCPUType() const { return CPUType; }
+uint32_t getCPUSubType() const { return CPUSubType; }
};
} // end llvm namespace
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetELFWriterInfo.h
Changes in directory llvm/include/llvm/Target:
TargetELFWriterInfo.h added (r1.1)
---
Log message:
The TargetELFWriterInfo class holds target-specific information for the ELF
writer.
---
Diffs of the changes: (+43 -0)
TargetELFWriterInfo.h | 43 +++
1 files changed, 43 insertions(+)
Index: llvm/include/llvm/Target/TargetELFWriterInfo.h
diff -c /dev/null llvm/include/llvm/Target/TargetELFWriterInfo.h:1.1
*** /dev/null Fri Jan 26 20:54:00 2007
--- llvm/include/llvm/Target/TargetELFWriterInfo.h Fri Jan 26 20:53:50 2007
***
*** 0
--- 1,43
+ //===-- llvm/Target/TargetELFWriterInfo.h - ELF Writer Info -*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Bill Wendling and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file defines the TargetELFWriterInfo class.
+ //
+
//===--===//
+
+ #ifndef LLVM_TARGET_TARGETELFWRITERINFO_H
+ #define LLVM_TARGET_TARGETELFWRITERINFO_H
+
+ namespace llvm {
+
+ class MachineBasicBlock;
+
+
//======//
+ // TargetELFWriterInfo
+
//======//
+
+ class TargetELFWriterInfo {
+ // EMachine - This field is the target specific value to emit as the
+ // e_machine member of the ELF header.
+ unsigned short EMachine;
+ public:
+ enum MachineType {
+ NoMachine,
+ EM_386 = 3
+ };
+
+ TargetELFWriterInfo(MachineType machine) : EMachine(machine) {}
+ virtual ~TargetELFWriterInfo() {}
+
+ unsigned short getEMachine() const { return EMachine; }
+ };
+
+ } // end llvm namespace
+
+ #endif // LLVM_TARGET_TARGETELFWRITERINFO_H
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ELFWriterInfo.cpp X86ELFWriterInfo.h
Changes in directory llvm/lib/Target/X86:
X86ELFWriterInfo.cpp added (r1.1)
X86ELFWriterInfo.h added (r1.1)
---
Log message:
X86 implementation of the TargetELFWriterInfo class.
---
Diffs of the changes: (+46 -0)
X86ELFWriterInfo.cpp | 17 +
X86ELFWriterInfo.h | 29 +
2 files changed, 46 insertions(+)
Index: llvm/lib/Target/X86/X86ELFWriterInfo.cpp
diff -c /dev/null llvm/lib/Target/X86/X86ELFWriterInfo.cpp:1.1
*** /dev/null Fri Jan 26 20:54:40 2007
--- llvm/lib/Target/X86/X86ELFWriterInfo.cppFri Jan 26 20:54:30 2007
***
*** 0
--- 1,17
+ //===-- X86ELFWriterInfo.cpp - ELF Writer Info for the X86 backend
===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Bill Wendling and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file implements ELF writer information for the X86 backend.
+ //
+
//===--===//
+
+ #include X86ELFWriterInfo.h
+ using namespace llvm;
+
+ X86ELFWriterInfo::X86ELFWriterInfo() : TargetELFWriterInfo(EM_386) {}
Index: llvm/lib/Target/X86/X86ELFWriterInfo.h
diff -c /dev/null llvm/lib/Target/X86/X86ELFWriterInfo.h:1.1
*** /dev/null Fri Jan 26 20:54:45 2007
--- llvm/lib/Target/X86/X86ELFWriterInfo.h Fri Jan 26 20:54:30 2007
***
*** 0
--- 1,29
+ //===-- X86ELFWriterInfo.h - ELF Writer Info for X86 *- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Bill Wendling and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file implements ELF writer information for the X86 backend.
+ //
+
//===--===//
+
+ #ifndef X86_ELF_WRITER_INFO_H
+ #define X86_ELF_WRITER_INFO_H
+
+ #include llvm/Target/TargetELFWriterInfo.h
+
+ namespace llvm {
+
+ class X86ELFWriterInfo : public TargetELFWriterInfo {
+ public:
+ X86ELFWriterInfo();
+ virtual ~X86ELFWriterInfo() {}
+ };
+
+ } // end llvm namespace
+
+ #endif // X86_ELF_WRITER_INFO_H
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h
Changes in directory llvm/include/llvm/Target:
TargetMachine.h updated: 1.74 - 1.75
---
Log message:
Accessor for the TargetELFWriterInfo class object.
---
Diffs of the changes: (+7 -1)
TargetMachine.h |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.74
llvm/include/llvm/Target/TargetMachine.h:1.75
--- llvm/include/llvm/Target/TargetMachine.h:1.74 Tue Jan 23 21:38:14 2007
+++ llvm/include/llvm/Target/TargetMachine.hFri Jan 26 20:55:04 2007
@@ -34,7 +34,8 @@
class FunctionPassManager;
class PassManager;
class Pass;
-struct TargetMachOWriterInfo;
+class TargetMachOWriterInfo;
+class TargetELFWriterInfo;
// Relocation model types.
namespace Reloc {
@@ -149,6 +150,11 @@
///
virtual const TargetMachOWriterInfo *getMachOWriterInfo() const { return 0; }
+ /// getELFWriterInfo - If this target supports an ELF writer, return
+ /// information for it, otherwise return null.
+ ///
+ virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
+
/// getRelocationModel - Returns the code generation relocation model. The
/// choices are static, PIC, and dynamic-no-pic, and target default.
static Reloc::Model getRelocationModel();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp
Changes in directory llvm/lib/CodeGen:
ELFWriter.cpp updated: 1.35 - 1.36
---
Log message:
Use TargetELFWriterInfo class.
---
Diffs of the changes: (+2 -2)
ELFWriter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/ELFWriter.cpp
diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.35 llvm/lib/CodeGen/ELFWriter.cpp:1.36
--- llvm/lib/CodeGen/ELFWriter.cpp:1.35 Sat Jan 20 16:35:55 2007
+++ llvm/lib/CodeGen/ELFWriter.cpp Fri Jan 26 20:55:44 2007
@@ -36,6 +36,7 @@
#include llvm/CodeGen/MachineCodeEmitter.h
#include llvm/CodeGen/MachineConstantPool.h
#include llvm/Target/TargetData.h
+#include llvm/Target/TargetELFWriterInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Support/Mangler.h
#include llvm/Support/OutputBuffer.h
@@ -162,7 +163,6 @@
//===--===//
ELFWriter::ELFWriter(std::ostream o, TargetMachine tm) : O(o), TM(tm) {
- e_machine = 0; // e_machine defaults to 'No Machine'
e_flags = 0;// e_flags defaults to 0, no flags.
is64Bit = TM.getTargetData()-getPointerSizeInBits() == 64;
@@ -197,7 +197,7 @@
// This should change for shared objects.
FHOut.outhalf(1); // e_type = ET_REL
- FHOut.outhalf(e_machine); // e_machine = whatever the target wants
+ FHOut.outword(TM.getELFWriterInfo()-getEMachine()); // target-defined
FHOut.outword(1); // e_version = 1
FHOut.outaddr(0); // e_entry = 0 - no entry point in .o file
FHOut.outaddr(0); // e_phoff = 0 - no program header for .o
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[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.h
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.h updated: 1.43 - 1.44
---
Log message:
Return an X86ELFWriterInfo object.
---
Diffs of the changes: (+6 -1)
X86TargetMachine.h |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86TargetMachine.h
diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.43
llvm/lib/Target/X86/X86TargetMachine.h:1.44
--- llvm/lib/Target/X86/X86TargetMachine.h:1.43 Wed Jan 17 03:06:13 2007
+++ llvm/lib/Target/X86/X86TargetMachine.h Fri Jan 26 20:56:16 2007
@@ -18,6 +18,7 @@
#include llvm/Target/TargetData.h
#include llvm/Target/TargetFrameInfo.h
#include X86.h
+#include X86ELFWriterInfo.h
#include X86InstrInfo.h
#include X86JITInfo.h
#include X86Subtarget.h
@@ -27,11 +28,12 @@
class X86TargetMachine : public LLVMTargetMachine {
X86Subtarget Subtarget;
- const TargetData DataLayout; // Calculates type size alignment
+ const TargetData DataLayout; // Calculates type size alignment
TargetFrameInfo FrameInfo;
X86InstrInfo InstrInfo;
X86JITInfoJITInfo;
X86TargetLowering TLInfo;
+ X86ELFWriterInfo ELFWriterInfo;
protected:
virtual const TargetAsmInfo *createTargetAsmInfo() const;
@@ -50,6 +52,9 @@
return InstrInfo.getRegisterInfo();
}
virtual const TargetData *getTargetData() const { return DataLayout; }
+ virtual const X86ELFWriterInfo *getELFWriterInfo() const {
+return ELFWriterInfo;
+ }
static unsigned getModuleMatchQuality(const Module M);
static unsigned getJITMatchQuality();
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ELFWriterInfo.cpp X86ELFWriterInfo.h
Changes in directory llvm/lib/Target/X86:
X86ELFWriterInfo.cpp updated: 1.1 - 1.2
X86ELFWriterInfo.h updated: 1.1 - 1.2
---
Log message:
Make d'tor out-of-line.
---
Diffs of the changes: (+2 -1)
X86ELFWriterInfo.cpp |1 +
X86ELFWriterInfo.h |2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ELFWriterInfo.cpp
diff -u llvm/lib/Target/X86/X86ELFWriterInfo.cpp:1.1
llvm/lib/Target/X86/X86ELFWriterInfo.cpp:1.2
--- llvm/lib/Target/X86/X86ELFWriterInfo.cpp:1.1Fri Jan 26 20:54:30 2007
+++ llvm/lib/Target/X86/X86ELFWriterInfo.cppSat Jan 27 05:40:32 2007
@@ -15,3 +15,4 @@
using namespace llvm;
X86ELFWriterInfo::X86ELFWriterInfo() : TargetELFWriterInfo(EM_386) {}
+X86ELFWriterInfo::~X86ELFWriterInfo() {}
Index: llvm/lib/Target/X86/X86ELFWriterInfo.h
diff -u llvm/lib/Target/X86/X86ELFWriterInfo.h:1.1
llvm/lib/Target/X86/X86ELFWriterInfo.h:1.2
--- llvm/lib/Target/X86/X86ELFWriterInfo.h:1.1 Fri Jan 26 20:54:30 2007
+++ llvm/lib/Target/X86/X86ELFWriterInfo.h Sat Jan 27 05:40:32 2007
@@ -21,7 +21,7 @@
class X86ELFWriterInfo : public TargetELFWriterInfo {
public:
X86ELFWriterInfo();
-virtual ~X86ELFWriterInfo() {}
+virtual ~X86ELFWriterInfo();
};
} // end llvm namespace
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachORelocation.h
Changes in directory llvm/include/llvm/CodeGen:
MachORelocation.h added (r1.1)
---
Log message:
New file for the MachORelocation structure. It doesn't have to be tied to the
MachOWriter.h file.
---
Diffs of the changes: (+54 -0)
MachORelocation.h | 54 ++
1 files changed, 54 insertions(+)
Index: llvm/include/llvm/CodeGen/MachORelocation.h
diff -c /dev/null llvm/include/llvm/CodeGen/MachORelocation.h:1.1
*** /dev/null Fri Feb 2 20:36:27 2007
--- llvm/include/llvm/CodeGen/MachORelocation.h Fri Feb 2 20:36:17 2007
***
*** 0
--- 1,54
+ //=== MachORelocation.h - Mach-O Relocation Info *- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Bill Wendling and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file defines the MachORelocation class.
+ //
+
//===--===//
+
+
+ #ifndef LLVM_CODEGEN_MACHO_RELOCATION_H
+ #define LLVM_CODEGEN_MACHO_RELOCATION_H
+
+ namespace llvm {
+
+ /// MachORelocation - This struct contains information about each relocation
+ /// that needs to be emitted to the file.
+ /// see mach-o/reloc.h
+ class MachORelocation {
+ uint32_t r_address; // offset in the section to what is being relocated
+ uint32_t r_symbolnum; // symbol index if r_extern == 1 else section index
+ bool r_pcrel; // was relocated pc-relative already
+ uint8_t r_length;// length = 2 ^ r_length
+ bool r_extern;//
+ uint8_t r_type; // if not 0, machine-specific relocation type.
+ bool r_scattered; // 1 = scattered, 0 = non-scattered
+ int32_t r_value; // the value the item to be relocated is referring
+ // to.
+ public:
+ uint32_t getPackedFields() const {
+ if (r_scattered)
+ return (1 31) | (r_pcrel 30) | ((r_length 3) 28) |
+ ((r_type 15) 24) | (r_address 0x00FF);
+ else
+ return (r_symbolnum 8) | (r_pcrel 7) | ((r_length 3) 5) |
+ (r_extern 4) | (r_type 15);
+ }
+ uint32_t getAddress() const { return r_scattered ? r_value : r_address; }
+ uint32_t getRawAddress() const { return r_address; }
+
+ MachORelocation(uint32_t addr, uint32_t index, bool pcrel, uint8_t len,
+ bool ext, uint8_t type, bool scattered = false,
+ int32_t value = 0) :
+ r_address(addr), r_symbolnum(index), r_pcrel(pcrel), r_length(len),
+ r_extern(ext), r_type(type), r_scattered(scattered), r_value(value) {}
+ };
+
+ } // end llvm namespace
+
+ #endif // LLVM_CODEGEN_MACHO_RELOCATION_H
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[llvm-commits] CVS: llvm/include/llvm/Support/OutputBuffer.h
Changes in directory llvm/include/llvm/Support:
OutputBuffer.h updated: 1.2 - 1.3
---
Log message:
Added some accessor methods.
---
Diffs of the changes: (+9 -0)
OutputBuffer.h |9 +
1 files changed, 9 insertions(+)
Index: llvm/include/llvm/Support/OutputBuffer.h
diff -u llvm/include/llvm/Support/OutputBuffer.h:1.2
llvm/include/llvm/Support/OutputBuffer.h:1.3
--- llvm/include/llvm/Support/OutputBuffer.h:1.2Wed Jan 17 19:23:11 2007
+++ llvm/include/llvm/Support/OutputBuffer.hFri Feb 2 20:38:15 2007
@@ -138,6 +138,15 @@
else
assert(0 Emission of 64-bit data not implemented yet!);
}
+
+std::vectorunsigned char::reference
+operator [] (unsigned Index) {
+ return Output[Index];
+}
+std::vectorunsigned char::const_reference
+operator [] (unsigned Index) const {
+ return Output[Index];
+}
};
} // end llvm namespace
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachOWriterInfo.h
Changes in directory llvm/include/llvm/Target:
TargetMachOWriterInfo.h updated: 1.2 - 1.3
---
Log message:
Added GetTargetRelocation method.
---
Diffs of the changes: (+10 -1)
TargetMachOWriterInfo.h | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetMachOWriterInfo.h
diff -u llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.2
llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.3
--- llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.2Wed Jan 24
01:13:55 2007
+++ llvm/include/llvm/Target/TargetMachOWriterInfo.hFri Feb 2 20:38:57 2007
@@ -19,6 +19,7 @@
namespace llvm {
class MachineBasicBlock;
+ class OutputBuffer;
//======//
//TargetMachOWriterInfo
@@ -88,11 +89,19 @@
TargetMachOWriterInfo(uint32_t cputype, uint32_t cpusubtype)
: CPUType(cputype), CPUSubType(cpusubtype) {}
-virtual ~TargetMachOWriterInfo() {}
+virtual ~TargetMachOWriterInfo();
virtual MachineRelocation GetJTRelocation(unsigned Offset,
MachineBasicBlock *MBB) const;
+virtual unsigned GetTargetRelocation(MachineRelocation MR,
+ unsigned FromIdx,
+ unsigned ToAddr,
+ unsigned ToIdx,
+ OutputBuffer RelocOut,
+ OutputBuffer SecOut,
+ bool Scattered) const { return 0; }
+
uint32_t getCPUType() const { return CPUType; }
uint32_t getCPUSubType() const { return CPUSubType; }
};
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[llvm-commits] CVS: llvm/lib/Target/TargetMachOWriterInfo.cpp
Changes in directory llvm/lib/Target:
TargetMachOWriterInfo.cpp updated: 1.1 - 1.2
---
Log message:
Put destructor out-of-line.
---
Diffs of the changes: (+2 -0)
TargetMachOWriterInfo.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/TargetMachOWriterInfo.cpp
diff -u llvm/lib/Target/TargetMachOWriterInfo.cpp:1.1
llvm/lib/Target/TargetMachOWriterInfo.cpp:1.2
--- llvm/lib/Target/TargetMachOWriterInfo.cpp:1.1 Tue Jan 23 21:36:05 2007
+++ llvm/lib/Target/TargetMachOWriterInfo.cpp Fri Feb 2 20:40:10 2007
@@ -15,6 +15,8 @@
#include llvm/CodeGen/MachineRelocation.h
using namespace llvm;
+TargetMachOWriterInfo::~TargetMachOWriterInfo() {}
+
MachineRelocation
TargetMachOWriterInfo::GetJTRelocation(unsigned Offset,
MachineBasicBlock *MBB) const {
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCMachOWriter.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCMachOWriter.cpp updated: 1.15 - 1.16
---
Log message:
Moved the GetTargetRelocation method to the PPCMachOWriterInfo object. The
PPCMachOWriter is now trivial.
---
Diffs of the changes: (+1 -131)
PPCMachOWriter.cpp | 132 -
1 files changed, 1 insertion(+), 131 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCMachOWriter.cpp
diff -u llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.15
llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.16
--- llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.15 Fri Jan 26 16:39:48 2007
+++ llvm/lib/Target/PowerPC/PPCMachOWriter.cpp Fri Feb 2 20:40:57 2007
@@ -12,35 +12,17 @@
//
//===--===//
-#include PPCRelocations.h
#include PPCTargetMachine.h
#include llvm/PassManager.h
#include llvm/CodeGen/MachOWriter.h
#include llvm/Support/Compiler.h
-#include llvm/Support/OutputBuffer.h
using namespace llvm;
namespace {
- class VISIBILITY_HIDDEN PPCMachOWriter : public MachOWriter {
- public:
+ struct VISIBILITY_HIDDEN PPCMachOWriter : public MachOWriter {
PPCMachOWriter(std::ostream O, PPCTargetMachine TM)
: MachOWriter(O, TM) {}
-
-virtual void GetTargetRelocation(MachineRelocation MR, MachOSection From,
- MachOSection To, bool Scattered);
-
-// Constants for the relocation r_type field.
-// see mach-o/ppc/reloc.h
-enum { PPC_RELOC_VANILLA, // generic relocation
- PPC_RELOC_PAIR,// the second relocation entry of a pair
- PPC_RELOC_BR14,// 14 bit branch displacement to word address
- PPC_RELOC_BR24,// 24 bit branch displacement to word address
- PPC_RELOC_HI16,// a PAIR follows with the low 16 bits
- PPC_RELOC_LO16,// a PAIR follows with the high 16 bits
- PPC_RELOC_HA16,// a PAIR follows, which is sign extended to 32b
- PPC_RELOC_LO14 // LO16 with low 2 bits implicitly zero
};
- };
}
/// addPPCMachOObjectWriterPass - Returns a pass that outputs the generated
code
@@ -52,115 +34,3 @@
FPM.add(MOW);
FPM.add(createPPCCodeEmitterPass(TM, MOW-getMachineCodeEmitter()));
}
-
-/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
-/// more PowerPC MachORelocation(s), add the new relocations to the
-/// MachOSection, and rewrite the instruction at the section offset if required
-/// by that relocation type.
-void PPCMachOWriter::GetTargetRelocation(MachineRelocation MR,
- MachOSection From,
- MachOSection To,
- bool Scattered) {
- uint64_t Addr = 0;
-
- // Keep track of whether or not this is an externally defined relocation.
- bool isExtern = false;
-
- // Get the address of whatever it is we're relocating, if possible.
- if (!isExtern)
-Addr = (uintptr_t)MR.getResultPointer() + To.addr;
-
- switch ((PPC::RelocationType)MR.getRelocationType()) {
- default: assert(0 Unknown PPC relocation type!);
- case PPC::reloc_absolute_low_ix:
-assert(0 Unhandled PPC relocation type!);
-break;
- case PPC::reloc_vanilla:
-{
- // FIXME: need to handle 64 bit vanilla relocs
- MachORelocation VANILLA(MR.getMachineCodeOffset(), To.Index, false, 2,
- isExtern, PPC_RELOC_VANILLA, Scattered,
- (intptr_t)MR.getResultPointer());
- ++From.nreloc;
- OutputBuffer RelocOut(From.RelocBuffer, is64Bit, isLittleEndian);
- OutputBuffer SecOut(From.SectionData, is64Bit, isLittleEndian);
-
- if (Scattered) {
-RelocOut.outword(VANILLA.getPackedFields());
-RelocOut.outword(VANILLA.getAddress());
- } else {
-RelocOut.outword(VANILLA.getAddress());
-RelocOut.outword(VANILLA.getPackedFields());
- }
-
- intptr_t SymbolOffset;
- if (Scattered)
-SymbolOffset = Addr + MR.getConstantVal();
- else
-SymbolOffset = Addr;
- printf(vanilla fixup: sec_%x[%x] = %x\n, From.Index,
unsigned(MR.getMachineCodeOffset()), (unsigned)SymbolOffset);
- SecOut.fixword(SymbolOffset, MR.getMachineCodeOffset());
-}
-break;
- case PPC::reloc_pcrel_bx:
-{
- Addr -= MR.getMachineCodeOffset();
- Addr = 2;
- Addr = 0xFF;
- Addr = 2;
- Addr |= (From.SectionData[MR.getMachineCodeOffset()] 24);
-
- OutputBuffer SecOut(From.SectionData, is64Bit, isLittleEndian);
- SecOut.fixword(Addr, MR.getMachineCodeOffset());
- break;
-}
- case PPC::reloc_pcrel_bcx:
-{
- Addr -= MR.getMachineCodeOffset();
- Addr = 0xFFFC;
-
- OutputBuffer SecOut(From.SectionData, is64Bit, isLittleEndian);
- SecOut.fixhalf(Addr, MR.getMachineCodeOffset() + 2);
- break;
-}
- case
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp PPCMachOWriterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCMachOWriterInfo.cpp updated: 1.1 - 1.2
PPCMachOWriterInfo.h updated: 1.2 - 1.3
---
Log message:
Moved the GetTargetRelocation method from PPCMachOWriter to here. It uses
non-Mach-O-specific information.
---
Diffs of the changes: (+143 -1)
PPCMachOWriterInfo.cpp | 119 +
PPCMachOWriterInfo.h | 25 +-
2 files changed, 143 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.1
llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.2
--- llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.1 Tue Jan 23 21:36:05 2007
+++ llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp Fri Feb 2 20:41:58 2007
@@ -12,7 +12,10 @@
//===--===//
#include PPCMachOWriterInfo.h
+#include PPCRelocations.h
#include PPCTargetMachine.h
+#include llvm/CodeGen/MachORelocation.h
+#include llvm/Support/OutputBuffer.h
using namespace llvm;
PPCMachOWriterInfo::PPCMachOWriterInfo(const PPCTargetMachine TM)
@@ -20,3 +23,119 @@
HDR_CPU_TYPE_POWERPC64 :
HDR_CPU_TYPE_POWERPC,
HDR_CPU_SUBTYPE_POWERPC_ALL) {}
+PPCMachOWriterInfo::~PPCMachOWriterInfo() {}
+
+
+/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
+/// more PowerPC MachORelocation(s), add the new relocations to the
+/// MachOSection, and rewrite the instruction at the section offset if required
+/// by that relocation type.
+unsigned PPCMachOWriterInfo::GetTargetRelocation(MachineRelocation MR,
+ unsigned FromIdx,
+ unsigned ToAddr,
+ unsigned ToIdx,
+ OutputBuffer RelocOut,
+ OutputBuffer SecOut,
+ bool Scattered) const {
+ unsigned NumRelocs = 0;
+ uint64_t Addr = 0;
+
+ // Keep track of whether or not this is an externally defined relocation.
+ bool isExtern = false;
+
+ // Get the address of whatever it is we're relocating, if possible.
+ if (!isExtern)
+Addr = (uintptr_t)MR.getResultPointer() + ToAddr;
+
+ switch ((PPC::RelocationType)MR.getRelocationType()) {
+ default: assert(0 Unknown PPC relocation type!);
+ case PPC::reloc_absolute_low_ix:
+assert(0 Unhandled PPC relocation type!);
+break;
+ case PPC::reloc_vanilla:
+{
+ // FIXME: need to handle 64 bit vanilla relocs
+ MachORelocation VANILLA(MR.getMachineCodeOffset(), ToIdx,
+ false, 2, isExtern,
+ PPC_RELOC_VANILLA,
+ Scattered, (intptr_t)MR.getResultPointer());
+ ++NumRelocs;
+
+ if (Scattered) {
+RelocOut.outword(VANILLA.getPackedFields());
+RelocOut.outword(VANILLA.getAddress());
+ } else {
+RelocOut.outword(VANILLA.getAddress());
+RelocOut.outword(VANILLA.getPackedFields());
+ }
+
+ intptr_t SymbolOffset;
+
+ if (Scattered)
+SymbolOffset = Addr + MR.getConstantVal();
+ else
+SymbolOffset = Addr;
+
+ printf(vanilla fixup: sec_%x[%x] = %x\n, FromIdx,
+ unsigned(MR.getMachineCodeOffset()),
+ unsigned(SymbolOffset));
+ SecOut.fixword(SymbolOffset, MR.getMachineCodeOffset());
+}
+break;
+ case PPC::reloc_pcrel_bx:
+{
+ Addr -= MR.getMachineCodeOffset();
+ Addr = 2;
+ Addr = 0xFF;
+ Addr = 2;
+ Addr |= (SecOut[MR.getMachineCodeOffset()] 24);
+
+ SecOut.fixword(Addr, MR.getMachineCodeOffset());
+ break;
+}
+ case PPC::reloc_pcrel_bcx:
+{
+ Addr -= MR.getMachineCodeOffset();
+ Addr = 0xFFFC;
+
+ SecOut.fixhalf(Addr, MR.getMachineCodeOffset() + 2);
+ break;
+}
+ case PPC::reloc_absolute_high:
+{
+ MachORelocation HA16(MR.getMachineCodeOffset(), ToIdx, false, 2,
+ isExtern, PPC_RELOC_HA16);
+ MachORelocation PAIR(Addr 0x, 0xFF, false, 2, isExtern,
+ PPC_RELOC_PAIR);
+ NumRelocs = 2;
+
+ RelocOut.outword(HA16.getRawAddress());
+ RelocOut.outword(HA16.getPackedFields());
+ RelocOut.outword(PAIR.getRawAddress());
+ RelocOut.outword(PAIR.getPackedFields());
+
+ Addr += 0x8000;
+
+ SecOut.fixhalf(Addr 16, MR.getMachineCodeOffset() + 2);
+ break;
+}
+ case PPC::reloc_absolute_low:
+{
+ MachORelocation LO16(MR.getMachineCodeOffset(), ToIdx, false, 2,
+ isExtern, PPC_RELOC_LO16);
+ MachORelocation PAIR(Addr 16, 0xFF, false, 2, isExtern,
+ PPC_RELOC_PAIR);
+
[llvm-commits] CVS: llvm/include/llvm/Support/OutputBuffer.h
Changes in directory llvm/include/llvm/Support:
OutputBuffer.h updated: 1.3 - 1.4
---
Log message:
Use unsigned char instead of std::vector::reference.
---
Diffs of the changes: (+2 -4)
OutputBuffer.h |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/Support/OutputBuffer.h
diff -u llvm/include/llvm/Support/OutputBuffer.h:1.3
llvm/include/llvm/Support/OutputBuffer.h:1.4
--- llvm/include/llvm/Support/OutputBuffer.h:1.3Fri Feb 2 20:38:15 2007
+++ llvm/include/llvm/Support/OutputBuffer.hSun Feb 4 20:37:07 2007
@@ -139,12 +139,10 @@
assert(0 Emission of 64-bit data not implemented yet!);
}
-std::vectorunsigned char::reference
-operator [] (unsigned Index) {
+unsigned char operator[](unsigned Index) {
return Output[Index];
}
-std::vectorunsigned char::const_reference
-operator [] (unsigned Index) const {
+const unsigned char operator[](unsigned Index) const {
return Output[Index];
}
};
___
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[llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.h MachOWriter.h
Changes in directory llvm/lib/CodeGen:
ELFWriter.h added (r1.1)
MachOWriter.h added (r1.1)
---
Log message:
Moved from include/llvm/CodeGen to lib/CodeGen.
---
Diffs of the changes: (+850 -0)
ELFWriter.h | 226 +
MachOWriter.h | 624 ++
2 files changed, 850 insertions(+)
Index: llvm/lib/CodeGen/ELFWriter.h
diff -c /dev/null llvm/lib/CodeGen/ELFWriter.h:1.1
*** /dev/null Wed Feb 7 19:31:00 2007
--- llvm/lib/CodeGen/ELFWriter.hWed Feb 7 19:30:50 2007
***
*** 0
--- 1,226
+ //===-- ELFWriter.h - Target-independent ELF writer support -*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file defines the ELFWriter class.
+ //
+
//===--===//
+
+ #ifndef ELFWRITER_H
+ #define ELFWRITER_H
+
+ #include llvm/CodeGen/MachineFunctionPass.h
+ #include list
+
+ namespace llvm {
+ class GlobalVariable;
+ class Mangler;
+ class MachineCodeEmitter;
+ class ELFCodeEmitter;
+
+ /// ELFWriter - This class implements the common target-independent code for
+ /// writing ELF files. Targets should derive a class from this to
+ /// parameterize the output format.
+ ///
+ class ELFWriter : public MachineFunctionPass {
+ friend class ELFCodeEmitter;
+ public:
+ MachineCodeEmitter getMachineCodeEmitter() const {
+ return *(MachineCodeEmitter*)MCE;
+ }
+
+ ELFWriter(std::ostream O, TargetMachine TM);
+ ~ELFWriter();
+
+ typedef std::vectorunsigned char DataBuffer;
+
+ protected:
+ /// Output stream to send the resultant object file to.
+ ///
+ std::ostream O;
+
+ /// Target machine description.
+ ///
+ TargetMachine TM;
+
+ /// Mang - The object used to perform name mangling for this module.
+ ///
+ Mangler *Mang;
+
+ /// MCE - The MachineCodeEmitter object that we are exposing to emit
machine
+ /// code for functions to the .o file.
+ ELFCodeEmitter *MCE;
+
+
//===--===//
+ // Properties to be set by the derived class ctor, used to configure the
+ // ELFWriter.
+
+ // e_machine - This field is the target specific value to emit as the
+ // e_machine member of the ELF header.
+ unsigned short e_machine;
+
+ // e_flags - The machine flags for the target. This defaults to zero.
+ unsigned e_flags;
+
+
//===--===//
+ // Properties inferred automatically from the target machine.
+ //
+
+ /// is64Bit/isLittleEndian - This information is inferred from the target
+ /// machine directly, indicating whether to emit a 32- or 64-bit ELF file.
+ bool is64Bit, isLittleEndian;
+
+ /// doInitialization - Emit the file header and all of the global
variables
+ /// for the module to the ELF file.
+ bool doInitialization(Module M);
+
+ bool runOnMachineFunction(MachineFunction MF);
+
+
+ /// doFinalization - Now that the module has been completely processed,
emit
+ /// the ELF file to 'O'.
+ bool doFinalization(Module M);
+
+ private:
+ // The buffer we accumulate the file header into. Note that this should
be
+ // changed into something much more efficient later (and the bytecode
writer
+ // as well!).
+ DataBuffer FileHeader;
+
+ /// ELFSection - This struct contains information about each section that
is
+ /// emitted to the file. This is eventually turned into the section
header
+ /// table at the end of the file.
+ struct ELFSection {
+ std::string Name; // Name of the section.
+ unsigned NameIdx; // Index in .shstrtab of name, once emitted.
+ unsigned Type;
+ unsigned Flags;
+ uint64_t Addr;
+ unsigned Offset;
+ unsigned Size;
+ unsigned Link;
+ unsigned Info;
+ unsigned Align;
+ unsigned EntSize;
+
+ /// SectionIdx - The number of the section in the Section Table.
+ ///
+ unsigned short SectionIdx;
+
+ /// SectionData - The actual data for this section which we are building
+ /// up for emission to the file.
+ DataBuffer SectionData;
+
+ enum { SHT_NULL = 0, SHT_PROGBITS = 1, SHT_SYMTAB = 2, SHT_STRTAB = 3,
+ SHT_RELA = 4, SHT_HASH = 5, SHT_DYNAMIC = 6, SHT_NOTE = 7,
+ SHT_NOBITS = 8, SHT_REL = 9, SHT_SHLIB = 10, SHT_DYNSYM = 11 };
+ enum { SHN_UNDEF = 0, SHN_ABS = 0xFFF1, SHN_COMMON = 0xFFF2 };
+ enum { // SHF - ELF Section Header Flags
[llvm-commits] CVS: llvm/include/llvm/CodeGen/FileWriters.h
Changes in directory llvm/include/llvm/CodeGen:
FileWriters.h added (r1.1)
---
Log message:
Declarations for functions that create different file writers.
---
Diffs of the changes: (+32 -0)
FileWriters.h | 32
1 files changed, 32 insertions(+)
Index: llvm/include/llvm/CodeGen/FileWriters.h
diff -c /dev/null llvm/include/llvm/CodeGen/FileWriters.h:1.1
*** /dev/null Wed Feb 7 19:31:48 2007
--- llvm/include/llvm/CodeGen/FileWriters.h Wed Feb 7 19:31:38 2007
***
*** 0
--- 1,32
+ //===-- FileWriters.cpp - File Writers Creation Functions ---*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Bill Wendling and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // Functions to add the various file writer passes.
+ //
+
//===--===//
+
+ #ifndef LLVM_CODEGEN_FILEWRITERS_H
+ #define LLVM_CODEGEN_FILEWRITERS_H
+
+ #include iosfwd
+
+ namespace llvm {
+
+ class FunctionPassManager;
+ class MachineCodeEmitter;
+ class TargetMachine;
+
+ MachineCodeEmitter *AddELFWriter(FunctionPassManager FPM, std::ostream O,
+TargetMachine TM);
+ MachineCodeEmitter *AddMachOWriter(FunctionPassManager FPM, std::ostream
O,
+ TargetMachine TM);
+
+ } // end llvm namespace
+
+ #endif // LLVM_CODEGEN_FILEWRITERS_H
___
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h
Changes in directory llvm/include/llvm/Target:
TargetMachine.h updated: 1.75 - 1.76
---
Log message:
Added new method to finish up the addition of passes to emit files. This
allows us to split that method into two so that we can optionally call a
concrete function to add a writer. Removed moribund addObjectWriter()
method.
---
Diffs of the changes: (+53 -24)
TargetMachine.h | 77 ++--
1 files changed, 53 insertions(+), 24 deletions(-)
Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.75
llvm/include/llvm/Target/TargetMachine.h:1.76
--- llvm/include/llvm/Target/TargetMachine.h:1.75 Fri Jan 26 20:55:04 2007
+++ llvm/include/llvm/Target/TargetMachine.hWed Feb 7 19:34:45 2007
@@ -58,6 +58,16 @@
};
}
+namespace FileModel {
+ enum Model {
+Error,
+None,
+AsmFile,
+MachOFile,
+ElfFile
+ };
+}
+
//===--===//
///
/// TargetMachine - Primary interface to the complete machine description for
@@ -175,14 +185,25 @@
AssemblyFile, ObjectFile, DynamicLibrary
};
- /// addPassesToEmitFile - Add passes to the specified pass manager to get
- /// the specified file emitted. Typically this will involve several steps of
- /// code generation. If Fast is set to true, the code generator should emit
- /// code as fast as possible, without regard for compile time. This method
- /// should return true if emission of this file type is not supported.
+ /// addPassesToEmitFile - Add passes to the specified pass manager to get the
+ /// specified file emitted. Typically this will involve several steps of
code
+ /// generation. If Fast is set to true, the code generator should emit code
+ /// as fast as possible, without regard for compile time. This method should
+ /// return FileModel::Error if emission of this file type is not supported.
+ ///
+ virtual FileModel::Model addPassesToEmitFile(FunctionPassManager PM,
+ std::ostream Out,
+ CodeGenFileType FileType,
+ bool Fast) {
+return FileModel::None;
+ }
+
+ /// addPassesToEmitFileFinish - If the passes to emit the specified file had
+ /// to be split up (e.g., to add an object writer pass), this method can be
+ /// used to finish up adding passes to emit the file, if necessary.
///
- virtual bool addPassesToEmitFile(FunctionPassManager PM, std::ostream Out,
- CodeGenFileType FileType, bool Fast) {
+ virtual bool addPassesToEmitFileFinish(FunctionPassManager PM,
+ MachineCodeEmitter *MCE, bool Fast) {
return true;
}
@@ -196,7 +217,6 @@
MachineCodeEmitter MCE, bool Fast) {
return true;
}
-
/// addPassesToEmitWholeFile - This method can be implemented by targets
that
/// require having the entire module at once. This is not recommended, do
not
@@ -216,19 +236,28 @@
LLVMTargetMachine() { }
public:
- /// addPassesToEmitFile - Add passes to the specified pass manager to get
- /// the specified file emitted. Typically this will involve several steps of
- /// code generation. If Fast is set to true, the code generator should emit
- /// code as fast as possible, without regard for compile time. This method
- /// should return true if emission of this file type is not supported.
+ /// addPassesToEmitFile - Add passes to the specified pass manager to get the
+ /// specified file emitted. Typically this will involve several steps of
code
+ /// generation. If Fast is set to true, the code generator should emit code
+ /// as fast as possible, without regard for compile time. This method should
+ /// return FileModel::Error if emission of this file type is not supported.
///
/// The default implementation of this method adds components from the
/// LLVM retargetable code generator, invoking the methods below to get
/// target-specific passes in standard locations.
///
- virtual bool addPassesToEmitFile(FunctionPassManager PM, std::ostream Out,
- CodeGenFileType FileType, bool Fast);
-
+ virtual FileModel::Model addPassesToEmitFile(FunctionPassManager PM,
+ std::ostream Out,
+ CodeGenFileType FileType,
+ bool Fast);
+
+ /// addPassesToEmitFileFinish - If the passes to emit the specified file had
+ /// to be split up (e.g., to add an object writer pass), this method can be
+ /// used to finish up adding passes to emit the file, if necessary.
+ ///
+ virtual bool addPassesToEmitFileFinish(FunctionPassManager PM,
+
[llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp MachOWriter.cpp
Changes in directory llvm/lib/CodeGen:
ELFWriter.cpp updated: 1.36 - 1.37
MachOWriter.cpp updated: 1.23 - 1.24
---
Log message:
Add function to create a file writer.
---
Diffs of the changes: (+28 -3)
ELFWriter.cpp | 16 +++-
MachOWriter.cpp | 15 +--
2 files changed, 28 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/ELFWriter.cpp
diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.36 llvm/lib/CodeGen/ELFWriter.cpp:1.37
--- llvm/lib/CodeGen/ELFWriter.cpp:1.36 Fri Jan 26 20:55:44 2007
+++ llvm/lib/CodeGen/ELFWriter.cpp Wed Feb 7 19:35:27 2007
@@ -31,18 +31,32 @@
//
//===--===//
-#include llvm/CodeGen/ELFWriter.h
+#include ELFWriter.h
#include llvm/Module.h
+#include llvm/PassManager.h
+#include llvm/CodeGen/FileWriters.h
#include llvm/CodeGen/MachineCodeEmitter.h
#include llvm/CodeGen/MachineConstantPool.h
+#include llvm/CodeGen/MachineFunctionPass.h
#include llvm/Target/TargetData.h
#include llvm/Target/TargetELFWriterInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Support/Mangler.h
#include llvm/Support/OutputBuffer.h
#include llvm/Support/Streams.h
+#include list
using namespace llvm;
+/// AddELFWriter - Concrete function to add the ELF writer to the function pass
+/// manager.
+MachineCodeEmitter *llvm::AddELFWriter(FunctionPassManager FPM,
+ std::ostream O,
+ TargetMachine TM) {
+ ELFWriter *EW = new ELFWriter(O, TM);
+ FPM.add(EW);
+ return EW-getMachineCodeEmitter();
+}
+
//===--===//
// ELFCodeEmitter Implementation
//===--===//
Index: llvm/lib/CodeGen/MachOWriter.cpp
diff -u llvm/lib/CodeGen/MachOWriter.cpp:1.23
llvm/lib/CodeGen/MachOWriter.cpp:1.24
--- llvm/lib/CodeGen/MachOWriter.cpp:1.23 Tue Feb 6 23:47:16 2007
+++ llvm/lib/CodeGen/MachOWriter.cppWed Feb 7 19:35:27 2007
@@ -22,13 +22,15 @@
//
//===--===//
+#include MachOWriter.h
#include llvm/Constants.h
#include llvm/DerivedTypes.h
#include llvm/Module.h
+#include llvm/PassManager.h
+#include llvm/CodeGen/FileWriters.h
#include llvm/CodeGen/MachineCodeEmitter.h
#include llvm/CodeGen/MachineConstantPool.h
#include llvm/CodeGen/MachineJumpTableInfo.h
-#include llvm/CodeGen/MachOWriter.h
#include llvm/ExecutionEngine/ExecutionEngine.h
#include llvm/Target/TargetAsmInfo.h
#include llvm/Target/TargetJITInfo.h
@@ -37,9 +39,18 @@
#include llvm/Support/OutputBuffer.h
#include llvm/Support/Streams.h
#include algorithm
-
using namespace llvm;
+/// AddMachOWriter - Concrete function to add the Mach-O writer to the function
+/// pass manager.
+MachineCodeEmitter *llvm::AddMachOWriter(FunctionPassManager FPM,
+ std::ostream O,
+ TargetMachine TM) {
+ MachOWriter *MOW = new MachOWriter(O, TM);
+ FPM.add(MOW);
+ return MOW-getMachineCodeEmitter();
+}
+
//===--===//
// MachOCodeEmitter Implementation
//===--===//
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[llvm-commits] CVS: llvm/lib/CodeGen/LLVMTargetMachine.cpp
Changes in directory llvm/lib/CodeGen:
LLVMTargetMachine.cpp updated: 1.7 - 1.8
---
Log message:
Split the addPassesToEmitFile method up into two. This is so that we can
do some common stuff, then on our own add an object file writer (by calling
a concrete function), and then do some finishing stuff, if need be.
---
Diffs of the changes: (+52 -48)
LLVMTargetMachine.cpp | 100 ++
1 files changed, 52 insertions(+), 48 deletions(-)
Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp
diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.7
llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.8
--- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.7 Thu Dec 7 14:28:15 2006
+++ llvm/lib/CodeGen/LLVMTargetMachine.cpp Wed Feb 7 19:36:53 2007
@@ -19,10 +19,11 @@
#include llvm/Transforms/Scalar.h
using namespace llvm;
-bool LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager PM,
-std::ostream Out,
-CodeGenFileType FileType,
-bool Fast) {
+FileModel::Model
+LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager PM,
+ std::ostream Out,
+ CodeGenFileType FileType,
+ bool Fast) {
// Standard LLVM-Level Passes.
// Run loop strength reduction before anything else.
@@ -36,29 +37,25 @@
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
-
-
+
// Ask the target for an isel.
if (addInstSelector(PM, Fast))
-return true;
-
-
+return FileModel::Error;
+
// Print the instruction selected machine code...
if (PrintMachineCode)
-PM.add(createMachineFunctionPrinterPass(cerr.stream()));
+PM.add(createMachineFunctionPrinterPass(cerr));
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
if (PrintMachineCode)
-PM.add(createMachineFunctionPrinterPass(cerr.stream()));
-
-
+PM.add(createMachineFunctionPrinterPass(cerr));
+
// Run post-ra passes.
if (addPostRegAlloc(PM, Fast) PrintMachineCode)
-PM.add(createMachineFunctionPrinterPass(cerr.stream()));
-
-
+PM.add(createMachineFunctionPrinterPass(cerr));
+
// Insert prolog/epilog code. Eliminate abstract frame index references...
PM.add(createPrologEpilogCodeInserter());
@@ -70,28 +67,40 @@
PM.add(createDebugLabelFoldingPass());
if (PrintMachineCode) // Print the register-allocated code
-PM.add(createMachineFunctionPrinterPass(cerr.stream()));
-
-
+PM.add(createMachineFunctionPrinterPass(cerr));
+
if (addPreEmitPass(PM, Fast) PrintMachineCode)
-PM.add(createMachineFunctionPrinterPass(cerr.stream()));
-
-
+PM.add(createMachineFunctionPrinterPass(cerr));
+
switch (FileType) {
-default: return true;
-case TargetMachine::AssemblyFile:
- if (addAssemblyEmitter(PM, Fast, Out))
-return true;
- break;
-case TargetMachine::ObjectFile:
- if (addObjectWriter(PM, Fast, Out))
-return true;
- break;
+ default:
+break;
+ case TargetMachine::AssemblyFile:
+if (addAssemblyEmitter(PM, Fast, Out))
+ return FileModel::Error;
+return FileModel::AsmFile;
+ case TargetMachine::ObjectFile:
+if (getMachOWriterInfo())
+ return FileModel::MachOFile;
+else if (getELFWriterInfo())
+ return FileModel::ElfFile;
}
-
+
+ return FileModel::Error;
+}
+
+/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
+/// be split up (e.g., to add an object writer pass), this method can be used
to
+/// finish up adding passes to emit the file, if necessary.
+bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager PM,
+ MachineCodeEmitter *MCE,
+ bool Fast) {
+ if (MCE)
+addSimpleCodeEmitter(PM, Fast, *MCE);
+
// Delete machine code for this function
PM.add(createMachineCodeDeleter());
-
+
return false; // success!
}
@@ -117,43 +126,38 @@
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
-
-
+
// Ask the target for an isel.
if (addInstSelector(PM, Fast))
return true;
-
-
+
// Print the instruction selected machine code...
if (PrintMachineCode)
-PM.add(createMachineFunctionPrinterPass(cerr.stream()));
+PM.add(createMachineFunctionPrinterPass(cerr));
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
if (PrintMachineCode)
-PM.add(createMachineFunctionPrinterPass(cerr.stream()));
-
-
+PM.add(createMachineFunctionPrinterPass(cerr));
+
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp AlphaTargetMachine.h
Changes in directory llvm/lib/Target/Alpha:
AlphaTargetMachine.cpp updated: 1.35 - 1.36
AlphaTargetMachine.h updated: 1.18 - 1.19
---
Log message:
Added new method to add a simple code emitter. That is, to only add
the code emitter and not set variables.
---
Diffs of the changes: (+7 -0)
AlphaTargetMachine.cpp |5 +
AlphaTargetMachine.h |2 ++
2 files changed, 7 insertions(+)
Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.35
llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.36
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.35 Tue Oct 31 10:49:55 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cppWed Feb 7 19:38:33 2007
@@ -88,3 +88,8 @@
PM.add(createAlphaCodeEmitterPass(*this, MCE));
return false;
}
+bool AlphaTargetMachine::addSimpleCodeEmitter(FunctionPassManager PM,
+ bool Fast,
+ MachineCodeEmitter MCE) {
+ return addCodeEmitter(PM, Fast, MCE);
+}
Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.18
llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.19
--- llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.18 Tue Oct 10 23:29:42 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.h Wed Feb 7 19:38:33 2007
@@ -64,6 +64,8 @@
std::ostream Out);
virtual bool addCodeEmitter(FunctionPassManager PM, bool Fast,
MachineCodeEmitter MCE);
+ virtual bool addSimpleCodeEmitter(FunctionPassManager PM, bool Fast,
+MachineCodeEmitter MCE);
};
} // end namespace llvm
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86TargetMachine.cpp X86TargetMachine.h
Changes in directory llvm/lib/Target/X86:
X86.h updated: 1.49 - 1.50
X86TargetMachine.cpp updated: 1.140 - 1.141
X86TargetMachine.h updated: 1.44 - 1.45
---
Log message:
Moved the MachOWriter and ELFWriter out of the Target/* files. Placed the
definition of it into the CodeGen library. This is so that a backend doesn't
necessarily add in these writers if it doesn't use them (like in the lli
program).
---
Diffs of the changes: (+9 -19)
X86.h|6 --
X86TargetMachine.cpp | 15 ++-
X86TargetMachine.h |7 +++
3 files changed, 9 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.49 llvm/lib/Target/X86/X86.h:1.50
--- llvm/lib/Target/X86/X86.h:1.49 Wed Nov 15 11:53:13 2006
+++ llvm/lib/Target/X86/X86.h Wed Feb 7 19:39:44 2007
@@ -46,12 +46,6 @@
FunctionPass *createX86CodeEmitterPass(X86TargetMachine TM,
MachineCodeEmitter MCE);
-/// addX86ELFObjectWriterPass - Add passes to the FPM that output the generated
-/// code as an ELF object file.
-///
-void addX86ELFObjectWriterPass(FunctionPassManager FPM,
- std::ostream o, X86TargetMachine tm);
-
/// createX86EmitCodeToMemory - Returns a pass that converts a register
/// allocated function into raw machine code in a dynamically
/// allocated chunk of memory.
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.140
llvm/lib/Target/X86/X86TargetMachine.cpp:1.141
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.140 Mon Jan 22 17:09:50 2007
+++ llvm/lib/Target/X86/X86TargetMachine.cppWed Feb 7 19:39:44 2007
@@ -163,15 +163,6 @@
return false;
}
-bool X86TargetMachine::addObjectWriter(FunctionPassManager PM, bool Fast,
- std::ostream Out) {
- if (Subtarget.isTargetELF()) {
-addX86ELFObjectWriterPass(PM, Out, *this);
-return false;
- }
- return true;
-}
-
bool X86TargetMachine::addCodeEmitter(FunctionPassManager PM, bool Fast,
MachineCodeEmitter MCE) {
// FIXME: Move this to TargetJITInfo!
@@ -185,3 +176,9 @@
PM.add(createX86CodeEmitterPass(*this, MCE));
return false;
}
+
+bool X86TargetMachine::addSimpleCodeEmitter(FunctionPassManager PM, bool Fast,
+MachineCodeEmitter MCE) {
+ PM.add(createX86CodeEmitterPass(*this, MCE));
+ return false;
+}
Index: llvm/lib/Target/X86/X86TargetMachine.h
diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.44
llvm/lib/Target/X86/X86TargetMachine.h:1.45
--- llvm/lib/Target/X86/X86TargetMachine.h:1.44 Fri Jan 26 20:56:16 2007
+++ llvm/lib/Target/X86/X86TargetMachine.h Wed Feb 7 19:39:44 2007
@@ -53,22 +53,21 @@
}
virtual const TargetData *getTargetData() const { return DataLayout; }
virtual const X86ELFWriterInfo *getELFWriterInfo() const {
-return ELFWriterInfo;
+return Subtarget.isTargetELF() ? ELFWriterInfo : 0;
}
static unsigned getModuleMatchQuality(const Module M);
static unsigned getJITMatchQuality();
-
// Set up the pass pipeline.
virtual bool addInstSelector(FunctionPassManager PM, bool Fast);
virtual bool addPostRegAlloc(FunctionPassManager PM, bool Fast);
virtual bool addAssemblyEmitter(FunctionPassManager PM, bool Fast,
std::ostream Out);
- virtual bool addObjectWriter(FunctionPassManager PM, bool Fast,
- std::ostream Out);
virtual bool addCodeEmitter(FunctionPassManager PM, bool Fast,
MachineCodeEmitter MCE);
+ virtual bool addSimpleCodeEmitter(FunctionPassManager PM, bool Fast,
+MachineCodeEmitter MCE);
};
/// X86_32TargetMachine - X86 32-bit target machine.
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.h PPCMachOWriterInfo.cpp PPCTargetMachine.cpp PPCTargetMachine.h
Changes in directory llvm/lib/Target/PowerPC:
PPC.h updated: 1.37 - 1.38
PPCMachOWriterInfo.cpp updated: 1.2 - 1.3
PPCTargetMachine.cpp updated: 1.115 - 1.116
PPCTargetMachine.h updated: 1.28 - 1.29
---
Log message:
Moved the MachOWriter and ELFWriter out of the Target/* files. Placed the
definition of it into the CodeGen library. This is so that a backend doesn't
necessarily add in these writers if it doesn't use them (like in the lli
program).
---
Diffs of the changes: (+11 -17)
PPC.h |2 --
PPCMachOWriterInfo.cpp |6 +++---
PPCTargetMachine.cpp | 16 ++--
PPCTargetMachine.h |4 ++--
4 files changed, 11 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC.h
diff -u llvm/lib/Target/PowerPC/PPC.h:1.37 llvm/lib/Target/PowerPC/PPC.h:1.38
--- llvm/lib/Target/PowerPC/PPC.h:1.37 Fri Nov 17 16:10:59 2006
+++ llvm/lib/Target/PowerPC/PPC.h Wed Feb 7 19:39:44 2007
@@ -33,8 +33,6 @@
PPCTargetMachine TM);
FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine TM,
MachineCodeEmitter MCE);
-void addPPCMachOObjectWriterPass(FunctionPassManager FPM, std::ostream o,
- PPCTargetMachine tm);
} // end namespace llvm;
// Defines symbolic names for PowerPC registers. This defines a mapping from
Index: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.2
llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.3
--- llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.2 Fri Feb 2 20:41:58 2007
+++ llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp Wed Feb 7 19:39:44 2007
@@ -2,8 +2,9 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Bill Wendling and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file was developed by Nate Begeman and Bill Wendling and is distributed
+// under the University of Illinois Open Source License. See LICENSE.TXT for
+// details.
//
//===--===//
//
@@ -25,7 +26,6 @@
HDR_CPU_SUBTYPE_POWERPC_ALL) {}
PPCMachOWriterInfo::~PPCMachOWriterInfo() {}
-
/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
/// more PowerPC MachORelocation(s), add the new relocations to the
/// MachOSection, and rewrite the instruction at the section offset if required
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.115
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.116
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.115 Tue Jan 23 21:41:36 2007
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cppWed Feb 7 19:39:44 2007
@@ -129,16 +129,6 @@
return false;
}
-bool PPCTargetMachine::addObjectWriter(FunctionPassManager PM, bool Fast,
- std::ostream Out) {
- // FIXME: until the macho writer is 100% functional, diable this by default.
- return true;
-
- // FIXME: support PPC ELF files at some point
- addPPCMachOObjectWriterPass(PM, Out, *this);
- return false;
-}
-
bool PPCTargetMachine::addCodeEmitter(FunctionPassManager PM, bool Fast,
MachineCodeEmitter MCE) {
// The JIT should use the static relocation model in ppc32 mode, PIC in
ppc64.
@@ -161,3 +151,9 @@
return false;
}
+bool PPCTargetMachine::addSimpleCodeEmitter(FunctionPassManager PM, bool Fast,
+MachineCodeEmitter MCE) {
+ // Machine code emitter pass for PowerPC.
+ PM.add(createPPCCodeEmitterPass(*this, MCE));
+ return false;
+}
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.28
llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.29
--- llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.28 Tue Jan 23 21:41:36 2007
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.h Wed Feb 7 19:39:44 2007
@@ -69,10 +69,10 @@
virtual bool addPreEmitPass(FunctionPassManager PM, bool Fast);
virtual bool addAssemblyEmitter(FunctionPassManager PM, bool Fast,
std::ostream Out);
- virtual bool addObjectWriter(FunctionPassManager PM, bool Fast,
- std::ostream Out);
virtual bool addCodeEmitter(FunctionPassManager PM, bool Fast,
MachineCodeEmitter MCE);
+ virtual bool addSimpleCodeEmitter(FunctionPassManager PM, bool Fast,
+MachineCodeEmitter MCE);
};
/// PPC32TargetMachine - PowerPC 32-bit target machine.
___
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[llvm-commits] CVS: llvm/tools/lto/lto.cpp
Changes in directory llvm/tools/lto:
lto.cpp updated: 1.34 - 1.35
---
Log message:
The new version of how to add passes to emit files. We explicitly call a
function to add the file writers between calls to add the passes.
---
Diffs of the changes: (+26 -2)
lto.cpp | 28 ++--
1 files changed, 26 insertions(+), 2 deletions(-)
Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.34 llvm/tools/lto/lto.cpp:1.35
--- llvm/tools/lto/lto.cpp:1.34 Mon Feb 5 14:47:21 2007
+++ llvm/tools/lto/lto.cpp Wed Feb 7 19:41:07 2007
@@ -27,6 +27,7 @@
#include llvm/System/Signals.h
#include llvm/Analysis/Passes.h
#include llvm/Analysis/Verifier.h
+#include llvm/CodeGen/FileWriters.h
#include llvm/Target/SubtargetFeature.h
#include llvm/Target/TargetData.h
#include llvm/Target/TargetMachine.h
@@ -308,8 +309,31 @@
new FunctionPassManager(new ExistingModuleProvider(M));
CodeGenPasses-add(new TargetData(*Target-getTargetData()));
- Target-addPassesToEmitFile(*CodeGenPasses, Out,
TargetMachine::AssemblyFile,
- true);
+
+ MachineCodeEmitter *MCE = 0;
+
+ switch (Target-addPassesToEmitFile(*CodeGenPasses, Out,
+ TargetMachine::AssemblyFile, true)) {
+ default:
+assert(0 Invalid file model!);
+return LTO_UNKNOWN;
+ case FileModel::Error:
+// FIXME: Error...
+return LTO_UNKNOWN;
+ case FileModel::AsmFile:
+break;
+ case FileModel::MachOFile:
+MCE = AddMachOWriter(*CodeGenPasses, Out, *Target);
+break;
+ case FileModel::ElfFile:
+MCE = AddELFWriter(*CodeGenPasses, Out, *Target);
+break;
+ }
+
+ if (Target-addPassesToEmitFileFinish(*CodeGenPasses, MCE, true)) {
+// FIXME: Error...
+return LTO_UNKNOWN;
+ }
// Run our queue of passes all at once now, efficiently.
Passes.run(*M);
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[llvm-commits] CVS: llvm/tools/lto/lto.cpp
Changes in directory llvm/tools/lto:
lto.cpp updated: 1.35 - 1.36
---
Log message:
Avoid assert() in lto. Let linker handle all failures. Use LTO_WRITE_FAILURE
instead of LTO_UNKNOWN.
---
Diffs of the changes: (+4 -9)
lto.cpp | 13 -
1 files changed, 4 insertions(+), 9 deletions(-)
Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.35 llvm/tools/lto/lto.cpp:1.36
--- llvm/tools/lto/lto.cpp:1.35 Wed Feb 7 19:41:07 2007
+++ llvm/tools/lto/lto.cpp Wed Feb 7 19:48:28 2007
@@ -313,13 +313,10 @@
MachineCodeEmitter *MCE = 0;
switch (Target-addPassesToEmitFile(*CodeGenPasses, Out,
- TargetMachine::AssemblyFile, true)) {
+ TargetMachine::AssemblyFile, true)) {
default:
-assert(0 Invalid file model!);
-return LTO_UNKNOWN;
case FileModel::Error:
-// FIXME: Error...
-return LTO_UNKNOWN;
+return LTO_WRITE_FAILURE;
case FileModel::AsmFile:
break;
case FileModel::MachOFile:
@@ -330,10 +327,8 @@
break;
}
- if (Target-addPassesToEmitFileFinish(*CodeGenPasses, MCE, true)) {
-// FIXME: Error...
-return LTO_UNKNOWN;
- }
+ if (Target-addPassesToEmitFileFinish(*CodeGenPasses, MCE, true))
+return LTO_WRITE_FAILURE;
// Run our queue of passes all at once now, efficiently.
Passes.run(*M);
___
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[llvm-commits] [PATCH] gcc/llvm-backend.cpp
Applied this patch. This goes along with the changes I checked in that
removed the MachO and ELF writers from LLI.
-bw
Index: gcc/llvm-backend.cpp
===
--- gcc/llvm-backend.cpp(revision 123562)
+++ gcc/llvm-backend.cpp(revision 123565)
@@ -338,10 +338,11 @@
}
// Normal mode, emit a .s file by running the code generator.
-if (TheTarget-addPassesToEmitFile(*PM, *AsmOutStream,
+if (TheTarget-addPassesToEmitFile(*PM, *AsmOutStream,
TargetMachine::AssemblyFile,
- /*FAST*/optimize == 0)) {
- cerr Error interfacing to target machine!;
+ /*FAST*/optimize == 0)
+== FileModel::Error) {
+ cerr Error interfacing to target machine!\n;
exit(1);
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCMachOWriterInfo.cpp updated: 1.3 - 1.4 --- Log message: Fixed comments. --- Diffs of the changes: (+2 -3) PPCMachOWriterInfo.cpp |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.3 llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.4 --- llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.3 Wed Feb 7 19:39:44 2007 +++ llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp Thu Feb 8 00:05:08 2007 @@ -2,9 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Nate Begeman and Bill Wendling and is distributed -// under the University of Illinois Open Source License. See LICENSE.TXT for -// details. +// This file was developed by Bill Wendling and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. // //===--===// // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/FileWriters.h
Changes in directory llvm/include/llvm/CodeGen: FileWriters.h updated: 1.1 - 1.2 --- Log message: Fixed comments. --- Diffs of the changes: (+1 -1) FileWriters.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/FileWriters.h diff -u llvm/include/llvm/CodeGen/FileWriters.h:1.1 llvm/include/llvm/CodeGen/FileWriters.h:1.2 --- llvm/include/llvm/CodeGen/FileWriters.h:1.1 Wed Feb 7 19:31:38 2007 +++ llvm/include/llvm/CodeGen/FileWriters.h Thu Feb 8 00:05:08 2007 @@ -1,4 +1,4 @@ -//===-- FileWriters.cpp - File Writers Creation Functions ---*- C++ -*-===// +//===-- FileWriters.h - File Writers Creation Functions -*- C++ -*-===// // // The LLVM Compiler Infrastructure // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/DeveloperPolicy.html
Changes in directory llvm/docs: DeveloperPolicy.html updated: 1.33 - 1.34 --- Log message: Corrected typo. --- Diffs of the changes: (+2 -2) DeveloperPolicy.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/DeveloperPolicy.html diff -u llvm/docs/DeveloperPolicy.html:1.33 llvm/docs/DeveloperPolicy.html:1.34 --- llvm/docs/DeveloperPolicy.html:1.33 Mon Feb 19 11:38:38 2007 +++ llvm/docs/DeveloperPolicy.html Mon Feb 19 12:32:40 2007 @@ -444,7 +444,7 @@ pNote that the LLVM Project does distribute some code that includes GPL software (notably, llvm-gcc which is based on the GCC GPL source base). - This means that anything linked into to llvm-gcc must itself be compatible + This means that anything linked into llvm-gcc must itself be compatible with the GPL, and must be releasable under the terms of the GPL. This implies that bany code linked into llvm-gcc and distributed to others may be subject to @@ -499,7 +499,7 @@ Written by the a href=mailto:[EMAIL PROTECTED]LLVM Oversight Group/abr a href=http://llvm.org;The LLVM Compiler Infrastructure/abr - Last modified: $Date: 2007/02/19 17:38:38 $ + Last modified: $Date: 2007/02/19 18:32:40 $ /address /body /html ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll
Changes in directory llvm/test/CodeGen/CBackend: 2007-01-08-ParamAttr-ICmp.ll updated: 1.3 - 1.4 --- Log message: PR1164: http://llvm.org/PR1164 : Generate local names with a llvm_cbe_ prefix using the actual name of the variable instead of a temporary name. --- Diffs of the changes: (+1 -1) 2007-01-08-ParamAttr-ICmp.ll |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll diff -u llvm/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll:1.3 llvm/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll:1.4 --- llvm/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll:1.3 Thu Feb 15 15:01:58 2007 +++ llvm/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll Fri Feb 23 16:45:08 2007 @@ -1,6 +1,6 @@ ; For PR1099 ; RUN: llvm-as %s | llc -march=c | \ -; RUN: grep 'return ltmp_2_2 == ltmp_1_2)) ? (1) : (0)))' +; RUN: grep 'return llvm_cbe_tmp2 == llvm_cbe_b_0_0_val)) ? (1) : (0)))' target datalayout = e-p:32:32 target triple = i686-apple-darwin8 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/CBackend/CBackend.cpp
Changes in directory llvm/lib/Target/CBackend:
CBackend.cpp updated: 1.327 - 1.328
---
Log message:
PR1164: http://llvm.org/PR1164 :
Generate local names with a llvm_cbe_ prefix using the actual name of the
variable instead of a temporary name.
---
Diffs of the changes: (+52 -22)
CBackend.cpp | 74 +--
1 files changed, 52 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/CBackend/CBackend.cpp
diff -u llvm/lib/Target/CBackend/CBackend.cpp:1.327
llvm/lib/Target/CBackend/CBackend.cpp:1.328
--- llvm/lib/Target/CBackend/CBackend.cpp:1.327 Wed Feb 14 21:39:18 2007
+++ llvm/lib/Target/CBackend/CBackend.cpp Fri Feb 23 16:45:08 2007
@@ -239,7 +239,7 @@
}
void outputLValue(Instruction *I) {
- Out Mang-getValueName(I) = ;
+ Out GetValueName(I) = ;
}
bool isGotoCodeNecessary(BasicBlock *From, BasicBlock *To);
@@ -249,6 +249,8 @@
unsigned Indent);
void printIndexingExpression(Value *Ptr, gep_type_iterator I,
gep_type_iterator E);
+
+std::string GetValueName(const Value *Operand);
};
}
@@ -1080,6 +1082,34 @@
printConstant(CPV);
}
+std::string CWriter::GetValueName(const Value *Operand) {
+ std::string Name;
+
+ if (!isaGlobalValue(Operand) Operand-getName() != ) {
+std::string VarName;
+
+Name = Operand-getName();
+VarName.reserve(Name.capacity());
+
+for (std::string::iterator I = Name.begin(), E = Name.end();
+ I != E; ++I) {
+ char ch = *I;
+
+ if (!((ch = 'a' ch = 'z') || (ch = 'A' ch = 'Z') ||
+(ch = '0' ch = '9') || ch == '_'))
+VarName += '_';
+ else
+VarName += ch;
+}
+
+Name = llvm_cbe_ + VarName;
+ } else {
+Name = Mang-getValueName(Operand);
+ }
+
+ return Name;
+}
+
void CWriter::writeOperandInternal(Value *Operand) {
if (Instruction *I = dyn_castInstruction(Operand))
if (isInlinableInst(*I) !isDirectAlloca(I)) {
@@ -1091,11 +1121,11 @@
}
Constant* CPV = dyn_castConstant(Operand);
- if (CPV !isaGlobalValue(CPV)) {
+
+ if (CPV !isaGlobalValue(CPV))
printConstant(CPV);
- } else {
-Out Mang-getValueName(Operand);
- }
+ else
+Out GetValueName(Operand);
}
void CWriter::writeOperandRaw(Value *Operand) {
@@ -1103,7 +1133,7 @@
if (CPV !isaGlobalValue(CPV)) {
printConstant(CPV);
} else {
-Out Mang-getValueName(Operand);
+Out GetValueName(Operand);
}
}
@@ -1472,17 +1502,17 @@
if (I-hasExternalLinkage()) {
Out extern ;
printType(Out, I-getType()-getElementType(), false,
- Mang-getValueName(I));
+ GetValueName(I));
Out ;\n;
} else if (I-hasDLLImportLinkage()) {
Out __declspec(dllimport) ;
printType(Out, I-getType()-getElementType(), false,
- Mang-getValueName(I));
+ GetValueName(I));
Out ;\n;
} else if (I-hasExternalWeakLinkage()) {
Out extern ;
printType(Out, I-getType()-getElementType(), false,
- Mang-getValueName(I));
+ GetValueName(I));
Out __EXTERNAL_WEAK__ ;\n;
}
}
@@ -1533,7 +1563,7 @@
else
Out extern ;
printType(Out, I-getType()-getElementType(), false,
- Mang-getValueName(I));
+ GetValueName(I));
if (I-hasLinkOnceLinkage())
Out __attribute__((common));
@@ -1565,7 +1595,7 @@
Out __declspec(dllexport) ;
printType(Out, I-getType()-getElementType(), false,
- Mang-getValueName(I));
+ GetValueName(I));
if (I-hasLinkOnceLinkage())
Out __attribute__((common));
else if (I-hasWeakLinkage())
@@ -1772,7 +1802,7 @@
std::stringstream FunctionInnards;
// Print out the name...
- FunctionInnards Mang-getValueName(F) '(';
+ FunctionInnards GetValueName(F) '(';
bool PrintedArg = false;
if (!F-isDeclaration()) {
@@ -1791,7 +1821,7 @@
for (; I != E; ++I) {
if (PrintedArg) FunctionInnards , ;
if (I-hasName() || !Prototype)
- ArgName = Mang-getValueName(I);
+ ArgName = GetValueName(I);
else
ArgName = ;
printType(FunctionInnards, I-getType(),
@@ -1874,7 +1904,7 @@
Out;
printType(Out, F.arg_begin()-getType(), false,
- Mang-getValueName(F.arg_begin()));
+ GetValueName(F.arg_begin()));
Out = StructReturn;\n;
}
@@ -1884,18 +1914,18 @@
for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) {
if (const AllocaInst *AI = isDirectAlloca(*I)) {
Out;
- printType(Out, AI-getAllocatedType(), false, Mang-getValueName(AI));
+ printType(Out, AI-getAllocatedType(), false,
[llvm-commits] CVS: llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll
Changes in directory llvm/test/CodeGen/CBackend:
2007-02-23-NameConflicts.ll added (r1.1)
---
Log message:
Testcase for PR1164: http://llvm.org/PR1164
---
Diffs of the changes: (+13 -0)
2007-02-23-NameConflicts.ll | 13 +
1 files changed, 13 insertions(+)
Index: llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll
diff -c /dev/null llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll:1.1
*** /dev/null Fri Feb 23 17:19:42 2007
--- llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll Fri Feb 23
17:19:32 2007
***
*** 0
--- 1,13
+ ; RUN: llvm-as %s | llc -march=c | grep 'llvm_cbe_A = *llvm_cbe_G;'
+ ; RUN: llvm-as %s | llc -march=c | grep 'llvm_cbe_B = *(ltmp_0_1);'
+ ; RUN: llvm-as %s | llc -march=c | grep 'return (llvm_cbe_A + llvm_cbe_B);'
+ ; PR1164
+ @G = global i32 123
+ @ltmp_0_1 = global i32 123
+
+ define i32 @test(i32 *%G) {
+ %A = load i32* %G
+ %B = load i32* @ltmp_0_1
+ %C = add i32 %A, %B
+ ret i32 %C
+ }
___
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[llvm-commits] CVS: llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll
Changes in directory llvm/test/CodeGen/CBackend: 2007-02-23-NameConflicts.ll updated: 1.1 - 1.2 --- Log message: Make the testcase correct. --- Diffs of the changes: (+2 -2) 2007-02-23-NameConflicts.ll |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll diff -u llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll:1.1 llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll:1.2 --- llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll:1.1 Fri Feb 23 17:19:32 2007 +++ llvm/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll Fri Feb 23 17:23:41 2007 @@ -1,5 +1,5 @@ -; RUN: llvm-as %s | llc -march=c | grep 'llvm_cbe_A = *llvm_cbe_G;' -; RUN: llvm-as %s | llc -march=c | grep 'llvm_cbe_B = *(ltmp_0_1);' +; RUN: llvm-as %s | llc -march=c | grep 'llvm_cbe_A = \*llvm_cbe_G;' +; RUN: llvm-as %s | llc -march=c | grep 'llvm_cbe_B = \*(ltmp_0_1);' ; RUN: llvm-as %s | llc -march=c | grep 'return (llvm_cbe_A + llvm_cbe_B);' ; PR1164 @G = global i32 123 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/HowToSubmitABug.html
Changes in directory llvm/docs: HowToSubmitABug.html updated: 1.27 - 1.28 --- Log message: Added some more information on how to use delta to reduce testcases. --- Diffs of the changes: (+11 -7) HowToSubmitABug.html | 18 +++--- 1 files changed, 11 insertions(+), 7 deletions(-) Index: llvm/docs/HowToSubmitABug.html diff -u llvm/docs/HowToSubmitABug.html:1.27 llvm/docs/HowToSubmitABug.html:1.28 --- llvm/docs/HowToSubmitABug.html:1.27 Sun Aug 27 19:34:18 2006 +++ llvm/docs/HowToSubmitABug.html Fri Feb 23 21:46:42 2007 @@ -81,7 +81,7 @@ div class=doc_text -pMore often than not, bugs in the compiler cause it to crash - often due to an +pMore often than not, bugs in the compiler cause it to crashmdash;often due to an assertion failure of some sort. If you are running ttbopt/b/tt directly, and something crashes, jump to the section on a href=#passesbugs in LLVM passes/a. Otherwise, the most important @@ -126,12 +126,16 @@ ttllvm-gcc/tt command that resulted in the crash, but add the tt-save-temps/tt option. The compiler will crash again, but it will leave behind a ttifoo/i.i/tt file (containing preprocessed C source code) and -possibly ttifoo/i.s/tt (containing LLVM assembly code), for each +possibly ttifoo/i.s/tt (containing LLVM assembly code) for each compiled ttifoo/i.c/tt file. Send us the ttifoo/i.i/tt file, -along with a brief description of the error it caused. A tool that might help -you reduce a front-end testcase to a more manageable size is -a href=http://delta.tigris.org/;delta/a. -/p +along with a brief description of the error it caused./p + +pThe a href=http://delta.tigris.org/;delta/a tool helps to reduce the +preprocessed file down to the smallest amount of code that still replicates the +problem. You're encouraged to use delta to reduce the code to make the +developers' lives easier. a +href=http://gcc.gnu.org/wiki/A_guide_to_testcase_reduction;This website/a +has instructions on the best way to use delta./p /div @@ -352,7 +356,7 @@ a href=mailto:[EMAIL PROTECTED]Chris Lattner/abr a href=http://llvm.org;The LLVM Compiler Infrastructure/a br - Last modified: $Date: 2006/08/28 00:34:18 $ + Last modified: $Date: 2007/02/24 03:46:42 $ /address /body ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.31 - 1.32
---
Log message:
Add the emms intrinsic for MMX support.
---
Diffs of the changes: (+9 -0)
IntrinsicsX86.td |9 +
1 files changed, 9 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.31
llvm/include/llvm/IntrinsicsX86.td:1.32
--- llvm/include/llvm/IntrinsicsX86.td:1.31 Sun Dec 31 16:24:55 2006
+++ llvm/include/llvm/IntrinsicsX86.td Mon Mar 5 17:09:45 2007
@@ -535,3 +535,12 @@
Intrinsic[llvm_void_ty, llvm_i32_ty,
llvm_i32_ty], [IntrWriteMem];
}
+
+//===--===//
+// MMX
+
+// Empty MMX state op.
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_mmx_emms : GCCBuiltin__builtin_ia32_emms,
+ Intrinsic[llvm_void_ty], [IntrWriteMem];
+}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.13 - 1.14
---
Log message:
Add the emms intrinsic for MMX support.
---
Diffs of the changes: (+4 -1)
X86InstrMMX.td |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.13
llvm/lib/Target/X86/X86InstrMMX.td:1.14
--- llvm/lib/Target/X86/X86InstrMMX.td:1.13 Tue Jul 18 19:27:29 2006
+++ llvm/lib/Target/X86/X86InstrMMX.td Mon Mar 5 17:09:45 2007
@@ -33,6 +33,10 @@
def : Pat(v4i16 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX];
def : Pat(v2i32 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX];
+// EMMS
+def EMMS : I0x77, RawFrm, (ops), emms, [(int_x86_mmx_emms)], TB,
+ Requires[HasMMX];
+
// Move Instructions
def MOVD64rr : I0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
movd {$src, $dst|$dst, $src}, [], TB,
@@ -94,4 +98,3 @@
def MASKMOVQ : I0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
maskmovq {$mask, $src|$src, $mask}, [], TB,
Requires[HasMMX];
-
___
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[llvm-commits] CVS: llvm/test/CodeGen/X86/mmx-emms.ll
Changes in directory llvm/test/CodeGen/X86:
mmx-emms.ll added (r1.1)
---
Log message:
Add the emms intrinsic for MMX support.
---
Diffs of the changes: (+11 -0)
mmx-emms.ll | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/CodeGen/X86/mmx-emms.ll
diff -c /dev/null llvm/test/CodeGen/X86/mmx-emms.ll:1.1
*** /dev/null Mon Mar 5 17:09:55 2007
--- llvm/test/CodeGen/X86/mmx-emms.ll Mon Mar 5 17:09:45 2007
***
*** 0
--- 1,11
+ ; RUN: llvm-as %s | llc -march=x86 -mattr=+mmx | grep emms
+ define void @foo() {
+ entry:
+ call void @llvm.x86.mmx.emms( )
+ br label %return
+
+ return: ; preds = %entry
+ ret void
+ }
+
+ declare void @llvm.x86.mmx.emms()
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.361 - 1.362
X86InstrMMX.td updated: 1.14 - 1.15
---
Log message:
Add LOAD/STORE support for MMX.
---
Diffs of the changes: (+47 -22)
X86ISelLowering.cpp |3 ++
X86InstrMMX.td | 66 ++--
2 files changed, 47 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.361
llvm/lib/Target/X86/X86ISelLowering.cpp:1.362
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.361 Tue Mar 6 02:12:33 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 6 12:53:42 2007
@@ -327,6 +327,9 @@
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
+setOperationAction(ISD::LOAD, MVT::v8i8, Legal);
+setOperationAction(ISD::LOAD, MVT::v4i16, Legal);
+setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.14
llvm/lib/Target/X86/X86InstrMMX.td:1.15
--- llvm/lib/Target/X86/X86InstrMMX.td:1.14 Mon Mar 5 17:09:45 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 6 12:53:42 2007
@@ -13,7 +13,10 @@
//
//===--===//
+//===--===//
// Instruction templates
+//===--===//
+
// MMXI - MMX instructions with TB prefix.
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
@@ -30,33 +33,42 @@
[(set VR64:$dst, (v8i8 (undef)))],
Requires[HasMMX];
+def : Pat(v8i8 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX];
def : Pat(v4i16 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX];
def : Pat(v2i32 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX];
-// EMMS
-def EMMS : I0x77, RawFrm, (ops), emms, [(int_x86_mmx_emms)], TB,
- Requires[HasMMX];
+//===--===//
+// MMX Pattern Fragments
+//===--===//
-// Move Instructions
-def MOVD64rr : I0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
- movd {$src, $dst|$dst, $src}, [], TB,
- Requires[HasMMX];
-def MOVD64rm : I0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
- movd {$src, $dst|$dst, $src}, [], TB,
- Requires[HasMMX];
-def MOVD64mr : I0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
- movd {$src, $dst|$dst, $src}, [], TB,
- Requires[HasMMX];
+def loadv2i32 : PatFrag(ops node:$ptr), (v2i32 (load node:$ptr));
-def MOVQ64rr : I0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
- movq {$src, $dst|$dst, $src}, [], TB,
- Requires[HasMMX];
-def MOVQ64rm : I0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
- movq {$src, $dst|$dst, $src}, [], TB,
- Requires[HasMMX];
-def MOVQ64mr : I0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
- movq {$src, $dst|$dst, $src}, [], TB,
- Requires[HasMMX];
+//===--===//
+// MMX EMMS Instruction
+//===--===//
+
+def EMMS : MMXI0x77, RawFrm, (ops), emms, [(int_x86_mmx_emms)];
+
+//===--===//
+// MMX Scalar Instructions
+//===--===//
+
+// Move Instructions
+def MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MOVD64rm : MMXI0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MOVD64mr : MMXI0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+movd {$src, $dst|$dst, $src}, [];
+
+def MOVQ64rr : MMXI0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src}, [];
+def MOVQ64rm : MMXI0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+movq {$src, $dst|$dst, $src},
+[(set VR64:$dst, (loadv2i32 addr:$src))];
+def MOVQ64mr : MMXI0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src},
+[(store (v2i32 VR64:$src), addr:$dst)];
// Conversion instructions
def CVTPI2PSrr : MMXI0x2A, MRMSrcReg, (ops
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.362 - 1.363 X86InstrMMX.td updated: 1.15 - 1.16 --- Log message: Properly support v8i8 and v4i16 types. It now converts them to v2i32 for load and stores. --- Diffs of the changes: (+20 -6) X86ISelLowering.cpp |7 +-- X86InstrMMX.td | 19 +++ 2 files changed, 20 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.362 llvm/lib/Target/X86/X86ISelLowering.cpp:1.363 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.362 Tue Mar 6 12:53:42 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 6 23:43:18 2007 @@ -327,9 +327,12 @@ addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); // FIXME: add MMX packed arithmetics -setOperationAction(ISD::LOAD, MVT::v8i8, Legal); -setOperationAction(ISD::LOAD, MVT::v4i16, Legal); +setOperationAction(ISD::LOAD, MVT::v8i8, Promote); +AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32); +setOperationAction(ISD::LOAD, MVT::v4i16, Promote); +AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32); setOperationAction(ISD::LOAD, MVT::v2i32, Legal); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.15 llvm/lib/Target/X86/X86InstrMMX.td:1.16 --- llvm/lib/Target/X86/X86InstrMMX.td:1.15 Tue Mar 6 12:53:42 2007 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 6 23:43:18 2007 @@ -1,4 +1,4 @@ -//- X86InstrMMX.td - Describe the X86 Instruction Set ---*- C++ -*-===// +//- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -33,14 +33,17 @@ [(set VR64:$dst, (v8i8 (undef)))], Requires[HasMMX]; -def : Pat(v8i8 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX]; -def : Pat(v4i16 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX]; -def : Pat(v2i32 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX]; +// 64-bit vector undef's. +def : Pat(v8i8 (undef)), (IMPLICIT_DEF_VR64); +def : Pat(v4i16 (undef)), (IMPLICIT_DEF_VR64); +def : Pat(v2i32 (undef)), (IMPLICIT_DEF_VR64); //===--===// // MMX Pattern Fragments //===--===// +def loadv8i8 : PatFrag(ops node:$ptr), (v8i8 (load node:$ptr)); +def loadv4i16 : PatFrag(ops node:$ptr), (v4i16 (load node:$ptr)); def loadv2i32 : PatFrag(ops node:$ptr), (v2i32 (load node:$ptr)); //===--===// @@ -120,3 +123,11 @@ (MOVQ64mr addr:$dst, VR64:$src); def : Pat(store (v4i16 VR64:$src), addr:$dst), (MOVQ64mr addr:$dst, VR64:$src); + +// Bit convert. +def : Pat(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src); +def : Pat(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src); +def : Pat(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src); +def : Pat(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src); +def : Pat(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src); +def : Pat(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td
Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.16 - 1.17 --- Log message: Remove useless pattern fragments. --- Diffs of the changes: (+0 -2) X86InstrMMX.td |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.16 llvm/lib/Target/X86/X86InstrMMX.td:1.17 --- llvm/lib/Target/X86/X86InstrMMX.td:1.16 Tue Mar 6 23:43:18 2007 +++ llvm/lib/Target/X86/X86InstrMMX.td Wed Mar 7 12:23:09 2007 @@ -42,8 +42,6 @@ // MMX Pattern Fragments //===--===// -def loadv8i8 : PatFrag(ops node:$ptr), (v8i8 (load node:$ptr)); -def loadv4i16 : PatFrag(ops node:$ptr), (v4i16 (load node:$ptr)); def loadv2i32 : PatFrag(ops node:$ptr), (v2i32 (load node:$ptr)); //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.cpp X86InstrMMX.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.364 - 1.365
X86InstrInfo.cpp updated: 1.77 - 1.78
X86InstrMMX.td updated: 1.17 - 1.18
X86RegisterInfo.cpp updated: 1.206 - 1.207
---
Log message:
Added padd* support for MMX. Added MMX move stuff to X86InstrInfo so that
moves, loads, etc. are recognized.
---
Diffs of the changes: (+73 -10)
X86ISelLowering.cpp | 23 ++-
X86InstrInfo.cpp|7 ++-
X86InstrMMX.td | 47 +++
X86RegisterInfo.cpp |6 ++
4 files changed, 73 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.364
llvm/lib/Target/X86/X86ISelLowering.cpp:1.365
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.364 Wed Mar 7 10:25:09 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 8 16:09:11 2007
@@ -326,15 +326,20 @@
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
-setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
-setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
-setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
-
-setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
+
+setOperationAction(ISD::ADD,MVT::v8i8, Legal);
+setOperationAction(ISD::ADD,MVT::v4i16, Legal);
+setOperationAction(ISD::ADD,MVT::v2i32, Legal);
+
+setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
+AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
+AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
+
+setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
}
if (Subtarget-hasSSE1()) {
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.77
llvm/lib/Target/X86/X86InstrInfo.cpp:1.78
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.77 Fri Jan 26 08:34:51 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppThu Mar 8 16:09:11 2007
@@ -37,7 +37,8 @@
oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
- oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr) {
+ oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
+ oc == X86::MOVD64rr || oc == X86::MOVQ64rr) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
@@ -64,6 +65,8 @@
case X86::MOVSDrm:
case X86::MOVAPSrm:
case X86::MOVAPDrm:
+ case X86::MOVD64rm:
+ case X86::MOVQ64rm:
if (MI-getOperand(1).isFrameIndex() MI-getOperand(2).isImmediate()
MI-getOperand(3).isRegister() MI-getOperand(4).isImmediate()
MI-getOperand(2).getImmedValue() == 1
@@ -92,6 +95,8 @@
case X86::MOVSDmr:
case X86::MOVAPSmr:
case X86::MOVAPDmr:
+ case X86::MOVD64mr:
+ case X86::MOVQ64mr:
if (MI-getOperand(0).isFrameIndex() MI-getOperand(1).isImmediate()
MI-getOperand(2).isRegister() MI-getOperand(3).isImmediate()
MI-getOperand(1).getImmedValue() == 1
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.17
llvm/lib/Target/X86/X86InstrMMX.td:1.18
--- llvm/lib/Target/X86/X86InstrMMX.td:1.17 Wed Mar 7 12:23:09 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Thu Mar 8 16:09:11 2007
@@ -45,6 +45,42 @@
def loadv2i32 : PatFrag(ops node:$ptr), (v2i32 (load node:$ptr));
//===--===//
+// MMX Multiclasses
+//===--===//
+
+let isTwoAddress = 1 in {
+ // MMXI_binop_rm - Simple MMX binary operator.
+ multiclass MMXI_binop_rmbits8 opc, string OpcodeStr, SDNode OpNode,
+ ValueType OpVT, bit Commutable = 0 {
+def rr : MMXIopc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))] {
+ let isCommutable = Commutable;
+}
+def rm : MMXIopc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ !strconcat(OpcodeStr,
[llvm-commits] CVS: llvm/test/CodeGen/X86/mmx-arith.ll
Changes in directory llvm/test/CodeGen/X86:
mmx-arith.ll added (r1.1)
---
Log message:
Add MMX arithmetic testcase.
---
Diffs of the changes: (+35 -0)
mmx-arith.ll | 35 +++
1 files changed, 35 insertions(+)
Index: llvm/test/CodeGen/X86/mmx-arith.ll
diff -c /dev/null llvm/test/CodeGen/X86/mmx-arith.ll:1.1
*** /dev/null Thu Mar 8 16:15:01 2007
--- llvm/test/CodeGen/X86/mmx-arith.ll Thu Mar 8 16:14:51 2007
***
*** 0
--- 1,35
+ ; RUN: llvm-as %s | llc -march=x86 -mattr=+mmx
+
+ ;; A basic sanity check to make sure that MMX arithmetic actually compiles.
+
+ define void @foo(2 x i32* %A, 2 x i32* %B) {
+ entry:
+ %tmp1 = load 2 x i32* %A ; 2 x i32 [#uses=1]
+ %tmp3 = load 2 x i32* %B ; 2 x i32 [#uses=1]
+ %tmp4 = add 2 x i32 %tmp1, %tmp3 ; 2 x i32 [#uses=1]
+ store 2 x i32 %tmp4, 2 x i32* %A
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+ }
+
+ define void @bar(4 x i16* %A, 4 x i16* %B) {
+ entry:
+ %tmp1 = load 4 x i16* %A ; 4 x i16 [#uses=1]
+ %tmp3 = load 4 x i16* %B ; 4 x i16 [#uses=1]
+ %tmp4 = add 4 x i16 %tmp1, %tmp3 ; 4 x i16 [#uses=1]
+ store 4 x i16 %tmp4, 4 x i16* %A
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+ }
+
+ define void @baz(8 x i8* %A, 8 x i8* %B) {
+ entry:
+ %tmp1 = load 8 x i8* %A ; 8 x i8 [#uses=1]
+ %tmp3 = load 8 x i8* %B ; 8 x i8 [#uses=1]
+ %tmp4 = add 8 x i8 %tmp1, %tmp3 ; 8 x i8 [#uses=1]
+ store 8 x i8 %tmp4, 8 x i8* %A
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+ }
+
+ declare void @llvm.x86.mmx.emms()
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[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
Changes in directory llvm/lib/ExecutionEngine/Interpreter: Execution.cpp updated: 1.175 - 1.176 --- Log message: Don't use a cast. It causes an error on some platforms. --- Diffs of the changes: (+1 -1) Execution.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp diff -u llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.175 llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.176 --- llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.175Mon Mar 5 21:46:41 2007 +++ llvm/lib/ExecutionEngine/Interpreter/Execution.cpp Thu Mar 8 17:26:50 2007 @@ -753,7 +753,7 @@ DOUT Allocated Type: *Ty ( TypeSize bytes) x NumElements (Total: MemToAlloc ) at -unsigned(Memory) '\n'; +std::hex Memory '\n'; GenericValue Result = PTOGV(Memory); assert(Result.PointerVal != 0 Null pointer returned by malloc!); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
Changes in directory llvm/lib/ExecutionEngine/Interpreter: Execution.cpp updated: 1.176 - 1.177 --- Log message: Don't use std::hex. --- Diffs of the changes: (+1 -1) Execution.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp diff -u llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.176 llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.177 --- llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.176Thu Mar 8 17:26:50 2007 +++ llvm/lib/ExecutionEngine/Interpreter/Execution.cpp Thu Mar 8 17:37:24 2007 @@ -753,7 +753,7 @@ DOUT Allocated Type: *Ty ( TypeSize bytes) x NumElements (Total: MemToAlloc ) at -std::hex Memory '\n'; +uintptr_t(Memory) '\n'; GenericValue Result = PTOGV(Memory); assert(Result.PointerVal != 0 Null pointer returned by malloc!); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.365 - 1.366
X86InstrMMX.td updated: 1.18 - 1.19
---
Log message:
Adding more arithmetic operators to MMX. This is an almost exact copy of
the addition. Please let me know if you have suggestions.
---
Diffs of the changes: (+14 -0)
X86ISelLowering.cpp |4
X86InstrMMX.td | 10 ++
2 files changed, 14 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.365
llvm/lib/Target/X86/X86ISelLowering.cpp:1.366
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.365 Thu Mar 8 16:09:11 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 10 03:57:05 2007
@@ -331,6 +331,10 @@
setOperationAction(ISD::ADD,MVT::v4i16, Legal);
setOperationAction(ISD::ADD,MVT::v2i32, Legal);
+setOperationAction(ISD::SUB,MVT::v8i8, Legal);
+setOperationAction(ISD::SUB,MVT::v4i16, Legal);
+setOperationAction(ISD::SUB,MVT::v2i32, Legal);
+
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.18
llvm/lib/Target/X86/X86InstrMMX.td:1.19
--- llvm/lib/Target/X86/X86InstrMMX.td:1.18 Thu Mar 8 16:09:11 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Sat Mar 10 03:57:05 2007
@@ -101,6 +101,16 @@
defm MMX_PADDUSB : MMXI_binop_rm_int0xDC, paddusb, int_x86_mmx_paddus_b, 1;
defm MMX_PADDUSW : MMXI_binop_rm_int0xDD, paddusw, int_x86_mmx_paddus_w, 1;
+defm MMX_PSUBB : MMXI_binop_rm0xF8, psubb, sub, v8i8;
+defm MMX_PSUBW : MMXI_binop_rm0xF9, psubw, sub, v4i16;
+defm MMX_PSUBD : MMXI_binop_rm0xFA, psubd, sub, v2i32;
+
+defm MMX_PSUBSB : MMXI_binop_rm_int0xE8, psubsb , int_x86_mmx_psubs_b;
+defm MMX_PSUBSW : MMXI_binop_rm_int0xE9, psubsw , int_x86_mmx_psubs_w;
+
+defm MMX_PSUBUSB : MMXI_binop_rm_int0xD8, psubusb, int_x86_mmx_psubus_b;
+defm MMX_PSUBUSW : MMXI_binop_rm_int0xD9, psubusw, int_x86_mmx_psubus_w;
+
// Move Instructions
def MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
movd {$src, $dst|$dst, $src}, [];
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.33 - 1.34
---
Log message:
Adding more arithmetic operators to MMX. This is an almost exact copy of
the addition. Please let me know if you have suggestions.
---
Diffs of the changes: (+16 -0)
IntrinsicsX86.td | 16
1 files changed, 16 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.33
llvm/include/llvm/IntrinsicsX86.td:1.34
--- llvm/include/llvm/IntrinsicsX86.td:1.33 Thu Mar 8 16:09:11 2007
+++ llvm/include/llvm/IntrinsicsX86.td Sat Mar 10 03:57:05 2007
@@ -547,6 +547,7 @@
// Integer arithmetic ops.
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ // Addition
def int_x86_mmx_padds_b : GCCBuiltin__builtin_ia32_paddsb,
Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
llvm_v8i8_ty], [IntrNoMem];
@@ -560,4 +561,19 @@
def int_x86_mmx_paddus_w : GCCBuiltin__builtin_ia32_paddusw,
Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem];
+
+ // Subtraction
+ def int_x86_mmx_psubs_b : GCCBuiltin__builtin_ia32_psubsb,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
+ def int_x86_mmx_psubs_w : GCCBuiltin__builtin_ia32_psubsw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+
+ def int_x86_mmx_psubus_b : GCCBuiltin__builtin_ia32_psubusb,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
+ def int_x86_mmx_psubus_w : GCCBuiltin__builtin_ia32_psubusw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
}
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[llvm-commits] CVS: llvm/test/CodeGen/X86/mmx-arith.ll
Changes in directory llvm/test/CodeGen/X86:
mmx-arith.ll updated: 1.1 - 1.2
---
Log message:
Adding more arithmetic operators to MMX. This is an almost exact copy of
the addition. Please let me know if you have suggestions.
---
Diffs of the changes: (+64 -15)
mmx-arith.ll | 79 +++
1 files changed, 64 insertions(+), 15 deletions(-)
Index: llvm/test/CodeGen/X86/mmx-arith.ll
diff -u llvm/test/CodeGen/X86/mmx-arith.ll:1.1
llvm/test/CodeGen/X86/mmx-arith.ll:1.2
--- llvm/test/CodeGen/X86/mmx-arith.ll:1.1 Thu Mar 8 16:14:51 2007
+++ llvm/test/CodeGen/X86/mmx-arith.ll Sat Mar 10 03:57:05 2007
@@ -2,34 +2,83 @@
;; A basic sanity check to make sure that MMX arithmetic actually compiles.
-define void @foo(2 x i32* %A, 2 x i32* %B) {
+define void @foo(8 x i8* %A, 8 x i8* %B) {
entry:
- %tmp1 = load 2 x i32* %A ; 2 x i32 [#uses=1]
- %tmp3 = load 2 x i32* %B ; 2 x i32 [#uses=1]
- %tmp4 = add 2 x i32 %tmp1, %tmp3 ; 2 x i32 [#uses=1]
- store 2 x i32 %tmp4, 2 x i32* %A
+ %tmp5 = load 8 x i8* %A ; 8 x i8 [#uses=1]
+ %tmp7 = load 8 x i8* %B ; 8 x i8 [#uses=1]
+ %tmp8 = add 8 x i8 %tmp5, %tmp7 ; 8 x i8 [#uses=2]
+ store 8 x i8 %tmp8, 8 x i8* %A
+ %tmp14 = load 8 x i8* %B ; 8 x i8 [#uses=1]
+ %tmp25 = tail call 8 x i8 @llvm.x86.mmx.padds.b( 8 x i8 %tmp14, 8
x i8 %tmp8 ); 8 x i8 [#uses=2]
+ store 8 x i8 %tmp25, 8 x i8* %B
+ %tmp36 = load 8 x i8* %A ; 8 x i8 [#uses=1]
+ %tmp49 = tail call 8 x i8 @llvm.x86.mmx.paddus.b( 8 x i8 %tmp36, 8
x i8 %tmp25 ) ; 8 x i8 [#uses=2]
+ store 8 x i8 %tmp49, 8 x i8* %B
+ %tmp58 = load 8 x i8* %A ; 8 x i8 [#uses=1]
+ %tmp61 = sub 8 x i8 %tmp58, %tmp49; 8 x i8 [#uses=2]
+ store 8 x i8 %tmp61, 8 x i8* %B
+ %tmp64 = load 8 x i8* %A ; 8 x i8 [#uses=1]
+ %tmp80 = tail call 8 x i8 @llvm.x86.mmx.psubs.b( 8 x i8 %tmp61, 8
x i8 %tmp64 ) ; 8 x i8 [#uses=2]
+ store 8 x i8 %tmp80, 8 x i8* %A
+ %tmp89 = load 8 x i8* %B ; 8 x i8 [#uses=1]
+ %tmp105 = tail call 8 x i8 @llvm.x86.mmx.psubus.b( 8 x i8 %tmp80,
8 x i8 %tmp89 ) ; 8 x i8 [#uses=1]
+ store 8 x i8 %tmp105, 8 x i8* %A
tail call void @llvm.x86.mmx.emms( )
ret void
}
-define void @bar(4 x i16* %A, 4 x i16* %B) {
+define void @baz(2 x i32* %A, 2 x i32* %B) {
entry:
- %tmp1 = load 4 x i16* %A ; 4 x i16 [#uses=1]
- %tmp3 = load 4 x i16* %B ; 4 x i16 [#uses=1]
- %tmp4 = add 4 x i16 %tmp1, %tmp3 ; 4 x i16 [#uses=1]
- store 4 x i16 %tmp4, 4 x i16* %A
+ %tmp1 = load 2 x i32* %A ; 2 x i32 [#uses=1]
+ %tmp3 = load 2 x i32* %B ; 2 x i32 [#uses=1]
+ %tmp4 = add 2 x i32 %tmp1, %tmp3 ; 2 x i32 [#uses=2]
+ store 2 x i32 %tmp4, 2 x i32* %A
+ %tmp9 = load 2 x i32* %B ; 2 x i32 [#uses=1]
+ %tmp10 = sub 2 x i32 %tmp4, %tmp9 ; 2 x i32 [#uses=1]
+ store 2 x i32 %tmp10, 2 x i32* %B
tail call void @llvm.x86.mmx.emms( )
ret void
}
-define void @baz(8 x i8* %A, 8 x i8* %B) {
+define void @bar(4 x i16* %A, 4 x i16* %B) {
entry:
- %tmp1 = load 8 x i8* %A ; 8 x i8 [#uses=1]
- %tmp3 = load 8 x i8* %B ; 8 x i8 [#uses=1]
- %tmp4 = add 8 x i8 %tmp1, %tmp3 ; 8 x i8 [#uses=1]
- store 8 x i8 %tmp4, 8 x i8* %A
+ %tmp5 = load 4 x i16* %A ; 4 x i16 [#uses=1]
+ %tmp7 = load 4 x i16* %B ; 4 x i16 [#uses=1]
+ %tmp8 = add 4 x i16 %tmp5, %tmp7 ; 4 x i16 [#uses=2]
+ store 4 x i16 %tmp8, 4 x i16* %A
+ %tmp14 = load 4 x i16* %B ; 4 x i16 [#uses=1]
+ %tmp25 = tail call 4 x i16 @llvm.x86.mmx.padds.w( 4 x i16 %tmp14,
4 x i16 %tmp8 ) ; 4 x i16 [#uses=2]
+ store 4 x i16 %tmp25, 4 x i16* %B
+ %tmp36 = load 4 x i16* %A ; 4 x i16 [#uses=1]
+ %tmp49 = tail call 4 x i16 @llvm.x86.mmx.paddus.w( 4 x i16 %tmp36,
4 x i16 %tmp25 ) ; 4 x i16 [#uses=2]
+ store 4 x i16 %tmp49, 4 x i16* %B
+ %tmp58 = load 4 x i16* %A ; 4 x i16 [#uses=1]
+ %tmp61 = sub 4 x i16 %tmp58, %tmp49 ; 4 x i16 [#uses=2]
+ store 4 x i16 %tmp61, 4 x i16* %B
+ %tmp64 = load 4 x i16* %A ; 4 x i16 [#uses=1]
+ %tmp80 = tail call 4 x i16 @llvm.x86.mmx.psubs.w( 4 x i16 %tmp61,
4 x i16 %tmp64 ); 4 x i16 [#uses=2]
+ store 4 x i16 %tmp80, 4 x i16* %A
+ %tmp89 = load 4 x i16* %B ; 4 x i16 [#uses=1]
+ %tmp105 = tail call 4 x i16 @llvm.x86.mmx.psubus.w( 4 x i16 %tmp80,
4 x i16 %tmp89 ) ; 4 x i16 [#uses=1]
+
[llvm-commits] CVS: llvm-www/pubs/2007-03-12-BossaLLVMIntro.html
Changes in directory llvm-www/pubs: 2007-03-12-BossaLLVMIntro.html updated: 1.1 - 1.2 --- Log message: Typo and formatting changes. --- Diffs of the changes: (+17 -2) 2007-03-12-BossaLLVMIntro.html | 19 +-- 1 files changed, 17 insertions(+), 2 deletions(-) Index: llvm-www/pubs/2007-03-12-BossaLLVMIntro.html diff -u llvm-www/pubs/2007-03-12-BossaLLVMIntro.html:1.1 llvm-www/pubs/2007-03-12-BossaLLVMIntro.html:1.2 --- llvm-www/pubs/2007-03-12-BossaLLVMIntro.html:1.1Tue Mar 13 08:15:19 2007 +++ llvm-www/pubs/2007-03-12-BossaLLVMIntro.htmlTue Mar 13 13:46:49 2007 @@ -17,9 +17,24 @@ h2Abstract:/h2 blockquote p -LLVM (http://llvm.org) is a suite of carefully designed open source libraries which implement compiler components (like language front-ends, code generators, aggressive optimizers, Just-In-Time compiler support, debug support, link-time optimization, etc). The goal of the LLVM project is to build these components in a way that allows them to be combined together to create familiar tools (like a C compiler), interesting new tools (like an OpenGL JIT compiler) and many other things we haven't though of yet. Because LLVM is under continuous development, clients of these components naturally benefit from improvements in the libraries./p +LLVM (http://llvm.org) is a suite of carefully designed open source +libraries which implement compiler components (like language +front-ends, code generators, aggressive optimizers, Just-In-Time +compiler support, debug support, link-time optimization, etc). The +goal of the LLVM project is to build these components in a way that +allows them to be combined together to create familiar tools (like a C +compiler), interesting new tools (like an OpenGL JIT compiler) and +many other things we haven't thought of yet. Because LLVM is under +continuous development, clients of these components naturally benefit +from improvements in the libraries./p -pThis talk gives an overview of LLVM's architecture, design and philosophy, and gives a high-level overview of the various components that are available. It then describes implementation details and design points of some example clients -- LLVM's GCC-based C/C++/Objective-C compiler, the OpenGL stack in Mac OS/X Leopard, and scripting language compilers -- describing some of the novel capabilities that LLVM contributes to these projects./p +pThis talk gives an overview of LLVM's architecture, design and +philosophy, and gives a high-level overview of the various components +that are available. It then describes implementation details and +design points of some example clientsmdash;LLVM's GCC-based +C/C++/Objective-C compiler, the OpenGL stack in Mac OS/X Leopard, and +scripting language compilersmdash;describing some of the novel +capabilities that LLVM contributes to these projects./p /blockquote ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.34 - 1.35 --- Log message: Multiplication support for MMX. --- Diffs of the changes: (+8 -0) IntrinsicsX86.td |8 1 files changed, 8 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.34 llvm/include/llvm/IntrinsicsX86.td:1.35 --- llvm/include/llvm/IntrinsicsX86.td:1.34 Sat Mar 10 03:57:05 2007 +++ llvm/include/llvm/IntrinsicsX86.td Thu Mar 15 16:24:36 2007 @@ -576,4 +576,12 @@ def int_x86_mmx_psubus_w : GCCBuiltin__builtin_ia32_psubusw, Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]; + + // Multiplication + def int_x86_mmx_pmulh_w : GCCBuiltin__builtin_ia32_pmulhw, + Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty, + llvm_v4i16_ty], [IntrNoMem]; + def int_x86_mmx_pmadd_wd : GCCBuiltin__builtin_ia32_pmaddwd, + Intrinsic[llvm_v2i32_ty, llvm_v4i16_ty, + llvm_v4i16_ty], [IntrNoMem]; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.369 - 1.370
X86InstrMMX.td updated: 1.19 - 1.20
---
Log message:
Multiplication support for MMX.
---
Diffs of the changes: (+9 -1)
X86ISelLowering.cpp |3 +++
X86InstrMMX.td |7 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.369
llvm/lib/Target/X86/X86ISelLowering.cpp:1.370
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.369 Wed Mar 14 17:11:11 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 15 16:24:36 2007
@@ -325,6 +325,9 @@
setOperationAction(ISD::SUB,MVT::v4i16, Legal);
setOperationAction(ISD::SUB,MVT::v2i32, Legal);
+setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
+setOperationAction(ISD::MUL,MVT::v4i16, Legal);
+
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.19
llvm/lib/Target/X86/X86InstrMMX.td:1.20
--- llvm/lib/Target/X86/X86InstrMMX.td:1.19 Sat Mar 10 03:57:05 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Thu Mar 15 16:24:36 2007
@@ -111,6 +111,11 @@
defm MMX_PSUBUSB : MMXI_binop_rm_int0xD8, psubusb, int_x86_mmx_psubus_b;
defm MMX_PSUBUSW : MMXI_binop_rm_int0xD9, psubusw, int_x86_mmx_psubus_w;
+defm MMX_PMULLW : MMXI_binop_rm0xD5, pmullw, mul, v4i16, 1;
+
+defm MMX_PMULHW : MMXI_binop_rm_int0xE5, pmulhw , int_x86_mmx_pmulh_w , 1;
+defm MMX_PMADDWD : MMXI_binop_rm_int0xF5, pmaddwd, int_x86_mmx_pmadd_wd, 1;
+
// Move Instructions
def MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
movd {$src, $dst|$dst, $src}, [];
@@ -139,7 +144,7 @@
cvtpi2pd {$src, $dst|$dst, $src}, [];
def CVTTPS2PIrr: I0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
cvttps2pi {$src, $dst|$dst, $src}, [], TB,
- Requires[HasSSE2];
+ Requires[HasMMX];
def CVTTPS2PIrm: I0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
cvttps2pi {$src, $dst|$dst, $src}, [], TB,
Requires[HasMMX];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.370 - 1.371
X86InstrMMX.td updated: 1.20 - 1.21
---
Log message:
And now support for MMX logical operations.
---
Diffs of the changes: (+54 -2)
X86ISelLowering.cpp | 18 ++
X86InstrMMX.td | 38 --
2 files changed, 54 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.370
llvm/lib/Target/X86/X86ISelLowering.cpp:1.371
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.370 Thu Mar 15 16:24:36 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 16 04:44:46 2007
@@ -328,6 +328,24 @@
setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
setOperationAction(ISD::MUL,MVT::v4i16, Legal);
+setOperationAction(ISD::AND,MVT::v8i8, Promote);
+AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::AND,MVT::v4i16, Promote);
+AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::AND,MVT::v2i32, Legal);
+
+setOperationAction(ISD::OR, MVT::v8i8, Promote);
+AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::OR, MVT::v4i16, Promote);
+AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::OR, MVT::v2i32, Legal);
+
+setOperationAction(ISD::XOR,MVT::v8i8, Promote);
+AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::XOR,MVT::v4i16, Promote);
+AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::XOR,MVT::v2i32, Legal);
+
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.20
llvm/lib/Target/X86/X86InstrMMX.td:1.21
--- llvm/lib/Target/X86/X86InstrMMX.td:1.20 Thu Mar 15 16:24:36 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Fri Mar 16 04:44:46 2007
@@ -63,9 +63,7 @@
(bitconvert
(loadv2i32 addr:$src2)];
}
-}
-let isTwoAddress = 1 in {
multiclass MMXI_binop_rm_intbits8 opc, string OpcodeStr, Intrinsic IntId,
bit Commutable = 0 {
def rr : MMXIopc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
@@ -78,6 +76,24 @@
[(set VR64:$dst, (IntId VR64:$src1,
(bitconvert (loadv2i32 addr:$src2];
}
+
+ // MMXI_binop_rm_v2i32 - Simple MMX binary operator whose type is v2i32.
+ //
+ // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen
knew
+ // to collapse (bitconvert VT to VT) into its operand.
+ //
+ multiclass MMXI_binop_rm_v2i32bits8 opc, string OpcodeStr, SDNode OpNode,
+ bit Commutable = 0 {
+def rr : MMXIopc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR64:$dst, (v2i32 (OpNode VR64:$src1, VR64:$src2)))] {
+ let isCommutable = Commutable;
+}
+def rm : MMXIopc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR64:$dst,
+(OpNode VR64:$src1,(loadv2i32 addr:$src2)))];
+ }
}
//===--===//
@@ -116,6 +132,24 @@
defm MMX_PMULHW : MMXI_binop_rm_int0xE5, pmulhw , int_x86_mmx_pmulh_w , 1;
defm MMX_PMADDWD : MMXI_binop_rm_int0xF5, pmaddwd, int_x86_mmx_pmadd_wd, 1;
+// Logical Instructions
+defm MMX_PAND : MMXI_binop_rm_v2i320xDB, pand, and, 1;
+defm MMX_POR : MMXI_binop_rm_v2i320xEB, por , or, 1;
+defm MMX_PXOR : MMXI_binop_rm_v2i320xEF, pxor, xor, 1;
+
+let isTwoAddress = 1 in {
+ def MMX_PANDNrr : MMXI0xDF, MRMSrcReg,
+ (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ pandn {$src2, $dst|$dst, $src2},
+ [(set VR64:$dst, (v2i32 (and (vnot VR64:$src1),
+ VR64:$src2)))];
+ def MMX_PANDNrm : MMXI0xDF, MRMSrcMem,
+ (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ pandn {$src2, $dst|$dst, $src2},
+ [(set VR64:$dst, (v2i32 (and (vnot VR64:$src1),
+ (load addr:$src2];
+}
+
// Move Instructions
def
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.35 - 1.36
---
Log message:
Support added for shifts and unpacking MMX instructions.
---
Diffs of the changes: (+38 -0)
IntrinsicsX86.td | 38 ++
1 files changed, 38 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.35
llvm/include/llvm/IntrinsicsX86.td:1.36
--- llvm/include/llvm/IntrinsicsX86.td:1.35 Thu Mar 15 16:24:36 2007
+++ llvm/include/llvm/IntrinsicsX86.td Thu Mar 22 13:42:45 2007
@@ -585,3 +585,41 @@
Intrinsic[llvm_v2i32_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem];
}
+
+// Integer shift ops.
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ // Shift left logical
+ def int_x86_mmx_psll_w : GCCBuiltin__builtin_ia32_psllw,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+ def int_x86_mmx_psll_d : GCCBuiltin__builtin_ia32_pslld,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+ def int_x86_mmx_psll_q : GCCBuiltin__builtin_ia32_psllq,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+
+ def int_x86_mmx_psrl_w : GCCBuiltin__builtin_ia32_psrlw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+ def int_x86_mmx_psrl_d : GCCBuiltin__builtin_ia32_psrld,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+ def int_x86_mmx_psrl_q : GCCBuiltin__builtin_ia32_psrlq,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+
+ def int_x86_mmx_psra_w : GCCBuiltin__builtin_ia32_psraw,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+ def int_x86_mmx_psra_d : GCCBuiltin__builtin_ia32_psrad,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+}
+
+// Vector pack/unpack ops.
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_mmx_punpckh_dq : GCCBuiltin__builtin_ia32_punpckhdq,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/README-MMX.txt README-SSE.txt X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
README-MMX.txt added (r1.1)
README-SSE.txt updated: 1.15 - 1.16
X86ISelLowering.cpp updated: 1.374 - 1.375
X86InstrMMX.td updated: 1.21 - 1.22
---
Log message:
Support added for shifts and unpacking MMX instructions.
---
Diffs of the changes: (+211 -2)
README-MMX.txt | 59
README-SSE.txt | 40 +++
X86ISelLowering.cpp |6 ++
X86InstrMMX.td | 108 +++-
4 files changed, 211 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/README-MMX.txt
diff -c /dev/null llvm/lib/Target/X86/README-MMX.txt:1.1
*** /dev/null Thu Mar 22 13:42:55 2007
--- llvm/lib/Target/X86/README-MMX.txt Thu Mar 22 13:42:45 2007
***
*** 0
--- 1,59
+
//===-===//
+ // Random ideas for the X86 backend: MMX-specific stuff.
+
//===-===//
+
+
//===-===//
+
+ We should compile
+
+ #include mmintrin.h
+
+ extern __m64 C;
+
+ void baz(__v2si *A, __v2si *B)
+ {
+ *A = __builtin_ia32_psllq(*B, C);
+ _mm_empty();
+ }
+
+ to:
+
+ .globl _baz
+ _baz:
+ callL3
+ L001$pb:
+ L3:
+ popl%ecx
+ subl$12, %esp
+ movl20(%esp), %eax
+ movq(%eax), %mm0
+ movlL_C$non_lazy_ptr-L001$pb(%ecx), %eax
+ movq(%eax), %mm1
+ movl16(%esp), %eax
+ psllq %mm1, %mm0
+ movq%mm0, (%eax)
+ emms
+ addl$12, %esp
+ ret
+
+ not:
+
+ _baz:
+ subl $12, %esp
+ call L1$pb
+ L1$pb:
+ popl %eax
+ movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
+ movl (%eax), %ecx
+ movl %ecx, (%esp)
+ movl 4(%eax), %eax
+ movl %eax, 4(%esp)
+ movl 20(%esp), %eax
+ movq (%eax), %mm0
+ movq (%esp), %mm1
+ psllq %mm1, %mm0
+ movl 16(%esp), %eax
+ movq %mm0, (%eax)
+ emms
+ addl $12, %esp
+ ret
Index: llvm/lib/Target/X86/README-SSE.txt
diff -u llvm/lib/Target/X86/README-SSE.txt:1.15
llvm/lib/Target/X86/README-SSE.txt:1.16
--- llvm/lib/Target/X86/README-SSE.txt:1.15 Tue Feb 27 11:21:09 2007
+++ llvm/lib/Target/X86/README-SSE.txt Thu Mar 22 13:42:45 2007
@@ -571,4 +571,44 @@
movaps %xmm0, (%eax)
ret
+//===-===//
+We should compile this:
+
+#include xmmintrin.h
+
+void foo(__m128i *A, __m128i *B) {
+ *A = _mm_sll_epi16 (*A, *B);
+}
+
+to:
+
+_foo:
+ subl$12, %esp
+ movl16(%esp), %edx
+ movl20(%esp), %eax
+ movdqa (%edx), %xmm1
+ movdqa (%eax), %xmm0
+ psllw %xmm0, %xmm1
+ movdqa %xmm1, (%edx)
+ addl$12, %esp
+ ret
+
+not:
+
+_foo:
+ movl 8(%esp), %eax
+ movdqa (%eax), %xmm0
+ #IMPLICIT_DEF %eax
+ pinsrw $2, %eax, %xmm0
+ xorl %ecx, %ecx
+ pinsrw $3, %ecx, %xmm0
+ pinsrw $4, %eax, %xmm0
+ pinsrw $5, %ecx, %xmm0
+ pinsrw $6, %eax, %xmm0
+ pinsrw $7, %ecx, %xmm0
+ movl 4(%esp), %eax
+ movdqa (%eax), %xmm1
+ psllw %xmm0, %xmm1
+ movdqa %xmm1, (%eax)
+ ret
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.374
llvm/lib/Target/X86/X86ISelLowering.cpp:1.375
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.374 Wed Mar 21 16:51:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 22 13:42:45 2007
@@ -355,6 +355,10 @@
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
+
+setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
+setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
+setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
}
if (Subtarget-hasSSE1()) {
@@ -2312,7 +2316,7 @@
return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
}
-/// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
+/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
///
static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
unsigned NumNonZero, unsigned NumZero,
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.21
llvm/lib/Target/X86/X86InstrMMX.td:1.22
--- llvm/lib/Target/X86/X86InstrMMX.td:1.21 Fri Mar 16 04:44:46 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Thu Mar 22 13:42:45 2007
@@ -44,6 +44,10 @@
def loadv2i32 : PatFrag(ops node:$ptr), (v2i32 (load node:$ptr));
+def bc_v8i8 : PatFrag(ops node:$in), (v8i8 (bitconvert node:$in));
+def
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.22 - 1.23
---
Log message:
We generate a shufflevector instruction, so we don't need the builtin
intrinsic.
---
Diffs of the changes: (+13 -6)
X86InstrMMX.td | 19 +--
1 files changed, 13 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.22
llvm/lib/Target/X86/X86InstrMMX.td:1.23
--- llvm/lib/Target/X86/X86InstrMMX.td:1.22 Thu Mar 22 13:42:45 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Thu Mar 22 15:29:26 2007
@@ -152,6 +152,16 @@
defm MMX_PMADDWD : MMXI_binop_rm_int0xF5, pmaddwd, int_x86_mmx_pmadd_wd, 1;
+// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
+// MMX_PSHUF*, MMX_SHUFP* etc. imm.
+def MMX_SHUFFLE_get_shuf_imm : SDNodeXFormbuild_vector, [{
+ return getI8Imm(X86::getShuffleSHUFImmediate(N));
+}];
+
+def MMX_splat_mask : PatLeaf(build_vector), [{
+ return X86::isSplatMask(N);
+}], MMX_SHUFFLE_get_shuf_imm;
+
def MMX_UNPCKH_shuffle_mask : PatLeaf(build_vector), [{
return X86::isUNPCKHMask(N);
}];
@@ -315,16 +325,13 @@
// Splat v2i32
let AddedComplexity = 10 in {
def : Pat(vector_shuffle (v2i32 VR64:$src), (undef),
+ MMX_splat_mask:$sm),
+(MMX_PUNPCKHDQrr VR64:$src, VR64:$src);
+ def : Pat(vector_shuffle (v2i32 VR64:$src), (undef),
MMX_UNPCKH_shuffle_mask:$sm),
(MMX_PUNPCKHDQrr VR64:$src, VR64:$src);
}
-// FIXME: Temporary workaround because 2-wide shuffle is broken.
-def : Pat(int_x86_mmx_punpckh_dq VR64:$src1, VR64:$src2),
- (v2i32 (MMX_PUNPCKHDQrr VR64:$src1, VR64:$src2));
-def : Pat(int_x86_mmx_punpckh_dq VR64:$src1, (load addr:$src2)),
- (v2i32 (MMX_PUNPCKHDQrm VR64:$src1, addr:$src2));
-
def MMX_X86s2vec : SDNodeX86ISD::S2VEC, SDTypeProfile1, 1, [], [];
// Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower 8 or
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.36 - 1.37
---
Log message:
We generate a shufflevector instruction, so we don't need the builtin
intrinsic.
---
Diffs of the changes: (+0 -7)
IntrinsicsX86.td |7 ---
1 files changed, 7 deletions(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.36
llvm/include/llvm/IntrinsicsX86.td:1.37
--- llvm/include/llvm/IntrinsicsX86.td:1.36 Thu Mar 22 13:42:45 2007
+++ llvm/include/llvm/IntrinsicsX86.td Thu Mar 22 15:29:26 2007
@@ -616,10 +616,3 @@
Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v2i32_ty], [IntrNoMem];
}
-
-// Vector pack/unpack ops.
-let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
- def int_x86_mmx_punpckh_dq : GCCBuiltin__builtin_ia32_punpckhdq,
- Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
- llvm_v2i32_ty], [IntrNoMem];
-}
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.37 - 1.38
---
Log message:
PR1260: http://llvm.org/PR1260 :
Add final support to get the QT example to compile.
---
Diffs of the changes: (+20 -4)
IntrinsicsX86.td | 24
1 files changed, 20 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.37
llvm/include/llvm/IntrinsicsX86.td:1.38
--- llvm/include/llvm/IntrinsicsX86.td:1.37 Thu Mar 22 15:29:26 2007
+++ llvm/include/llvm/IntrinsicsX86.td Fri Mar 23 17:35:46 2007
@@ -581,6 +581,9 @@
def int_x86_mmx_pmulh_w : GCCBuiltin__builtin_ia32_pmulhw,
Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem];
+ def int_x86_mmx_pmull_w : GCCBuiltin__builtin_ia32_pmullw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
def int_x86_mmx_pmadd_wd : GCCBuiltin__builtin_ia32_pmaddwd,
Intrinsic[llvm_v2i32_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem];
@@ -590,10 +593,10 @@
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
// Shift left logical
def int_x86_mmx_psll_w : GCCBuiltin__builtin_ia32_psllw,
- Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v2i32_ty], [IntrNoMem];
def int_x86_mmx_psll_d : GCCBuiltin__builtin_ia32_pslld,
- Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v2i32_ty], [IntrNoMem];
def int_x86_mmx_psll_q : GCCBuiltin__builtin_ia32_psllq,
Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
@@ -610,9 +613,22 @@
llvm_v2i32_ty], [IntrNoMem];
def int_x86_mmx_psra_w : GCCBuiltin__builtin_ia32_psraw,
- Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v2i32_ty], [IntrNoMem];
def int_x86_mmx_psra_d : GCCBuiltin__builtin_ia32_psrad,
- Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v2i32_ty], [IntrNoMem];
}
+
+// Pack ops.
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_mmx_packsswb : GCCBuiltin__builtin_ia32_packsswb,
+ Intrinsic[llvm_v8i8_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+ def int_x86_mmx_packssdw : GCCBuiltin__builtin_ia32_packssdw,
+ Intrinsic[llvm_v4i16_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+ def int_x86_mmx_packuswb : GCCBuiltin__builtin_ia32_packuswb,
+ Intrinsic[llvm_v8i8_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.23 - 1.24
---
Log message:
PR1260: http://llvm.org/PR1260 :
Add final support to get the QT example to compile.
---
Diffs of the changes: (+6 -2)
X86InstrMMX.td |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.23
llvm/lib/Target/X86/X86InstrMMX.td:1.24
--- llvm/lib/Target/X86/X86InstrMMX.td:1.23 Thu Mar 22 15:29:26 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Fri Mar 23 17:35:46 2007
@@ -23,7 +23,7 @@
class MMXIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, TB, Requires[HasMMX];
class MMX2Ibits8 o, Format F, dag ops, string asm, listdag pattern
- : Io, F, ops, asm, pattern, TB, OpSize, Requires[HasSSE2];
+ : Io, F, ops, asm, pattern, TB, OpSize, Requires[HasMMX];
class MMXIi8bits8 o, Format F, dag ops, string asm, listdag pattern
: Ii8o, F, ops, asm, pattern, TB, Requires[HasMMX];
@@ -151,7 +151,6 @@
defm MMX_PMULHW : MMXI_binop_rm_int0xE5, pmulhw , int_x86_mmx_pmulh_w , 1;
defm MMX_PMADDWD : MMXI_binop_rm_int0xF5, pmaddwd, int_x86_mmx_pmadd_wd, 1;
-
// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
// MMX_PSHUF*, MMX_SHUFP* etc. imm.
def MMX_SHUFFLE_get_shuf_imm : SDNodeXFormbuild_vector, [{
@@ -246,6 +245,11 @@
defm MMX_PSRAD : MMXI_binop_rmi_int0xE2, 0x72, MRM4r, psrad,
int_x86_mmx_psra_d;
+// Pack instructions
+defm MMX_PACKSSWB : MMXI_binop_rm_int0x63, packsswb, int_x86_mmx_packsswb;
+defm MMX_PACKSSDW : MMXI_binop_rm_int0x6B, packssdw, int_x86_mmx_packssdw;
+defm MMX_PACKUSWB : MMXI_binop_rm_int0x67, packuswb, int_x86_mmx_packuswb;
+
// Move Instructions
def MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
movd {$src, $dst|$dst, $src}, [];
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.38 - 1.39 --- Log message: This is dead. DEAD I tells you!! --- Diffs of the changes: (+0 -3) IntrinsicsX86.td |3 --- 1 files changed, 3 deletions(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.38 llvm/include/llvm/IntrinsicsX86.td:1.39 --- llvm/include/llvm/IntrinsicsX86.td:1.38 Fri Mar 23 17:35:46 2007 +++ llvm/include/llvm/IntrinsicsX86.td Fri Mar 23 17:42:04 2007 @@ -581,9 +581,6 @@ def int_x86_mmx_pmulh_w : GCCBuiltin__builtin_ia32_pmulhw, Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]; - def int_x86_mmx_pmull_w : GCCBuiltin__builtin_ia32_pmullw, - Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty, - llvm_v4i16_ty], [IntrNoMem]; def int_x86_mmx_pmadd_wd : GCCBuiltin__builtin_ia32_pmaddwd, Intrinsic[llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.86 - 1.87
---
Log message:
Add support for the v1i64 type. This makes better code for this:
#include mmintrin.h
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call L1$pb
L1$pb:
popl %eax
movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
callL3
L001$pb:
L3:
popl%ebx
subl$8, %esp
movlL_C$non_lazy_ptr-L001$pb(%ebx), %eax
movl(%eax), %edx
movl4(%eax), %ecx
movl16(%esp), %eax
movl%edx, (%eax)
movl%ecx, 4(%eax)
emms
addl$8, %esp
popl%ebx
ret
---
Diffs of the changes: (+2 -0)
CodeGenTarget.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.86
llvm/utils/TableGen/CodeGenTarget.cpp:1.87
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.86 Mon Mar 19 01:20:37 2007
+++ llvm/utils/TableGen/CodeGenTarget.cpp Mon Mar 26 02:53:08 2007
@@ -52,6 +52,7 @@
case MVT::v8i8: return MVT::v8i8;
case MVT::v4i16: return MVT::v4i16;
case MVT::v2i32: return MVT::v2i32;
+ case MVT::v1i64: return MVT::v1i64;
case MVT::v16i8: return MVT::v16i8;
case MVT::v8i16: return MVT::v8i16;
case MVT::v4i32: return MVT::v4i32;
@@ -82,6 +83,7 @@
case MVT::v8i8: return MVT::v8i8;
case MVT::v4i16: return MVT::v4i16;
case MVT::v2i32: return MVT::v2i32;
+ case MVT::v1i64: return MVT::v1i64;
case MVT::v16i8: return MVT::v16i8;
case MVT::v8i16: return MVT::v8i16;
case MVT::v4i32: return MVT::v4i32;
___
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[llvm-commits] CVS: llvm/include/llvm/Intrinsics.td
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.50 - 1.51
---
Log message:
Add support for the v1i64 type. This makes better code for this:
#include mmintrin.h
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call L1$pb
L1$pb:
popl %eax
movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
callL3
L001$pb:
L3:
popl%ebx
subl$8, %esp
movlL_C$non_lazy_ptr-L001$pb(%ebx), %eax
movl(%eax), %edx
movl4(%eax), %ecx
movl16(%esp), %eax
movl%edx, (%eax)
movl%ecx, 4(%eax)
emms
addl$8, %esp
popl%ebx
ret
---
Diffs of the changes: (+1 -0)
Intrinsics.td |1 +
1 files changed, 1 insertion(+)
Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.50
llvm/include/llvm/Intrinsics.td:1.51
--- llvm/include/llvm/Intrinsics.td:1.50Thu Mar 8 16:09:11 2007
+++ llvm/include/llvm/Intrinsics.td Mon Mar 26 02:53:08 2007
@@ -94,6 +94,7 @@
def llvm_v8i16_ty : LLVMVectorTypev8i16, 8, llvm_i16_ty; // 8 x i16
def llvm_v2i64_ty : LLVMVectorTypev2i64, 2, llvm_i64_ty; // 2 x i64
def llvm_v2i32_ty : LLVMVectorTypev2i32, 2, llvm_i32_ty; // 2 x i32
+def llvm_v1i64_ty : LLVMVectorTypev1i64, 1, llvm_i64_ty; // 1 x i64
def llvm_v4i32_ty : LLVMVectorTypev4i32, 4, llvm_i32_ty; // 4 x i32
def llvm_v4f32_ty : LLVMVectorTypev4f32, 4, llvm_float_ty; // 4 x float
def llvm_v2f64_ty : LLVMVectorTypev2f64, 2, llvm_double_ty;// 2 x
double
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.377 - 1.378
X86InstrMMX.td updated: 1.24 - 1.25
X86RegisterInfo.td updated: 1.40 - 1.41
---
Log message:
Add support for the v1i64 type. This makes better code for this:
#include mmintrin.h
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call L1$pb
L1$pb:
popl %eax
movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
callL3
L001$pb:
L3:
popl%ebx
subl$8, %esp
movlL_C$non_lazy_ptr-L001$pb(%ebx), %eax
movl(%eax), %edx
movl4(%eax), %ecx
movl16(%esp), %eax
movl%edx, (%eax)
movl%ecx, 4(%eax)
emms
addl$8, %esp
popl%ebx
ret
---
Diffs of the changes: (+58 -28)
X86ISelLowering.cpp |9 --
X86InstrMMX.td | 75 +++-
X86RegisterInfo.td |2 -
3 files changed, 58 insertions(+), 28 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.377
llvm/lib/Target/X86/X86ISelLowering.cpp:1.378
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.377 Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 26 02:53:08 2007
@@ -314,6 +314,7 @@
addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
+addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
@@ -347,10 +348,12 @@
setOperationAction(ISD::XOR,MVT::v2i32, Legal);
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
+AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
-setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
+AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
+setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
+AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
+setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.24
llvm/lib/Target/X86/X86InstrMMX.td:1.25
--- llvm/lib/Target/X86/X86InstrMMX.td:1.24 Fri Mar 23 17:35:46 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Mon Mar 26 02:53:08 2007
@@ -37,12 +37,13 @@
def : Pat(v8i8 (undef)), (IMPLICIT_DEF_VR64);
def : Pat(v4i16 (undef)), (IMPLICIT_DEF_VR64);
def : Pat(v2i32 (undef)), (IMPLICIT_DEF_VR64);
+def : Pat(v1i64 (undef)), (IMPLICIT_DEF_VR64);
//===--===//
// MMX Pattern Fragments
//===--===//
-def loadv2i32 : PatFrag(ops node:$ptr), (v2i32 (load node:$ptr));
+def loadv1i64 : PatFrag(ops node:$ptr), (v1i64 (load node:$ptr));
def bc_v8i8 : PatFrag(ops node:$in), (v8i8 (bitconvert node:$in));
def bc_v4i16 : PatFrag(ops node:$in), (v4i16 (bitconvert node:$in));
@@ -65,7 +66,7 @@
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
(bitconvert
- (loadv2i32 addr:$src2)];
+ (loadv1i64 addr:$src2)];
}
multiclass MMXI_binop_rm_intbits8 opc, string OpcodeStr, Intrinsic IntId,
@@ -78,25 +79,25 @@
def rm : MMXIopc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (IntId VR64:$src1,
- (bitconvert (loadv2i32 addr:$src2];
+ (bitconvert (loadv1i64 addr:$src2];
}
- // MMXI_binop_rm_v2i32 - Simple MMX binary operator whose type is v2i32.
+ // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
//
// FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen
knew
// to collapse (bitconvert VT to VT) into its operand.
//
- multiclass MMXI_binop_rm_v2i32bits8 opc, string OpcodeStr, SDNode OpNode,
+ multiclass MMXI_binop_rm_v1i64bits8 opc, string OpcodeStr, SDNode
[llvm-commits] CVS: llvm/lib/Target/X86/README-MMX.txt
Changes in directory llvm/lib/Target/X86:
README-MMX.txt updated: 1.1 - 1.2
---
Log message:
Updated.
---
Diffs of the changes: (+0 -54)
README-MMX.txt | 54 --
1 files changed, 54 deletions(-)
Index: llvm/lib/Target/X86/README-MMX.txt
diff -u llvm/lib/Target/X86/README-MMX.txt:1.1
llvm/lib/Target/X86/README-MMX.txt:1.2
--- llvm/lib/Target/X86/README-MMX.txt:1.1 Thu Mar 22 13:42:45 2007
+++ llvm/lib/Target/X86/README-MMX.txt Mon Mar 26 02:55:58 2007
@@ -3,57 +3,3 @@
//===-===//
//===-===//
-
-We should compile
-
-#include mmintrin.h
-
-extern __m64 C;
-
-void baz(__v2si *A, __v2si *B)
-{
- *A = __builtin_ia32_psllq(*B, C);
- _mm_empty();
-}
-
-to:
-
-.globl _baz
-_baz:
- callL3
-L001$pb:
-L3:
- popl%ecx
- subl$12, %esp
- movl20(%esp), %eax
- movq(%eax), %mm0
- movlL_C$non_lazy_ptr-L001$pb(%ecx), %eax
- movq(%eax), %mm1
- movl16(%esp), %eax
- psllq %mm1, %mm0
- movq%mm0, (%eax)
- emms
- addl$12, %esp
- ret
-
-not:
-
-_baz:
- subl $12, %esp
- call L1$pb
-L1$pb:
- popl %eax
- movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
- movl (%eax), %ecx
- movl %ecx, (%esp)
- movl 4(%eax), %eax
- movl %eax, 4(%esp)
- movl 20(%esp), %eax
- movq (%eax), %mm0
- movq (%esp), %mm1
- psllq %mm1, %mm0
- movl 16(%esp), %eax
- movq %mm0, (%eax)
- emms
- addl $12, %esp
- ret
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.378 - 1.379 --- Log message: Promote to v1i64 type... --- Diffs of the changes: (+15 -9) X86ISelLowering.cpp | 24 +++- 1 files changed, 15 insertions(+), 9 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.378 llvm/lib/Target/X86/X86ISelLowering.cpp:1.379 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.378 Mon Mar 26 02:53:08 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 26 03:03:33 2007 @@ -330,22 +330,28 @@ setOperationAction(ISD::MUL,MVT::v4i16, Legal); setOperationAction(ISD::AND,MVT::v8i8, Promote); -AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v1i64); setOperationAction(ISD::AND,MVT::v4i16, Promote); -AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::AND,MVT::v2i32, Legal); +AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::AND,MVT::v2i32, Promote); +AddPromotedToType (ISD::AND,MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::AND,MVT::v1i64, Legal); setOperationAction(ISD::OR, MVT::v8i8, Promote); -AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); setOperationAction(ISD::OR, MVT::v4i16, Promote); -AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::OR, MVT::v2i32, Legal); +AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::OR, MVT::v2i32, Promote); +AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::OR, MVT::v1i64, Legal); setOperationAction(ISD::XOR,MVT::v8i8, Promote); -AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v1i64); setOperationAction(ISD::XOR,MVT::v4i16, Promote); -AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::XOR,MVT::v2i32, Legal); +AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::XOR,MVT::v2i32, Promote); +AddPromotedToType (ISD::XOR,MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::XOR,MVT::v1i64, Legal); setOperationAction(ISD::LOAD, MVT::v8i8, Promote); AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.39 - 1.40
---
Log message:
Add support for integer comparison builtins.
---
Diffs of the changes: (+23 -0)
IntrinsicsX86.td | 23 +++
1 files changed, 23 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.39
llvm/include/llvm/IntrinsicsX86.td:1.40
--- llvm/include/llvm/IntrinsicsX86.td:1.39 Fri Mar 23 17:42:04 2007
+++ llvm/include/llvm/IntrinsicsX86.td Tue Mar 27 15:21:31 2007
@@ -629,3 +629,26 @@
Intrinsic[llvm_v8i8_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem];
}
+
+// Integer comparison ops
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_mmx_pcmpeq_b : GCCBuiltin__builtin_ia32_pcmpeqb,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
+ def int_x86_mmx_pcmpeq_w : GCCBuiltin__builtin_ia32_pcmpeqw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+ def int_x86_mmx_pcmpeq_d : GCCBuiltin__builtin_ia32_pcmpeqd,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+
+ def int_x86_mmx_pcmpgt_b : GCCBuiltin__builtin_ia32_pcmpgtb,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
+ def int_x86_mmx_pcmpgt_w : GCCBuiltin__builtin_ia32_pcmpgtw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+ def int_x86_mmx_pcmpgt_d : GCCBuiltin__builtin_ia32_pcmpgtd,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
+}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.379 - 1.380
X86InstrMMX.td updated: 1.25 - 1.26
---
Log message:
Fix so that pandn is emitted instead of an xor/and combo. Add integer
comparison operators.
---
Diffs of the changes: (+55 -13)
X86ISelLowering.cpp |8 --
X86InstrMMX.td | 60 +++-
2 files changed, 55 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.379
llvm/lib/Target/X86/X86ISelLowering.cpp:1.380
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.379 Mon Mar 26 03:03:33 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 27 15:22:40 2007
@@ -361,13 +361,15 @@
AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
+setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
}
if (Subtarget-hasSSE1()) {
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.25
llvm/lib/Target/X86/X86InstrMMX.td:1.26
--- llvm/lib/Target/X86/X86InstrMMX.td:1.25 Mon Mar 26 02:53:08 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 27 15:22:40 2007
@@ -43,11 +43,12 @@
// MMX Pattern Fragments
//===--===//
-def loadv1i64 : PatFrag(ops node:$ptr), (v1i64 (load node:$ptr));
+def load_mmx : PatFrag(ops node:$ptr), (v1i64 (load node:$ptr));
def bc_v8i8 : PatFrag(ops node:$in), (v8i8 (bitconvert node:$in));
def bc_v4i16 : PatFrag(ops node:$in), (v4i16 (bitconvert node:$in));
def bc_v2i32 : PatFrag(ops node:$in), (v2i32 (bitconvert node:$in));
+def bc_v1i64 : PatFrag(ops node:$in), (v1i64 (bitconvert node:$in));
//===--===//
// MMX Multiclasses
@@ -66,7 +67,7 @@
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
(bitconvert
- (loadv1i64 addr:$src2)];
+ (load_mmx addr:$src2)];
}
multiclass MMXI_binop_rm_intbits8 opc, string OpcodeStr, Intrinsic IntId,
@@ -79,7 +80,7 @@
def rm : MMXIopc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (IntId VR64:$src1,
- (bitconvert (loadv1i64 addr:$src2];
+ (bitconvert (load_mmx addr:$src2];
}
// MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
@@ -97,7 +98,7 @@
def rm : MMXIopc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst,
-(OpNode VR64:$src1,(loadv1i64 addr:$src2)))];
+(OpNode VR64:$src1,(load_mmx addr:$src2)))];
}
multiclass MMXI_binop_rmi_intbits8 opc, bits8 opc2, Format ImmForm,
@@ -108,7 +109,7 @@
def rm : MMXIopc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (IntId VR64:$src1,
-(bitconvert (loadv1i64 addr:$src2];
+(bitconvert (load_mmx addr:$src2];
def ri : MMXIi8opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (IntId VR64:$src1,
@@ -178,7 +179,7 @@
punpckhbw {$src2, $dst|$dst, $src2},
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1,
-(bc_v8i8 (loadv1i64 addr:$src2)),
+(bc_v8i8 (load_mmx addr:$src2)),
MMX_UNPCKH_shuffle_mask)))];
def MMX_PUNPCKHWDrr : MMXI0x69, MRMSrcReg,
[llvm-commits] CVS: llvm/utils/emacs/tablegen-mode.el
Changes in directory llvm/utils/emacs: tablegen-mode.el updated: 1.2 - 1.3 --- Log message: Add better support for keywords. --- Diffs of the changes: (+40 -21) tablegen-mode.el | 61 --- 1 files changed, 40 insertions(+), 21 deletions(-) Index: llvm/utils/emacs/tablegen-mode.el diff -u llvm/utils/emacs/tablegen-mode.el:1.2 llvm/utils/emacs/tablegen-mode.el:1.3 --- llvm/utils/emacs/tablegen-mode.el:1.2 Mon Mar 13 23:54:52 2006 +++ llvm/utils/emacs/tablegen-mode.el Tue Mar 27 15:23:56 2007 @@ -1,32 +1,51 @@ ;; Maintainer: The LLVM team, http://llvm.org/ ;; Description: Major mode for TableGen description files (part of LLVM project) -;; Updated: 2003-08-11 +;; Updated: 2007-03-26 + +(require 'comint) +(require 'custom) +(require 'ansi-color) ;; Create mode-specific tables. (defvar tablegen-mode-syntax-table nil Syntax table used while in TableGen mode.) +(defvar td-decorators-face 'td-decorators-face + Face method decorators.) +(make-face 'td-decorators-face) + (defvar tablegen-font-lock-keywords - (list - ;; Comments - '(\/\/.* . font-lock-comment-face) - ;; Strings - '(\[^\]+\ . font-lock-string-face) - ;; Hex constants - '(0x[0-9A-Fa-f]+ . font-lock-preprocessor-face) - ;; Binary constants - '(0b[01]+ . font-lock-preprocessor-face) - ;; Integer literals - '([-]?[0-9]+ . font-lock-preprocessor-face) - ;; Floating point constants - '([-+]?[0-9]+\.[0-9]*\([eE][-+]?[0-9]+\)? . font-lock-preprocessor-face) - ;; Keywords - '(include\\|def\\|let\\|in\\|code\\|dag\\|field . font-lock-keyword-face) - ;; Types - '(class\\|int\\|string\\|list\\|bits? . font-lock-type-face) - ) - Syntax highlighting for TableGen - ) + (let ((kw (mapconcat 'identity + '(class def defm field in include + let multiclass) + \\|)) +(type-kw (mapconcat 'identity +'(bit bits code dag int list string) +\\|)) +) +(list + ;; Comments + '(\/\/ . font-lock-comment-face) + ;; Strings + '(\[^\]+\ . font-lock-string-face) + ;; Hex constants + '(0x[0-9A-Fa-f]+ . font-lock-preprocessor-face) + ;; Binary constants + '(0b[01]+ . font-lock-preprocessor-face) + ;; Integer literals + '([-]?[0-9]+ . font-lock-preprocessor-face) + ;; Floating point constants + '([-+]?[0-9]+\.[0-9]*\([eE][-+]?[0-9]+\)? . font-lock-preprocessor-face) + + '(^[ \t]*\\(@.+\\) 1 'td-decorators-face) + ;; Keywords + (cons (concat ( kw \\)\\[ \n\t(]) 1) + + ;; Type keywords + (cons (concat ( type-kw \\)[ \n\t(]) 1) + )) + Additional expressions to highlight in TableGen mode.) +(put 'tablegen-mode 'font-lock-defaults '(tablegen-font-lock-keywords)) ;; -- Syntax table --- ;; Shamelessly ripped from jasmin.el ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.26 - 1.27
---
Log message:
Add the unpack low packed data instructions. This should be the last of
the MMX instructions that are needed...
---
Diffs of the changes: (+130 -73)
X86InstrMMX.td | 203 -
1 files changed, 130 insertions(+), 73 deletions(-)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.26
llvm/lib/Target/X86/X86InstrMMX.td:1.27
--- llvm/lib/Target/X86/X86InstrMMX.td:1.26 Tue Mar 27 15:22:40 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 27 16:20:36 2007
@@ -2,8 +2,8 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the Evan Cheng and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file was developed by the Evan Cheng and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===--===//
//
@@ -128,6 +128,8 @@
//===--===//
// Arithmetic Instructions
+
+// -- Addition
defm MMX_PADDB : MMXI_binop_rm0xFC, paddb, add, v8i8, 1;
defm MMX_PADDW : MMXI_binop_rm0xFD, paddw, add, v4i16, 1;
defm MMX_PADDD : MMXI_binop_rm0xFE, paddd, add, v2i32, 1;
@@ -138,6 +140,7 @@
defm MMX_PADDUSB : MMXI_binop_rm_int0xDC, paddusb, int_x86_mmx_paddus_b, 1;
defm MMX_PADDUSW : MMXI_binop_rm_int0xDD, paddusw, int_x86_mmx_paddus_w, 1;
+// -- Subtraction
defm MMX_PSUBB : MMXI_binop_rm0xF8, psubb, sub, v8i8;
defm MMX_PSUBW : MMXI_binop_rm0xF9, psubw, sub, v4i16;
defm MMX_PSUBD : MMXI_binop_rm0xFA, psubd, sub, v2i32;
@@ -148,66 +151,12 @@
defm MMX_PSUBUSB : MMXI_binop_rm_int0xD8, psubusb, int_x86_mmx_psubus_b;
defm MMX_PSUBUSW : MMXI_binop_rm_int0xD9, psubusw, int_x86_mmx_psubus_w;
+// -- Multiplication
defm MMX_PMULLW : MMXI_binop_rm0xD5, pmullw, mul, v4i16, 1;
-
defm MMX_PMULHW : MMXI_binop_rm_int0xE5, pmulhw , int_x86_mmx_pmulh_w , 1;
-defm MMX_PMADDWD : MMXI_binop_rm_int0xF5, pmaddwd, int_x86_mmx_pmadd_wd, 1;
-
-// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
-// MMX_PSHUF*, MMX_SHUFP* etc. imm.
-def MMX_SHUFFLE_get_shuf_imm : SDNodeXFormbuild_vector, [{
- return getI8Imm(X86::getShuffleSHUFImmediate(N));
-}];
-
-def MMX_splat_mask : PatLeaf(build_vector), [{
- return X86::isSplatMask(N);
-}], MMX_SHUFFLE_get_shuf_imm;
-
-def MMX_UNPCKH_shuffle_mask : PatLeaf(build_vector), [{
- return X86::isUNPCKHMask(N);
-}];
-let isTwoAddress = 1 in {
-def MMX_PUNPCKHBWrr : MMXI0x68, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
- punpckhbw {$src2, $dst|$dst, $src2},
- [(set VR64:$dst,
- (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
-MMX_UNPCKH_shuffle_mask)))];
-def MMX_PUNPCKHBWrm : MMXI0x68, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
- punpckhbw {$src2, $dst|$dst, $src2},
- [(set VR64:$dst,
- (v8i8 (vector_shuffle VR64:$src1,
-(bc_v8i8 (load_mmx addr:$src2)),
-MMX_UNPCKH_shuffle_mask)))];
-def MMX_PUNPCKHWDrr : MMXI0x69, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
- punpckhwd {$src2, $dst|$dst, $src2},
- [(set VR64:$dst,
- (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
- MMX_UNPCKH_shuffle_mask)))];
-def MMX_PUNPCKHWDrm : MMXI0x69, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
- punpckhwd {$src2, $dst|$dst, $src2},
- [(set VR64:$dst,
- (v4i16 (vector_shuffle VR64:$src1,
- (bc_v4i16 (load_mmx addr:$src2)),
- MMX_UNPCKH_shuffle_mask)))];
-def MMX_PUNPCKHDQrr : MMXI0x6A, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
- punpckhdq {$src2, $dst|$dst, $src2},
- [(set VR64:$dst,
- (v1i64 (vector_shuffle VR64:$src1, VR64:$src2,
- MMX_UNPCKH_shuffle_mask)))];
-def MMX_PUNPCKHDQrm : MMXI0x6A, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
- punpckhdq {$src2, $dst|$dst, $src2},
- [(set VR64:$dst,
- (v1i64 (vector_shuffle VR64:$src1,
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.381 - 1.382
---
Log message:
Remove cruft I put in there...
---
Diffs of the changes: (+0 -72)
X86ISelLowering.cpp | 72
1 files changed, 72 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.381
llvm/lib/Target/X86/X86ISelLowering.cpp:1.382
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.381 Tue Mar 27 19:57:11 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 27 20:02:54 2007
@@ -2286,78 +2286,6 @@
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
}
-/// LowerBuildVectorv8i8 - Custom lower build_vector of v8i8.
-///
-static SDOperand LowerBuildVectorv8i8(SDOperand Op, unsigned NonZeros,
- unsigned NumNonZero, unsigned NumZero,
- SelectionDAG DAG, TargetLowering TLI) {
- if (NumNonZero 8)
-return SDOperand();
-
- SDOperand V(0, 0);
- bool First = true;
- for (unsigned i = 0; i 8; ++i) {
-bool ThisIsNonZero = (NonZeros (1 i)) != 0;
-if (ThisIsNonZero First) {
- if (NumZero)
-V = getZeroVector(MVT::v4i16, DAG);
- else
-V = DAG.getNode(ISD::UNDEF, MVT::v4i16);
- First = false;
-}
-
-if ((i 1) != 0) {
- SDOperand ThisElt(0, 0), LastElt(0, 0);
- bool LastIsNonZero = (NonZeros (1 (i-1))) != 0;
- if (LastIsNonZero) {
-LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
- }
- if (ThisIsNonZero) {
-ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
-ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
- ThisElt, DAG.getConstant(8, MVT::i8));
-if (LastIsNonZero)
- ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
- } else
-ThisElt = LastElt;
-
- if (ThisElt.Val)
-V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v4i16, V, ThisElt,
-DAG.getConstant(i/2, TLI.getPointerTy()));
-}
- }
-
- return DAG.getNode(ISD::BIT_CONVERT, MVT::v8i8, V);
-}
-
-/// LowerBuildVectorv4i16 - Custom lower build_vector of v4i16.
-///
-static SDOperand LowerBuildVectorv4i16(SDOperand Op, unsigned NonZeros,
- unsigned NumNonZero, unsigned NumZero,
- SelectionDAG DAG, TargetLowering TLI)
{
- if (NumNonZero 4)
-return SDOperand();
-
- SDOperand V(0, 0);
- bool First = true;
- for (unsigned i = 0; i 4; ++i) {
-bool isNonZero = (NonZeros (1 i)) != 0;
-if (isNonZero) {
- if (First) {
-if (NumZero)
- V = getZeroVector(MVT::v4i16, DAG);
-else
- V = DAG.getNode(ISD::UNDEF, MVT::v4i16);
-First = false;
- }
- V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v4i16, V, Op.getOperand(i),
- DAG.getConstant(i, TLI.getPointerTy()));
-}
- }
-
- return V;
-}
-
/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
///
static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/README-SSE.txt
Changes in directory llvm/lib/Target/X86:
README-SSE.txt updated: 1.16 - 1.17
---
Log message:
Made this into a bug report: PR1286: http://llvm.org/PR1286
---
Diffs of the changes: (+0 -40)
README-SSE.txt | 40
1 files changed, 40 deletions(-)
Index: llvm/lib/Target/X86/README-SSE.txt
diff -u llvm/lib/Target/X86/README-SSE.txt:1.16
llvm/lib/Target/X86/README-SSE.txt:1.17
--- llvm/lib/Target/X86/README-SSE.txt:1.16 Thu Mar 22 13:42:45 2007
+++ llvm/lib/Target/X86/README-SSE.txt Wed Mar 28 14:07:34 2007
@@ -572,43 +572,3 @@
ret
//===-===//
-
-We should compile this:
-
-#include xmmintrin.h
-
-void foo(__m128i *A, __m128i *B) {
- *A = _mm_sll_epi16 (*A, *B);
-}
-
-to:
-
-_foo:
- subl$12, %esp
- movl16(%esp), %edx
- movl20(%esp), %eax
- movdqa (%edx), %xmm1
- movdqa (%eax), %xmm0
- psllw %xmm0, %xmm1
- movdqa %xmm1, (%edx)
- addl$12, %esp
- ret
-
-not:
-
-_foo:
- movl 8(%esp), %eax
- movdqa (%eax), %xmm0
- #IMPLICIT_DEF %eax
- pinsrw $2, %eax, %xmm0
- xorl %ecx, %ecx
- pinsrw $3, %ecx, %xmm0
- pinsrw $4, %eax, %xmm0
- pinsrw $5, %ecx, %xmm0
- pinsrw $6, %eax, %xmm0
- pinsrw $7, %ecx, %xmm0
- movl 4(%esp), %eax
- movdqa (%eax), %xmm1
- psllw %xmm0, %xmm1
- movdqa %xmm1, (%eax)
- ret
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td
Changes in directory llvm/lib/Target/X86: X86CallingConv.td updated: 1.10 - 1.11 --- Log message: Add MMX calling conventions. --- Diffs of the changes: (+14 -4) X86CallingConv.td | 18 ++ 1 files changed, 14 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86CallingConv.td diff -u llvm/lib/Target/X86/X86CallingConv.td:1.10 llvm/lib/Target/X86/X86CallingConv.td:1.11 --- llvm/lib/Target/X86/X86CallingConv.td:1.10 Wed Feb 28 12:35:11 2007 +++ llvm/lib/Target/X86/X86CallingConv.td Thu Mar 29 19:35:22 2007 @@ -30,7 +30,11 @@ // Vector types are always returned in XMM0. If the target doesn't have XMM0, // it won't have vector types. - CCIfType[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg[XMM0] + CCIfType[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg[XMM0], + + // MMX vector types are always returned in MM0. If the target doesn't have + // MM0, it doesn't support these vector types. + CCIfType[v8i8, v4i16, v2i32, v1i64], CCAssignToReg[MM0] ]; // X86-32 C return-value convention. @@ -102,8 +106,10 @@ CCIfType[i32, i64, f32, f64], CCAssignToStack8, 8, // Vectors get 16-byte stack slots that are 16-byte aligned. - CCIfType[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], - CCAssignToStack16, 16 + CCIfType[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack16, 16, + + // __m64 vectors get 8-byte stack slots that are 8-byte aligned. + CCIfType[v8i8, v4i16, v2i32, v1i64], CCAssignToStack8, 8 ]; @@ -127,7 +133,11 @@ CCAssignToReg[XMM0, XMM1, XMM2, XMM3], // Other vectors get 16-byte stack slots that are 16-byte aligned. - CCIfType[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack16, 16 + CCIfType[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack16, 16, + + // __m64 vectors get 8-byte stack slots that are 8-byte aligned. They are + // passed in the parameter area. + CCIfType[v8i8, v4i16, v2i32, v1i64], CCAssignToStack8, 8 ]; def CC_X86_32_C : CallingConv[ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td
Changes in directory llvm/lib/Target/X86: X86CallingConv.td updated: 1.11 - 1.12 --- Log message: Match GCC's MMX calling convention. --- Diffs of the changes: (+4 -0) X86CallingConv.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/X86/X86CallingConv.td diff -u llvm/lib/Target/X86/X86CallingConv.td:1.11 llvm/lib/Target/X86/X86CallingConv.td:1.12 --- llvm/lib/Target/X86/X86CallingConv.td:1.11 Thu Mar 29 19:35:22 2007 +++ llvm/lib/Target/X86/X86CallingConv.td Fri Mar 30 20:03:53 2007 @@ -101,6 +101,10 @@ CCIfType[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], + // The first 8 MMX vector arguments are passed in MMX registers. + CCIfType[v8i8, v4i16, v2i32, v1i64], + CCAssignToReg[RDI, RSI, RDX, RCX, R8 , R9 ], + // Integer/FP values get stored in stack slots that are 8 bytes in size and // 8-byte aligned if there are no more registers to hold them. CCIfType[i32, i64, f32, f64], CCAssignToStack8, 8, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td
Changes in directory llvm/lib/Target/X86: X86CallingConv.td updated: 1.12 - 1.13 --- Log message: Fix comment. --- Diffs of the changes: (+1 -1) X86CallingConv.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86CallingConv.td diff -u llvm/lib/Target/X86/X86CallingConv.td:1.12 llvm/lib/Target/X86/X86CallingConv.td:1.13 --- llvm/lib/Target/X86/X86CallingConv.td:1.12 Fri Mar 30 20:03:53 2007 +++ llvm/lib/Target/X86/X86CallingConv.td Sat Mar 31 04:36:12 2007 @@ -101,7 +101,7 @@ CCIfType[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], - // The first 8 MMX vector arguments are passed in MMX registers. + // The first 8 MMX vector arguments are passed in GPRs. CCIfType[v8i8, v4i16, v2i32, v1i64], CCAssignToReg[RDI, RSI, RDX, RCX, R8 , R9 ], ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.40 - 1.41
---
Log message:
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
---
Diffs of the changes: (+3 -1)
IntrinsicsX86.td |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.40
llvm/include/llvm/IntrinsicsX86.td:1.41
--- llvm/include/llvm/IntrinsicsX86.td:1.40 Tue Mar 27 15:21:31 2007
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 3 01:00:36 2007
@@ -541,7 +541,9 @@
// Empty MMX state op.
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
- def int_x86_mmx_emms : GCCBuiltin__builtin_ia32_emms,
+ def int_x86_mmx_emms : GCCBuiltin__builtin_ia32_emms,
+ Intrinsic[llvm_void_ty], [IntrWriteMem];
+ def int_x86_mmx_femms : GCCBuiltin__builtin_ia32_femms,
Intrinsic[llvm_void_ty], [IntrWriteMem];
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.81 - 1.82
X86InstrMMX.td updated: 1.28 - 1.29
---
Log message:
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
---
Diffs of the changes: (+85 -69)
X86InstrInfo.cpp | 10 +--
X86InstrMMX.td | 144 ++-
2 files changed, 85 insertions(+), 69 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.81
llvm/lib/Target/X86/X86InstrInfo.cpp:1.82
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.81 Wed Mar 28 13:12:31 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Apr 3 01:00:37 2007
@@ -38,7 +38,7 @@
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
- oc == X86::MOVD64rr || oc == X86::MOVQ64rr) {
+ oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
@@ -65,8 +65,8 @@
case X86::MOVSDrm:
case X86::MOVAPSrm:
case X86::MOVAPDrm:
- case X86::MOVD64rm:
- case X86::MOVQ64rm:
+ case X86::MMX_MOVD64rm:
+ case X86::MMX_MOVQ64rm:
if (MI-getOperand(1).isFrameIndex() MI-getOperand(2).isImmediate()
MI-getOperand(3).isRegister() MI-getOperand(4).isImmediate()
MI-getOperand(2).getImmedValue() == 1
@@ -95,8 +95,8 @@
case X86::MOVSDmr:
case X86::MOVAPSmr:
case X86::MOVAPDmr:
- case X86::MOVD64mr:
- case X86::MOVQ64mr:
+ case X86::MMX_MOVD64mr:
+ case X86::MMX_MOVQ64mr:
if (MI-getOperand(0).isFrameIndex() MI-getOperand(1).isImmediate()
MI-getOperand(2).isRegister() MI-getOperand(3).isImmediate()
MI-getOperand(1).getImmedValue() == 1
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.28
llvm/lib/Target/X86/X86InstrMMX.td:1.29
--- llvm/lib/Target/X86/X86InstrMMX.td:1.28 Tue Mar 27 19:57:11 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Apr 3 01:00:37 2007
@@ -118,10 +118,11 @@
}
//===--===//
-// MMX EMMS Instruction
+// MMX EMMS FEMMS Instructions
//===--===//
-def MMX_EMMS : MMXI0x77, RawFrm, (ops), emms, [(int_x86_mmx_emms)];
+def MMX_EMMS : MMXI0x77, RawFrm, (ops), emms, [(int_x86_mmx_emms)];
+def MMX_FEMMS : MMXI0x0E, RawFrm, (ops), femms, [(int_x86_mmx_femms)];
//===--===//
// MMX Scalar Instructions
@@ -130,9 +131,10 @@
// Arithmetic Instructions
// -- Addition
-defm MMX_PADDB : MMXI_binop_rm0xFC, paddb, add, v8i8, 1;
+defm MMX_PADDB : MMXI_binop_rm0xFC, paddb, add, v8i8, 1;
defm MMX_PADDW : MMXI_binop_rm0xFD, paddw, add, v4i16, 1;
defm MMX_PADDD : MMXI_binop_rm0xFE, paddd, add, v2i32, 1;
+defm MMX_PADDQ : MMXI_binop_rm0xD4, paddq, add, v1i64, 1;
defm MMX_PADDSB : MMXI_binop_rm_int0xEC, paddsb , int_x86_mmx_padds_b, 1;
defm MMX_PADDSW : MMXI_binop_rm_int0xED, paddsw , int_x86_mmx_padds_w, 1;
@@ -309,45 +311,52 @@
defm MMX_PACKUSWB : MMXI_binop_rm_int0x67, packuswb, int_x86_mmx_packuswb;
// Data Transfer Instructions
-def MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
-movd {$src, $dst|$dst, $src}, [];
-def MOVD64rm : MMXI0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
-movd {$src, $dst|$dst, $src}, [];
-def MOVD64mr : MMXI0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
-movd {$src, $dst|$dst, $src}, [];
-
-def MOVQ64rr : MMXI0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
-movq {$src, $dst|$dst, $src}, [];
-def MOVQ64rm : MMXI0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
-movq {$src, $dst|$dst, $src},
-[(set VR64:$dst, (load_mmx addr:$src))];
-def MOVQ64mr : MMXI0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
-movq {$src, $dst|$dst, $src},
-[(store (v1i64 VR64:$src), addr:$dst)];
+def MMX_MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64rm : MMXI0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64mr : MMXI0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+movd {$src, $dst|$dst, $src}, [];
+
+def MMX_MOVQ64rr : MMXI0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src}, [];
+def MMX_MOVQ64rm : MMXI0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+movq {$src, $dst|$dst, $src},
+[(set VR64:$dst, (load_mmx addr:$src))];
+def MMX_MOVQ64mr : MMXI0x7F, MRMDestMem, (ops i64mem:$dst,
[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.208 - 1.209
---
Log message:
Changed to new MMX_ recipes.
---
Diffs of the changes: (+3 -3)
X86RegisterInfo.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.208
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.209
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.208 Tue Mar 20 03:09:38 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 3 01:18:31 2007
@@ -90,7 +90,7 @@
} else if (RC == X86::VR128RegClass) {
Opc = X86::MOVAPSmr;
} else if (RC == X86::VR64RegClass) {
-Opc = X86::MOVQ64mr;
+Opc = X86::MMX_MOVQ64mr;
} else {
assert(0 Unknown regclass);
abort();
@@ -125,7 +125,7 @@
} else if (RC == X86::VR128RegClass) {
Opc = X86::MOVAPSrm;
} else if (RC == X86::VR64RegClass) {
-Opc = X86::MOVQ64rm;
+Opc = X86::MMX_MOVQ64rm;
} else {
assert(0 Unknown regclass);
abort();
@@ -159,7 +159,7 @@
} else if (RC == X86::VR128RegClass) {
Opc = X86::MOVAPSrr;
} else if (RC == X86::VR64RegClass) {
-Opc = X86::MOVQ64rr;
+Opc = X86::MMX_MOVQ64rr;
} else {
assert(0 Unknown regclass);
abort();
___
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[llvm-commits] eh_arm.cc
I'm getting this error during llvm-gcc compilation: make[3]: *** No rule to make target `eh_arm.cc', needed by `eh_arm.lo'. Stop. make[3]: *** Waiting for unfinished jobs -bw ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86: README.txt updated: 1.160 - 1.161 --- Log message: Updated --- Diffs of the changes: (+4 -0) README.txt |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.160 llvm/lib/Target/X86/README.txt:1.161 --- llvm/lib/Target/X86/README.txt:1.160Wed Mar 28 13:17:19 2007 +++ llvm/lib/Target/X86/README.txt Tue Apr 3 18:37:20 2007 @@ -1039,3 +1039,7 @@ return f(decode); return 0; } + +//===-===// + +Add support for 3DNow! ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.82 - 1.83
X86InstrMMX.td updated: 1.29 - 1.30
---
Log message:
Adding more MMX instructions.
---
Diffs of the changes: (+128 -64)
X86InstrInfo.cpp |4 -
X86InstrMMX.td | 188 ---
2 files changed, 128 insertions(+), 64 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.82
llvm/lib/Target/X86/X86InstrInfo.cpp:1.83
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.82 Tue Apr 3 01:00:37 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Apr 3 18:48:32 2007
@@ -38,7 +38,8 @@
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
- oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
+ oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr ||
+ oc == X86::MMX_MOVDQ2Qrr || oc == X86::MMX_MOVQ2DQrr) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
@@ -97,6 +98,7 @@
case X86::MOVAPDmr:
case X86::MMX_MOVD64mr:
case X86::MMX_MOVQ64mr:
+ case X86::MMX_MOVNTQmr:
if (MI-getOperand(0).isFrameIndex() MI-getOperand(1).isImmediate()
MI-getOperand(2).isRegister() MI-getOperand(3).isImmediate()
MI-getOperand(1).getImmedValue() == 1
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.29
llvm/lib/Target/X86/X86InstrMMX.td:1.30
--- llvm/lib/Target/X86/X86InstrMMX.td:1.29 Tue Apr 3 01:00:37 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Apr 3 18:48:32 2007
@@ -20,12 +20,19 @@
// MMXI - MMX instructions with TB prefix.
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
+// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
+// MMXID - MMX instructions with XD prefix.
+// MMXIS - MMX instructions with XS prefix.
class MMXIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, TB, Requires[HasMMX];
class MMX2Ibits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, TB, OpSize, Requires[HasMMX];
class MMXIi8bits8 o, Format F, dag ops, string asm, listdag pattern
: Ii8o, F, ops, asm, pattern, TB, Requires[HasMMX];
+class MMXIDbits8 o, Format F, dag ops, string asm, listdag pattern
+ : Ii8o, F, ops, asm, pattern, XD, Requires[HasMMX];
+class MMXISbits8 o, Format F, dag ops, string asm, listdag pattern
+ : Ii8o, F, ops, asm, pattern, XS, Requires[HasMMX];
// Some 'special' instructions
def IMPLICIT_DEF_VR64 : I0, Pseudo, (ops VR64:$dst),
@@ -51,6 +58,18 @@
def bc_v1i64 : PatFrag(ops node:$in), (v1i64 (bitconvert node:$in));
//===--===//
+// MMX Masks
+//===--===//
+
+def MMX_UNPCKH_shuffle_mask : PatLeaf(build_vector), [{
+ return X86::isUNPCKHMask(N);
+}];
+
+def MMX_UNPCKL_shuffle_mask : PatLeaf(build_vector), [{
+ return X86::isUNPCKLMask(N);
+}];
+
+//===--===//
// MMX Multiclasses
//===--===//
@@ -128,6 +147,35 @@
// MMX Scalar Instructions
//===--===//
+// Data Transfer Instructions
+def MMX_MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64rm : MMXI0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64mr : MMXI0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+movd {$src, $dst|$dst, $src}, [];
+
+def MMX_MOVQ64rr : MMXI0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src}, [];
+def MMX_MOVQ64rm : MMXI0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+movq {$src, $dst|$dst, $src},
+[(set VR64:$dst, (load_mmx addr:$src))];
+def MMX_MOVQ64mr : MMXI0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src},
+[(store (v1i64 VR64:$src), addr:$dst)];
+
+def MMX_MOVDQ2Qrr : MMXID0xD6, MRMDestMem, (ops VR64:$dst, VR128:$src),
+ movdq2q {$src, $dst|$dst, $src},
+ [(store (i64 (vector_extract (v2i64 VR128:$src),
+(iPTR 0))), VR64:$dst)];
+def MMX_MOVQ2DQrr : MMXIS0xD6, MRMDestMem, (ops VR128:$dst, VR64:$src),
+ movq2dq {$src, $dst|$dst, $src},
+ [(store (v1i64
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.41 - 1.42
---
Log message:
Adding more MMX instructions.
---
Diffs of the changes: (+41 -0)
IntrinsicsX86.td | 41 +
1 files changed, 41 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.41
llvm/include/llvm/IntrinsicsX86.td:1.42
--- llvm/include/llvm/IntrinsicsX86.td:1.41 Tue Apr 3 01:00:36 2007
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 3 18:48:32 2007
@@ -583,9 +583,44 @@
def int_x86_mmx_pmulh_w : GCCBuiltin__builtin_ia32_pmulhw,
Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem];
+ def int_x86_mmx_pmulhu_w : GCCBuiltin__builtin_ia32_pmulhuw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+ def int_x86_mmx_pmulu_dq : GCCBuiltin__builtin_ia32_pmuludq,
+ Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem];
def int_x86_mmx_pmadd_wd : GCCBuiltin__builtin_ia32_pmaddwd,
Intrinsic[llvm_v2i32_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem];
+
+ // Averages
+ def int_x86_mmx_pavg_b : GCCBuiltin__builtin_ia32_pavgb,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
+ def int_x86_mmx_pavg_w : GCCBuiltin__builtin_ia32_pavgw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+
+ // Maximum
+ def int_x86_mmx_pmaxu_b : GCCBuiltin__builtin_ia32_pmaxub,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
+ def int_x86_mmx_pmaxs_w : GCCBuiltin__builtin_ia32_pmaxsw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+
+ // Minimum
+ def int_x86_mmx_pminu_b : GCCBuiltin__builtin_ia32_pminub,
+ Intrinsic[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
+ def int_x86_mmx_pmins_w : GCCBuiltin__builtin_ia32_pminsw,
+ Intrinsic[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem];
+
+ // Packed sum of absolute differences
+ def int_x86_mmx_psad_bw : GCCBuiltin__builtin_ia32_psadbw,
+ Intrinsic[llvm_v4i16_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem];
}
// Integer shift ops.
@@ -654,3 +689,9 @@
Intrinsic[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v2i32_ty], [IntrNoMem];
}
+
+// Misc.
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_mmx_pmovmskb : GCCBuiltin__builtin_ia32_pmovmskb,
+ Intrinsic[llvm_i32_ty, llvm_v8i8_ty], [IntrNoMem];
+}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86.td X86CodeEmitter.cpp X86InstrInfo.h X86InstrInfo.td X86InstrSSE.td X86Subtarget.cpp X86Subtarget.h
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.29 - 1.30
X86CodeEmitter.cpp updated: 1.131 - 1.132
X86InstrInfo.h updated: 1.62 - 1.63
X86InstrInfo.td updated: 1.300 - 1.301
X86InstrSSE.td updated: 1.179 - 1.180
X86Subtarget.cpp updated: 1.53 - 1.54
X86Subtarget.h updated: 1.28 - 1.29
---
Log message:
Add support for our first SSSE3 instruction pmulhrsw.
---
Diffs of the changes: (+54 -10)
X86.td |2 ++
X86CodeEmitter.cpp |8
X86InstrInfo.h |5 -
X86InstrInfo.td|3 +++
X86InstrSSE.td | 40 +---
X86Subtarget.cpp |1 +
X86Subtarget.h |5 +++--
7 files changed, 54 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86.td
diff -u llvm/lib/Target/X86/X86.td:1.29 llvm/lib/Target/X86/X86.td:1.30
--- llvm/lib/Target/X86/X86.td:1.29 Mon Feb 26 12:17:14 2007
+++ llvm/lib/Target/X86/X86.td Tue Apr 10 17:10:25 2007
@@ -30,6 +30,8 @@
Enable SSE2 instructions;
def FeatureSSE3 : SubtargetFeaturesse3, X86SSELevel, SSE3,
Enable SSE3 instructions;
+def FeatureSSSE3 : SubtargetFeaturessse3, X86SSELevel, SSSE3,
+Enable SSSE3 instructions;
def Feature3DNow : SubtargetFeature3dnow, X863DNowLevel, ThreeDNow,
Enable 3DNow! instructions;
def Feature3DNowA: SubtargetFeature3dnowa, X863DNowLevel,
ThreeDNowA,
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.131
llvm/lib/Target/X86/X86CodeEmitter.cpp:1.132
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.131Wed Mar 14 15:20:19 2007
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue Apr 10 17:10:25 2007
@@ -584,6 +584,14 @@
case X86II::TB:
Need0FPrefix = true; // Two-byte opcode prefix
break;
+ case X86II::T8:
+MCE.emitByte(0x0F);
+MCE.emitByte(0x38);
+break;
+ case X86II::TA:
+MCE.emitByte(0x0F);
+MCE.emitByte(0x3A);
+break;
case X86II::REP: break; // already handled.
case X86II::XS: // F3 0F
MCE.emitByte(0xF3);
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.62
llvm/lib/Target/X86/X86InstrInfo.h:1.63
--- llvm/lib/Target/X86/X86InstrInfo.h:1.62 Fri Jan 26 08:34:52 2007
+++ llvm/lib/Target/X86/X86InstrInfo.h Tue Apr 10 17:10:25 2007
@@ -154,7 +154,10 @@
// XS, XD - These prefix codes are for single and double precision scalar
// floating point operations performed in the SSE registers.
-XD = 11 Op0Shift, XS = 12 Op0Shift,
+XD = 11 Op0Shift, XS = 12 Op0Shift,
+
+// T8, TA - Prefix after the 0x0F prefix.
+T8 = 13 Op0Shift, TA = 14 Op0Shift,
//===--===//
// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.300
llvm/lib/Target/X86/X86InstrInfo.td:1.301
--- llvm/lib/Target/X86/X86InstrInfo.td:1.300 Tue Mar 20 19:16:56 2007
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Apr 10 17:10:25 2007
@@ -167,6 +167,7 @@
def HasSSE1 : PredicateSubtarget-hasSSE1();
def HasSSE2 : PredicateSubtarget-hasSSE2();
def HasSSE3 : PredicateSubtarget-hasSSE3();
+def HasSSSE3 : PredicateSubtarget-hasSSSE3();
def FPStack : Predicate!Subtarget-hasSSE2();
def In32BitMode : Predicate!Subtarget-is64Bit();
def In64BitMode : PredicateSubtarget-is64Bit();
@@ -248,6 +249,8 @@
class DF { bits4 Prefix = 10; }
class XD { bits4 Prefix = 11; }
class XS { bits4 Prefix = 12; }
+class T8 { bits4 Prefix = 13; }
+class TA { bits4 Prefix = 14; }
//===--===//
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.179
llvm/lib/Target/X86/X86InstrSSE.td:1.180
--- llvm/lib/Target/X86/X86InstrSSE.td:1.179Tue Mar 20 19:16:56 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 10 17:10:25 2007
@@ -183,15 +183,17 @@
//===--===//
// Instruction templates
-// SSI - SSE1 instructions with XS prefix.
-// SDI - SSE2 instructions with XD prefix.
-// PSI - SSE1 instructions with TB prefix.
-// PDI - SSE2 instructions with TB and OpSize prefixes.
+// SSI - SSE1 instructions with XS prefix.
+// SDI - SSE2 instructions with XD prefix.
+// PSI - SSE1 instructions with TB prefix.
+// PDI - SSE2 instructions with TB and OpSize prefixes.
// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
-// S3I - SSE3 instructions with TB and OpSize prefixes.
-// S3SI - SSE3 instructions with XS prefix.
-// S3DI - SSE3 instructions with XD prefix.
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.42 - 1.43
---
Log message:
Add support for our first SSSE3 instruction pmulhrsw.
---
Diffs of the changes: (+10 -0)
IntrinsicsX86.td | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.42
llvm/include/llvm/IntrinsicsX86.td:1.43
--- llvm/include/llvm/IntrinsicsX86.td:1.42 Tue Apr 3 18:48:32 2007
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 10 17:10:25 2007
@@ -537,6 +537,16 @@
}
//===--===//
+// SSSE3
+
+// FP arithmetic ops
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_ssse3_pmulhrsw_128 : GCCBuiltin__builtin_ia32_pmulhrsw128,
+ Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty,
+ llvm_v8i16_ty], [IntrNoMem];
+}
+
+//===--===//
// MMX
// Empty MMX state op.
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Re: [llvm-commits] CVS: llvm-www/Funding.html
On Apr 12, 2007, at 5:25 AM, Reid Spencer wrote: + pbTax Exempt/b. Your donations are tax exempt in the United States (and + probably other countries). UIUC is a recognized non-profit organization. + Reciepts are available upon request./p + p Exempt or Deductible? -bw ___ llvm-commits mailing list [EMAIL PROTECTED] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm-www/Funding.html
On Apr 12, 2007, at 8:52 PM, Reid Spencer wrote: On Thu, 2007-04-12 at 20:38 -0700, Bill Wendling wrote: On Apr 12, 2007, at 5:25 AM, Reid Spencer wrote: + pbTax Exempt/b. Your donations are tax exempt in the United States (and + probably other countries). UIUC is a recognized non-profit organization. + Reciepts are available upon request./p + p Exempt or Deductible? I dunno. You can legally claim it as a charitable donation. Whether that makes it an exemption or a deduction or even what those two words mean in the gobbledy gook of Title 26, I have no idea. I'm not a tax lawyer. An organization that's designated as a non-profit is tax exempt. The donations to it are deductible. it doesn't make sense for a donation to be tax exempt to the person giving the donation. -bw ___ llvm-commits mailing list [EMAIL PROTECTED] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/Name.html
Changes in directory llvm-www: Name.html updated: 1.7 - 1.8 --- Log message: Fix anchor tags. --- Diffs of the changes: (+5 -5) Name.html | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm-www/Name.html diff -u llvm-www/Name.html:1.7 llvm-www/Name.html:1.8 --- llvm-www/Name.html:1.7 Thu Apr 12 23:31:20 2007 +++ llvm-www/Name.html Fri Apr 13 03:57:22 2007 @@ -2,10 +2,10 @@ div class=www_sectiontitleName That Compiler!/div div class=www_text table class=www -trtda href=backgroundBackground/a/td -tda href=bootyBooty/a/td -tda href=ideasIdeas/a/td -tda href=namesCandidate Names List/a/td +trtda href=#backgroundBackground/a/td +tda href=#bootyBooty/a/td +tda href=#ideasIdeas/a/td +tda href=#namesCandidate Names List/a/td /tr/table /div div class=www_subsectiona name=backgroundBackground/a/div @@ -244,6 +244,6 @@ src=http://jigsaw.w3.org/css-validator/images/vcss; alt=Valid CSS!/a a href=http://validator.w3.org/check/referer;img src=http://www.w3.org/Icons/valid-html401; alt=Valid HTML 4.01!/a -br/Last modified: $Date: 2007/04/13 04:31:20 $ +br/Last modified: $Date: 2007/04/13 08:57:22 $ /address !--#include virtual=footer.incl -- ___ llvm-commits mailing list [EMAIL PROTECTED] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [126379] apply reid's patch for PR1146
The program which does this is done at 2AM every morning.
-bw
On Apr 22, 2007, at 12:32 AM, Christopher Lamb wrote:
How long does it usually take for these to propagate to the public
SVN site?
--
Christopher Lamb
On Apr 22, 2007, at 12:52 AM, [EMAIL PROTECTED] wrote:
Revision: 126379
Author: clattner
Date: 2007-04-21 22:52:13 -0700 (Sat, 21 Apr 2007)
Log Message:
---
apply reid's patch for PR1146
Modified Paths:
--
apple-local/branches/llvm/gcc/llvm-types.cpp
Modified: apple-local/branches/llvm/gcc/llvm-types.cpp
===
--- apple-local/branches/llvm/gcc/llvm-types.cpp 2007-04-21
06:48:37 UTC (rev 126378)
+++ apple-local/branches/llvm/gcc/llvm-types.cpp 2007-04-22
05:52:13 UTC (rev 126379)
@@ -751,15 +751,17 @@
for (; Args TREE_TYPE(Args) != void_type_node; Args =
TREE_CHAIN(Args))
ABIConverter.HandleArgument(TREE_TYPE(Args));
- ParamAttrsList *ParamAttrs = 0;
+ ParamAttrsList *PAL = 0;
if (static_chain) {
// Pass the static chain in a register.
-ParamAttrs = new ParamAttrsList();
-ParamAttrs-addAttributes(1, ParamAttr::InReg);
+ParamAttrsVector Attrs;
+ParamAttrsWithIndex PAWI; PAWI.index = 1; PAWI.attrs =
ParamAttr::InReg;
+Attrs.push_back(PAWI);
+PAL = ParamAttrsList::get(Attrs);
}
- return FunctionType::get(RetTy, ArgTys, false, ParamAttrs);
+ return FunctionType::get(RetTy, ArgTys, false, PAL);
}
const FunctionType *TypeConverter::ConvertFunctionType(tree type,
@@ -811,7 +813,7 @@
// the parameter attribute in the FunctionType so any arguments
passed to
// the function will be correctly sign or zero extended to 32-
bits by
// the LLVM code gen.
- ParamAttrsList Attrs;
+ ParamAttrsVector Attrs;
uint16_t RAttributes = ParamAttr::None;
if (CallingConv == CallingConv::C) {
tree ResultTy = TREE_TYPE(type);
@@ -827,8 +829,10 @@
RAttributes |= ParamAttr::SExt;
}
}
- if (RAttributes != ParamAttr::None)
-Attrs.addAttributes(0, RAttributes);
+ if (RAttributes != ParamAttr::None) {
+ParamAttrsWithIndex PAWI; PAWI.index = 0; PAWI.attrs =
RAttributes;
+Attrs.push_back(PAWI);
+ }
unsigned Idx = 1;
bool isFirstArg = true;
@@ -838,16 +842,21 @@
LLVM_TARGET_INIT_REGPARM(lparam, type);
#endif // LLVM_TARGET_ENABLE_REGPARM
- if (static_chain)
+ if (static_chain) {
// Pass the static chain in a register.
-Attrs.addAttributes(Idx++, ParamAttr::InReg);
+ParamAttrsWithIndex PAWI; PAWI.index = Idx++; PAWI.attrs =
ParamAttr::InReg;
+Attrs.push_back(PAWI);
+ }
// The struct return attribute must be associated with the first
// parameter but that parameter may have other attributes too
so we set up
// the first Attributes value here based on struct return. This
only works
// Handle the structure return calling convention
- if (ABIConverter.isStructReturn())
-Attrs.addAttributes(Idx++, ParamAttr::StructRet);
+ if (ABIConverter.isStructReturn()) {
+ParamAttrsWithIndex PAWI;
+PAWI.index = Idx++; PAWI.attrs = ParamAttr::StructRet;
+Attrs.push_back(PAWI);
+ }
for (tree Args = TYPE_ARG_TYPES(type);
Args TREE_VALUE(Args) != void_type_node; Args =
TREE_CHAIN(Args)) {
@@ -873,18 +882,20 @@
isVarArg, lparam);
#endif // LLVM_TARGET_ENABLE_REGPARM
-if (Attributes != ParamAttr::None)
- Attrs.addAttributes(Idx, Attributes);
+if (Attributes != ParamAttr::None) {
+ ParamAttrsWithIndex PAWI; PAWI.index = Idx; PAWI.attrs =
Attributes;
+ Attrs.push_back(PAWI);
+}
Idx++;
}
// Only instantiate the parameter attributes if we got some
- ParamAttrsList *ParamAttrs = 0;
+ ParamAttrsList *PAL = 0;
if (!Attrs.empty())
-ParamAttrs = new ParamAttrsList(Attrs);
+PAL = ParamAttrsList::get(Attrs);
// Finally, make the function type
- return FunctionType::get(RetTy, ArgTypes, isVarArg, ParamAttrs);
+ return FunctionType::get(RetTy, ArgTypes, isVarArg, PAL);
}
//
===--
===//
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Re: [llvm-commits] CVS: llvm-www/Users.html
Hi John, +tda href=http://www.abo.fi/;Åbo Akademi University/a/td Could you use the HTML entity for the Å? I think it's Acirc;. Thanks! -bw ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.425 - 1.426
---
Log message:
Assertion when using a 1-element vector for an add operation. Get the
real vector type in this case.
---
Diffs of the changes: (+7 -4)
SelectionDAGISel.cpp | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.426
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425Mon Apr 23
20:24:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Apr 24 16:13:23 2007
@@ -308,19 +308,22 @@
const VectorType *PTy = castVectorType(V-getType());
unsigned NumElts = PTy-getNumElements();
MVT::ValueType EltTy = TLI.getValueType(PTy-getElementType());
+MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
-while (NumElts 1 !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
+while (NumElts 1 !TLI.isTypeLegal(VecTy)) {
NumElts = 1;
NumVectorRegs = 1;
}
-if (NumElts == 1)
+
+// Check that VecTy isn't a 1-element vector.
+if (NumElts == 1 VecTy == MVT::Other)
VT = EltTy;
else
- VT = getVectorType(EltTy, NumElts);
+ VT = VecTy;
}
-
+
// The common case is that we will only create one register for this
// value. If we have that case, create and return the virtual register.
unsigned NV = TLI.getNumElements(VT);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.396 - 1.397
X86ISelLowering.h updated: 1.99 - 1.100
---
Log message:
Support for the special case of a vector with the canonical form:
vector_shuffle v1, v2, 2, 6, 3, 7
I.e.
vector_shuffle v, undef, 2, 2, 3, 3
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
---
Diffs of the changes: (+35 -2)
X86ISelLowering.cpp | 32 ++--
X86ISelLowering.h |5 +
2 files changed, 35 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.396
llvm/lib/Target/X86/X86ISelLowering.cpp:1.397
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.396 Sun Apr 22 17:50:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Apr 24 16:16:55 2007
@@ -379,6 +379,8 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
}
if (Subtarget-hasSSE1()) {
@@ -1776,7 +1778,7 @@
assert(N-getOpcode() == ISD::BUILD_VECTOR);
unsigned NumElems = N-getNumOperands();
- if (NumElems != 4 NumElems != 8 NumElems != 16)
+ if (NumElems != 2 NumElems != 4 NumElems != 8 NumElems != 16)
return false;
for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
@@ -1792,6 +1794,29 @@
return true;
}
+/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
+/// of vector_shuffle v, v, 2, 6, 3, 7, i.e. vector_shuffle v, undef,
+/// 2, 2, 3, 3
+bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
+ assert(N-getOpcode() == ISD::BUILD_VECTOR);
+
+ unsigned NumElems = N-getNumOperands();
+ if (NumElems != 2 NumElems != 4 NumElems != 8 NumElems != 16)
+return false;
+
+ for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
+SDOperand BitI = N-getOperand(i);
+SDOperand BitI1 = N-getOperand(i + 1);
+
+if (!isUndefOrEqual(BitI, j))
+ return false;
+if (!isUndefOrEqual(BitI1, j))
+ return false;
+ }
+
+ return true;
+}
+
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element.
@@ -2432,7 +2457,7 @@
}
}
- // Let legalizer expand 2-wide build_vector's.
+ // Let legalizer expand 2-wide build_vectors.
if (EVTBits == 64)
return SDOperand();
@@ -2591,6 +2616,7 @@
}
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
+ X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val))
return Op;
@@ -2619,6 +2645,7 @@
// Commute is back and try unpck* again.
Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
+X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val))
return Op;
@@ -4231,6 +4258,7 @@
isPSHUFHW_PSHUFLWMask(Mask.Val) ||
X86::isUNPCKLMask(Mask.Val) ||
X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
+ X86::isUNPCKH_v_undef_Mask(Mask.Val) ||
X86::isUNPCKHMask(Mask.Val));
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.99
llvm/lib/Target/X86/X86ISelLowering.h:1.100
--- llvm/lib/Target/X86/X86ISelLowering.h:1.99 Fri Apr 20 16:38:10 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Tue Apr 24 16:16:55 2007
@@ -231,6 +231,11 @@
/// 0, 0, 1, 1
bool isUNPCKL_v_undef_Mask(SDNode *N);
+ /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
+ /// of vector_shuffle v, v, 2, 6, 3, 7, i.e. vector_shuffle v, undef,
+ /// 2, 2, 3, 3
+ bool isUNPCKH_v_undef_Mask(SDNode *N);
+
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.83 - 1.84
---
Log message:
Remove some invalid instructions from this check.
---
Diffs of the changes: (+1 -2)
X86InstrInfo.cpp |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.83
llvm/lib/Target/X86/X86InstrInfo.cpp:1.84
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.83 Tue Apr 3 18:48:32 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Apr 24 16:17:46 2007
@@ -38,8 +38,7 @@
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
- oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr ||
- oc == X86::MMX_MOVDQ2Qrr || oc == X86::MMX_MOVQ2DQrr) {
+ oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.43 - 1.44
---
Log message:
Add the final MMX instructions. Correct a few wrong patterns.
---
Diffs of the changes: (+4 -0)
IntrinsicsX86.td |4
1 files changed, 4 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.43
llvm/include/llvm/IntrinsicsX86.td:1.44
--- llvm/include/llvm/IntrinsicsX86.td:1.43 Tue Apr 10 17:10:25 2007
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 24 16:18:37 2007
@@ -704,4 +704,8 @@
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
def int_x86_mmx_pmovmskb : GCCBuiltin__builtin_ia32_pmovmskb,
Intrinsic[llvm_i32_ty, llvm_v8i8_ty], [IntrNoMem];
+
+ def int_x86_mmx_movnt_dq : GCCBuiltin__builtin_ia32_movntq,
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_v1i64_ty], [IntrWriteMem];
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.211 - 1.212
---
Log message:
Add the PADDQ to the list.
---
Diffs of the changes: (+1 -0)
X86RegisterInfo.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.211
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.212
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.211 Tue Apr 17 12:21:52 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 24 16:19:14 2007
@@ -769,6 +769,7 @@
{ X86::PACKUSWBrr, X86::PACKUSWBrm },
{ X86::PADDBrr, X86::PADDBrm },
{ X86::PADDDrr, X86::PADDDrm },
+ { X86::PADDQrr, X86::PADDQrm },
{ X86::PADDSBrr,X86::PADDSBrm },
{ X86::PADDSWrr,X86::PADDSWrm },
{ X86::PADDWrr, X86::PADDWrm },
___
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