Changes in directory llvm:
CREDITS.TXT updated: 1.51 - 1.52
---
Log message:
added myself to CREDITS.TXT
---
Diffs of the changes: (+4 -0)
CREDITS.TXT |4
1 files changed, 4 insertions(+)
Index: llvm/CREDITS.TXT
diff -u llvm/CREDITS.TXT:1.51 llvm/CREDITS.TXT:1.52
---
Changes in directory llvm:
configure updated: 1.227 - 1.228
---
Log message:
added a skeleton of the ARM backend
---
Diffs of the changes: (+1 -1)
configure |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/configure
diff -u llvm/configure:1.227 llvm/configure:1.228
Changes in directory llvm/tools/llc:
Makefile updated: 1.80 - 1.81
---
Log message:
added a skeleton of the ARM backend
---
Diffs of the changes: (+5 -0)
Makefile |5 +
1 files changed, 5 insertions(+)
Index: llvm/tools/llc/Makefile
diff -u llvm/tools/llc/Makefile:1.80
Changes in directory llvm/autoconf:
configure.ac updated: 1.224 - 1.225
---
Log message:
added a skeleton of the ARM backend
---
Diffs of the changes: (+1 -1)
configure.ac |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/autoconf/configure.ac
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.2 - 1.3
ARMInstrInfo.td updated: 1.1 - 1.2
ARMRegisterInfo.cpp updated: 1.2 - 1.3
---
Log message:
implement movri
add a stub LowerFORMAL_ARGUMENTS
---
Diffs of the changes: (+14 -3)
ARMISelDAGToDAG.cpp |6
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.1 - 1.2
ARMISelDAGToDAG.cpp updated: 1.3 - 1.4
ARMInstrInfo.cpp updated: 1.1 - 1.2
---
Log message:
implement minimal versions of
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
---
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.7 - 1.8
---
Log message:
port the ARM backend to use ISD::CALL instead of LowerCallTo
---
Diffs of the changes: (+3 -12)
ARMISelDAGToDAG.cpp | 15 +++
1 files changed, 3 insertions(+), 12 deletions(-)
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.2 - 1.3
---
Log message:
implement initial version of ARMAsmPrinter::printOperand
---
Diffs of the changes: (+31 -1)
ARMAsmPrinter.cpp | 32 +++-
1 files changed, 31 insertions(+), 1
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.3 - 1.4
ARMInstrInfo.td updated: 1.2 - 1.3
---
Log message:
On ARM, alignment is in bits
Add lr as a hard coded operand of bx
---
Diffs of the changes: (+7 -2)
ARMAsmPrinter.cpp |3 ++-
ARMInstrInfo.td |6
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.9 - 1.10
ARMInstrInfo.td updated: 1.3 - 1.4
---
Log message:
Expand ret into CopyToReg;BRIND
---
Diffs of the changes: (+4 -18)
ARMISelDAGToDAG.cpp | 12 +++-
ARMInstrInfo.td | 10 +-
2 files
Changes in directory llvm/test/Regression/CodeGen/ARM:
ret_arg1.ll added (r1.1)
ret_arg2.ll added (r1.1)
ret_arg3.ll added (r1.1)
ret_arg4.ll added (r1.1)
ret_arg5.ll added (r1.1)
ret_void.ll added (r1.1)
---
Log message:
added some tests for argument passing
---
Diffs of the changes: (+24
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.10 - 1.11
---
Log message:
add R0 to liveout
expand ret null (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
---
Diffs of the changes: (+13 -3)
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.11 - 1.12
---
Log message:
lower more then 4 formal arguments. The offset is currently hard coded.
implement SelectFrameIndex
---
Diffs of the changes: (+50 -15)
ARMISelDAGToDAG.cpp | 65
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.4 - 1.5
ARMRegisterInfo.cpp updated: 1.3 - 1.4
ARMRegisterInfo.td updated: 1.1 - 1.2
---
Log message:
initial implementation of ARMRegisterInfo::eliminateFrameIndex
fixes test/Regression/CodeGen/ARM/ret_arg5.ll
---
Diffs
Changes in directory llvm/test/Regression/CodeGen/ARM:
ret_arg5.ll updated: 1.2 - 1.3
---
Log message:
initial implementation of ARMRegisterInfo::eliminateFrameIndex
fixes test/Regression/CodeGen/ARM/ret_arg5.ll
---
Diffs of the changes: (+0 -1)
ret_arg5.ll |1 -
1 files changed, 1
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.12 - 1.13
ARMInstrInfo.cpp updated: 1.2 - 1.3
ARMRegisterInfo.cpp updated: 1.4 - 1.5
---
Log message:
handle the mov reg1, reg2 case in isMoveInstr
---
Diffs of the changes: (+20 -6)
ARMISelDAGToDAG.cpp | 10
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.8 - 1.9
ARMRegisterInfo.cpp updated: 1.7 - 1.8
---
Log message:
initial prologue and epilogue implementation. Need to define add and sub before
finishing it :-)
---
Diffs of the changes: (+23 -1)
ARMInstrInfo.td |
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.9 - 1.10
ARMRegisterInfo.cpp updated: 1.8 - 1.9
---
Log message:
implemented sub
correctly update the stack pointer in the prologue and epilogue
---
Diffs of the changes: (+12 -3)
ARMInstrInfo.td |4
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.16 - 1.17
---
Log message:
implement function calling of functions with up to 4 arguments
---
Diffs of the changes: (+45 -3)
ARMISelDAGToDAG.cpp | 48 +---
1 files
Changes in directory llvm/test/Regression/CodeGen/ARM:
call.ll added (r1.1)
---
Log message:
implement function calling of functions with up to 4 arguments
---
Diffs of the changes: (+8 -0)
call.ll |8
1 files changed, 8 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.6 - 1.7
---
Log message:
emit global constants
---
Diffs of the changes: (+29 -0)
ARMAsmPrinter.cpp | 29 +
1 files changed, 29 insertions(+)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.7 - 1.8
---
Log message:
handle GlobalValue::InternalLinkage in doFinalization
---
Diffs of the changes: (+10 -2)
ARMAsmPrinter.cpp | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.8 - 1.9
ARMISelDAGToDAG.cpp updated: 1.18 - 1.19
---
Log message:
implement LowerConstantPool and LowerGlobalAddress
---
Diffs of the changes: (+26 -3)
ARMAsmPrinter.cpp |4 ++--
ARMISelDAGToDAG.cpp | 25
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.19 - 1.20
ARMInstrInfo.td updated: 1.11 - 1.12
---
Log message:
add and use ARMISD::RET_FLAG
---
Diffs of the changes: (+10 -9)
ARMISelDAGToDAG.cpp | 15 +++
ARMInstrInfo.td |4 +++-
2 files
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.20 - 1.21
---
Log message:
Bug fix: always generate a RET_FLAG in LowerRET
fixes ret_null.ll and call.ll
---
Diffs of the changes: (+1 -1)
ARMISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Changes in directory llvm/test/Regression/CodeGen/ARM:
hello.ll added (r1.1)
---
Log message:
use a 'register pressure reducing' scheduler
make sure only one move is used in a hello world
---
Diffs of the changes: (+13 -0)
hello.ll | 13 +
1 files changed, 13 insertions(+)
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.21 - 1.22
---
Log message:
use a 'register pressure reducing' scheduler
make sure only one move is used in a hello world
---
Diffs of the changes: (+2 -0)
ARMISelDAGToDAG.cpp |2 ++
1 files changed, 2
Changes in directory llvm/test/Regression/CodeGen/ARM:
vargs.ll added (r1.1)
---
Log message:
initial support for variable number of arguments
---
Diffs of the changes: (+12 -0)
vargs.ll | 12
1 files changed, 12 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.23 - 1.24
ARMRegisterInfo.cpp updated: 1.9 - 1.10
---
Log message:
initial support for variable number of arguments
---
Diffs of the changes: (+37 -12)
ARMISelDAGToDAG.cpp | 24
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.4 - 1.5
ARMInstrInfo.h updated: 1.2 - 1.3
ARMInstrInfo.td updated: 1.12 - 1.13
ARMRegisterInfo.cpp updated: 1.10 - 1.11
---
Log message:
change the addressing mode of the str instruction to reg+imm
---
Diffs of the
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.11 - 1.12
---
Log message:
fix the loading of the link register in emitepilogue
---
Diffs of the changes: (+3 -1)
ARMRegisterInfo.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.24 - 1.25
ARMRegisterInfo.cpp updated: 1.12 - 1.13
---
Log message:
fix the spill code
---
Diffs of the changes: (+15 -7)
ARMISelDAGToDAG.cpp |6 ++
ARMRegisterInfo.cpp | 16 +---
2 files
Changes in directory llvm/test/Regression/CodeGen/ARM:
vargs.ll updated: 1.1 - 1.2
---
Log message:
fix the spill code
---
Diffs of the changes: (+3 -2)
vargs.ll |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/test/Regression/CodeGen/ARM/vargs.ll
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.13 - 1.14
ARMTargetMachine.cpp updated: 1.3 - 1.4
---
Log message:
correctly set LocalAreaOffset of TargetFrameInfo
---
Diffs of the changes: (+1 -6)
ARMRegisterInfo.cpp |5 -
ARMTargetMachine.cpp |2 +-
Changes in directory llvm/test/Regression/CodeGen/ARM:
ldr.ll added (r1.1)
---
Log message:
select code like
ldr rx, [ry, #offset]
---
Diffs of the changes: (+23 -0)
ldr.ll | 23 +++
1 files changed, 23 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/ldr.ll
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.28 - 1.29
---
Log message:
select code like
ldr rx, [ry, #offset]
---
Diffs of the changes: (+34 -1)
ARMISelDAGToDAG.cpp | 35 ++-
1 files changed, 34 insertions(+), 1 deletion(-)
Changes in directory llvm/lib/Target/ARM:
ARMFrameInfo.h added (r1.1)
ARMISelDAGToDAG.cpp updated: 1.29 - 1.30
ARMInstrInfo.td updated: 1.14 - 1.15
ARMRegisterInfo.cpp updated: 1.14 - 1.15
ARMTargetMachine.cpp updated: 1.4 - 1.5
ARMTargetMachine.h updated: 1.1 - 1.2
---
Log message:
Declare
Changes in directory llvm/test/Regression/CodeGen/ARM:
argaddr.ll added (r1.1)
---
Log message:
add a load effective address
---
Diffs of the changes: (+18 -0)
argaddr.ll | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/argaddr.ll
diff
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.10 - 1.11
ARMISelDAGToDAG.cpp updated: 1.30 - 1.31
ARMInstrInfo.td updated: 1.15 - 1.16
ARMRegisterInfo.cpp updated: 1.15 - 1.16
---
Log message:
add a load effective address
---
Diffs of the changes: (+30 -10)
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.31 - 1.32
---
Log message:
call computeRegisterProperties
---
Diffs of the changes: (+6 -0)
ARMISelDAGToDAG.cpp |6 ++
1 files changed, 6 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u
Changes in directory llvm/test/Regression/CodeGen/ARM:
select.ll added (r1.1)
---
Log message:
initial support for select
---
Diffs of the changes: (+15 -0)
select.ll | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/select.ll
diff -c
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.32 - 1.33
ARMInstrInfo.td updated: 1.17 - 1.18
ARMTargetMachine.cpp updated: 1.5 - 1.6
---
Log message:
initial support for select
---
Diffs of the changes: (+42 -1)
ARMISelDAGToDAG.cpp | 26
Changes in directory llvm/lib/Target/ARM:
README.txt added (r1.1)
---
Log message:
add a README.txt
---
Diffs of the changes: (+9 -0)
README.txt |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/ARM/README.txt
diff -c /dev/null llvm/lib/Target/ARM/README.txt:1.1
Changes in directory llvm/test/Regression/CodeGen/ARM:
select.ll updated: 1.4 - 1.5
---
Log message:
run llc with -march=arm in select.ll
---
Diffs of the changes: (+1 -1)
select.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.11 - 1.12
ARMISelDAGToDAG.cpp updated: 1.33 - 1.34
ARMInstrInfo.td updated: 1.18 - 1.19
---
Log message:
initial support for branches
---
Diffs of the changes: (+30 -3)
ARMAsmPrinter.cpp |3 +--
Changes in directory llvm/lib/Target/ARM:
ARM.h updated: 1.1 - 1.2
ARMAsmPrinter.cpp updated: 1.12 - 1.13
ARMISelDAGToDAG.cpp updated: 1.34 - 1.35
ARMInstrInfo.td updated: 1.19 - 1.20
---
Log message:
create a generic bcond instruction that has a conditional code argument
---
Diffs of the
Changes in directory llvm/lib/Target/ARM:
ARM.h updated: 1.3 - 1.4
ARMISelDAGToDAG.cpp updated: 1.38 - 1.39
---
Log message:
add more condition codes
---
Diffs of the changes: (+30 -2)
ARM.h | 30 --
ARMISelDAGToDAG.cpp |2 ++
2 files
Changes in directory llvm/test/Regression/CodeGen/ARM:
branch.ll updated: 1.1 - 1.2
---
Log message:
add more condition codes
---
Diffs of the changes: (+33 -3)
branch.ll | 36 +---
1 files changed, 33 insertions(+), 3 deletions(-)
Index:
Changes in directory llvm/test/Regression/CodeGen/ARM:
branch.ll updated: 1.2 - 1.3
---
Log message:
add the SETULT condition code
---
Diffs of the changes: (+15 -1)
branch.ll | 16 +++-
1 files changed, 15 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.21 - 1.22
---
Log message:
add the orr instruction
---
Diffs of the changes: (+4 -0)
ARMInstrInfo.td |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.22 - 1.23
---
Log message:
implement unconditional branches
fix select.ll
---
Diffs of the changes: (+4 -0)
ARMInstrInfo.td |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff
Changes in directory llvm/test/Regression/CodeGen/ARM:
select.ll updated: 1.7 - 1.8
---
Log message:
fix select.ll to always test a select node
---
Diffs of the changes: (+2 -11)
select.ll | 13 ++---
1 files changed, 2 insertions(+), 11 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.23 - 1.24
---
Log message:
add the eor (xor) instruction
---
Diffs of the changes: (+5 -0)
ARMInstrInfo.td |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.24 - 1.25
---
Log message:
implement shl and sra
---
Diffs of the changes: (+12 -0)
ARMInstrInfo.td | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u
Changes in directory llvm/test/Regression/CodeGen/ARM:
bits.ll added (r1.1)
---
Log message:
implement shl and sra
---
Diffs of the changes: (+36 -0)
bits.ll | 36
1 files changed, 36 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/bits.ll
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.17 - 1.18
---
Log message:
call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
---
Diffs of the changes: (+1 -0)
ARMAsmPrinter.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/test/Regression/CodeGen/ARM:
select.ll updated: 1.6 - 1.7
---
Log message:
implement unconditional branches
fix select.ll
---
Diffs of the changes: (+0 -1)
select.ll |1 -
1 files changed, 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/select.ll
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.18 - 1.19
ARMISelDAGToDAG.cpp updated: 1.41 - 1.42
ARMInstrInfo.cpp updated: 1.5 - 1.6
ARMInstrInfo.td updated: 1.25 - 1.26
ARMRegisterInfo.cpp updated: 1.17 - 1.18
---
Log message:
partial implementation of the ARM
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.26 - 1.27
---
Log message:
implement SRL and MUL
---
Diffs of the changes: (+9 -0)
ARMInstrInfo.td |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.42 - 1.43
---
Log message:
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
---
Diffs of the changes: (+3 -6)
ARMISelDAGToDAG.cpp |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
Changes in directory llvm/lib/Target/ARM:
ARM.h updated: 1.4 - 1.5
ARMAsmPrinter.cpp updated: 1.19 - 1.20
ARMISelDAGToDAG.cpp updated: 1.44 - 1.45
ARMInstrInfo.cpp updated: 1.6 - 1.7
ARMInstrInfo.td updated: 1.27 - 1.28
ARMRegisterInfo.cpp updated: 1.18 - 1.19
---
Log message:
add shifts to
Changes in directory llvm/test/Regression/CodeGen/ARM:
mul.ll added (r1.1)
---
Log message:
Implement a MachineFunctionPass to fix the mul instruction
---
Diffs of the changes: (+15 -0)
mul.ll | 15 +++
1 files changed, 15 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMMul.cpp added (r1.1)
ARM.h updated: 1.5 - 1.6
ARMTargetMachine.cpp updated: 1.9 - 1.10
ARMTargetMachine.h updated: 1.5 - 1.6
---
Log message:
Implement a MachineFunctionPass to fix the mul instruction
---
Diffs of the changes: (+74 -1)
ARM.h
Changes in directory llvm/lib/Target/ARM:
ARMMul.cpp updated: 1.1 - 1.2
---
Log message:
fix header
add comments
untabify
---
Diffs of the changes: (+23 -20)
ARMMul.cpp | 43 +++
1 files changed, 23 insertions(+), 20 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.45 - 1.46
---
Log message:
if a constant can't be an immediate, add it to the constant pool
---
Diffs of the changes: (+34 -4)
ARMISelDAGToDAG.cpp | 38 ++
1 files changed, 34
Changes in directory llvm/test/Regression/CodeGen/ARM:
select.ll updated: 1.8 - 1.9
---
Log message:
more condition codes
---
Diffs of the changes: (+43 -2)
select.ll | 45 +++--
1 files changed, 43 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
README.txt updated: 1.1 - 1.2
---
Log message:
add a note
---
Diffs of the changes: (+21 -0)
README.txt | 21 +
1 files changed, 21 insertions(+)
Index: llvm/lib/Target/ARM/README.txt
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.47 - 1.48
ARMInstrInfo.td updated: 1.28 - 1.29
ARMRegisterInfo.td updated: 1.3 - 1.4
---
Log message:
add floating point registers
implement SINT_TO_FP
---
Diffs of the changes: (+137 -23)
ARMISelDAGToDAG.cpp | 32
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll added (r1.1)
---
Log message:
add floating point registers
implement SINT_TO_FP
---
Diffs of the changes: (+10 -0)
fp.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/fp.ll
diff
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.1 - 1.2
---
Log message:
fix the names of the 64bit fp register
initial support for returning 64bit floating point numbers
---
Diffs of the changes: (+10 -2)
fp.ll | 12 ++--
1 files changed, 10
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.48 - 1.49
ARMInstrInfo.td updated: 1.29 - 1.30
ARMRegisterInfo.td updated: 1.4 - 1.5
---
Log message:
fix the names of the 64bit fp register
initial support for returning 64bit floating point numbers
---
Diffs of the
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.49 - 1.50
ARMInstrInfo.td updated: 1.30 - 1.31
README.txt updated: 1.2 - 1.3
---
Log message:
Implement floating point constants
---
Diffs of the changes: (+11 -0)
ARMISelDAGToDAG.cpp |3 +++
ARMInstrInfo.td
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.2 - 1.3
---
Log message:
Implement floating point constants
---
Diffs of the changes: (+8 -1)
fp.ll |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/fp.ll
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.50 - 1.51
ARMInstrInfo.td updated: 1.31 - 1.32
---
Log message:
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS
and LowerCALL
implement FMDRR
add support for f64 function arguments
---
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.3 - 1.4
---
Log message:
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS
and LowerCALL
implement FMDRR
add support for f64 function arguments
---
Diffs of the changes: (+7 -2)
fp.ll |
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.51 - 1.52
---
Log message:
use a const ref for passing the vector to ArgumentLayout
---
Diffs of the changes: (+2 -2)
ARMISelDAGToDAG.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.54 - 1.55
---
Log message:
fix some bugs affecting functions with no arguments
---
Diffs of the changes: (+4 -2)
ARMISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.56 - 1.57
ARMInstrInfo.td updated: 1.32 - 1.33
---
Log message:
add optional input flag to FMRRD
---
Diffs of the changes: (+4 -3)
ARMISelDAGToDAG.cpp |4 ++--
ARMInstrInfo.td |3 ++-
2 files changed, 4
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.33 - 1.34
---
Log message:
implement fadds, faddd, fmuls and fmuld
---
Diffs of the changes: (+18 -0)
ARMInstrInfo.td | 18 ++
1 files changed, 18 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.34 - 1.35
README.txt updated: 1.3 - 1.4
---
Log message:
implement FLDD
---
Diffs of the changes: (+11 -5)
ARMInstrInfo.td | 14 ++
README.txt |2 +-
2 files changed, 11 insertions(+), 5
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.6 - 1.7
---
Log message:
implement FLDD
---
Diffs of the changes: (+8 -1)
fp.ll |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/fp.ll
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.57 - 1.58
ARMInstrInfo.td updated: 1.35 - 1.36
---
Log message:
implement FUITOS and FUITOD
---
Diffs of the changes: (+31 -1)
ARMISelDAGToDAG.cpp | 22 ++
ARMInstrInfo.td | 10 +-
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.7 - 1.8
---
Log message:
implement FUITOS and FUITOD
---
Diffs of the changes: (+17 -2)
fp.ll | 19 +--
1 files changed, 17 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.58 - 1.59
---
Log message:
expand ISD::EXTLOAD
---
Diffs of the changes: (+2 -0)
ARMISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u
Changes in directory llvm/lib/Target/ARM:
README.txt updated: 1.4 - 1.5
---
Log message:
add a note
---
Diffs of the changes: (+14 -0)
README.txt | 14 ++
1 files changed, 14 insertions(+)
Index: llvm/lib/Target/ARM/README.txt
diff -u llvm/lib/Target/ARM/README.txt:1.4
Changes in directory llvm/lib/Target/ARM:
ARMTargetMachine.cpp updated: 1.10 - 1.11
---
Log message:
most ARM targets are little endian
---
Diffs of the changes: (+1 -1)
ARMTargetMachine.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.59 - 1.60
---
Log message:
expand ISD::SELECT
---
Diffs of the changes: (+2 -0)
ARMISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.36 - 1.37
---
Log message:
add ADDS and ADCS
---
Diffs of the changes: (+8 -0)
ARMInstrInfo.td |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u
Changes in directory llvm/test/Regression/CodeGen/ARM:
long.ll updated: 1.2 - 1.3
---
Log message:
add a test for adds adcs
---
Diffs of the changes: (+9 -1)
long.ll | 10 +-
1 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/long.ll
diff
Changes in directory llvm/test/Regression/CodeGen/ARM:
fpconv.ll added (r1.1)
---
Log message:
add float - double and double - float conversion
---
Diffs of the changes: (+15 -0)
fpconv.ll | 15 +++
1 files changed, 15 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.37 - 1.38
---
Log message:
add float - double and double - float conversion
---
Diffs of the changes: (+5 -0)
ARMInstrInfo.td |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/test/Regression/CodeGen/ARM:
fparith.ll added (r1.1)
---
Log message:
add some tests for floating point arithmetic
---
Diffs of the changes: (+29 -0)
fparith.ll | 29 +
1 files changed, 29 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.61 - 1.62
ARMInstrInfo.td updated: 1.38 - 1.39
---
Log message:
initial support for fp compares. Unordered compares not implemented yet
---
Diffs of the changes: (+49 -11)
ARMISelDAGToDAG.cpp | 50
Changes in directory llvm/test/Regression/CodeGen/ARM:
fpcmp.ll added (r1.1)
---
Log message:
add some tests for floating point compare
---
Diffs of the changes: (+41 -0)
fpcmp.ll | 41 +
1 files changed, 41 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.62 - 1.63
ARMInstrInfo.td updated: 1.39 - 1.40
---
Log message:
compare doubles
---
Diffs of the changes: (+6 -2)
ARMISelDAGToDAG.cpp |4 ++--
ARMInstrInfo.td |4
2 files changed, 6 insertions(+), 2
Changes in directory llvm/test/Regression/CodeGen/ARM:
fpcmp.ll updated: 1.1 - 1.2
---
Log message:
compare doubles
---
Diffs of the changes: (+10 -1)
fpcmp.ll | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/fpcmp.ll
diff -u
Changes in directory llvm/test/Regression/CodeGen/ARM:
fpconv.ll updated: 1.1 - 1.2
---
Log message:
add double - int conversion
---
Diffs of the changes: (+14 -2)
fpconv.ll | 16 ++--
1 files changed, 14 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.63 - 1.64
ARMInstrInfo.td updated: 1.40 - 1.41
---
Log message:
add double - int conversion
---
Diffs of the changes: (+26 -0)
ARMISelDAGToDAG.cpp | 18 ++
ARMInstrInfo.td |8
2
Changes in directory llvm/test/Regression/CodeGen/ARM:
fparith.ll updated: 1.1 - 1.2
---
Log message:
add fp sub
---
Diffs of the changes: (+16 -4)
fparith.ll | 20
1 files changed, 16 insertions(+), 4 deletions(-)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.41 - 1.42
---
Log message:
add fp sub
---
Diffs of the changes: (+8 -0)
ARMInstrInfo.td |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u
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