[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.503 - 1.504
---
Log message:
Fix an assertion failure in legalizing bitcast operators on targets where
vectors are split down to single elements as part of legalization.
---
Diffs of the changes: (+15 -23)
LegalizeDAG.cpp | 38 +++---
1 files changed, 15 insertions(+), 23 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.503
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.504
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.503 Wed Jun 27 11:08:04 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jun 28 19:09:08 2007
@@ -5568,38 +5568,30 @@
case ISD::BIT_CONVERT: {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
-if (!MVT::isVector(Op.getOperand(0).getValueType())) {
- // Lower to a store/load. FIXME: this could be improved probably.
- SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
+SDOperand InOp = Node-getOperand(0);
+if (!MVT::isVector(InOp.getValueType()) ||
+MVT::getVectorNumElements(InOp.getValueType()) == 1) {
+ // The input is a scalar or single-element vector.
+ // Lower to a store/load so that it can be split.
+ // FIXME: this could be improved probably.
+ SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
SDOperand St = DAG.getStore(DAG.getEntryNode(),
- Op.getOperand(0), Ptr, NULL, 0);
- St = DAG.getLoad(NewVT, St, Ptr, NULL, 0);
- SplitVectorOp(St, Lo, Hi);
-} else {
- // If the input is a vector type, we have to either scalarize it, pack it
- // or convert it based on whether the input vector type is legal.
- SDNode *InVal = Node-getOperand(0).Val;
- unsigned NumElems = MVT::getVectorNumElements(InVal-getValueType(0));
-
- assert(NumElems 1);
- {
-// Split the input vector.
-SplitVectorOp(Op.getOperand(0), Lo, Hi);
-
-// Convert each of the pieces now.
-Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
-Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
- }
- break;
+ InOp, Ptr, NULL, 0);
+ InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
}
+// Split the vector and convert each of the pieces now.
+SplitVectorOp(InOp, Lo, Hi);
+Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
+Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
+break;
}
}
// Remember in a map if the values will be reused later.
bool isNew =
SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
- assert(isNew Value already expanded?!?);
+ assert(isNew Value already split?!?);
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.501 - 1.502
---
Log message:
Make the comment for ScalarizeVectorOp mention that it is only for use
with single-element vectors.
---
Diffs of the changes: (+6 -4)
LegalizeDAG.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.501
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.502
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.501 Mon Jun 25 11:23:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jun 27 09:06:22 2007
@@ -177,8 +177,9 @@
/// two smaller values.
void SplitVectorOp(SDOperand O, SDOperand Lo, SDOperand Hi);
- /// ScalarizeVectorOp - Given an operand of vector type, convert it into the
- /// equivalent operation that returns a scalar value.
+ /// ScalarizeVectorOp - Given an operand of single-element vector type
+ /// (e.g. v1f32), convert it into the equivalent operation that returns a
+ /// scalar (e.g. f32) value.
SDOperand ScalarizeVectorOp(SDOperand O);
/// isShuffleLegal - Return true if a vector shuffle is legal with the
@@ -5602,8 +5603,9 @@
}
-/// ScalarizeVectorOp - Given an operand of vector type, convert it into the
-/// equivalent operation that returns a scalar (e.g. F32) value.
+/// ScalarizeVectorOp - Given an operand of single-element vector type
+/// (e.g. v1f32), convert it into the equivalent operation that returns a
+/// scalar (e.g. f32) value.
SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
assert(MVT::isVector(Op.getValueType())
Bad ScalarizeVectorOp invocation!);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.502 - 1.503
SelectionDAG.cpp updated: 1.410 - 1.411
---
Log message:
Rename (shrinkify) MVT::isExtendedValueType to MVT::isExtendedVT.
---
Diffs of the changes: (+2 -2)
LegalizeDAG.cpp |2 +-
SelectionDAG.cpp |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.502
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.503
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.502 Wed Jun 27 09:06:22 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jun 27 11:08:04 2007
@@ -1714,7 +1714,7 @@
break;
case Expand: {
SDOperand Lo, Hi;
-
assert(!MVT::isExtendedValueType(Node-getOperand(i).getValueType())
+ assert(!MVT::isExtendedVT(Node-getOperand(i).getValueType())
FIXME: TODO: implement returning non-legal vector types!);
ExpandOp(Node-getOperand(i), Lo, Hi);
NewValues.push_back(Lo);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.411
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410Mon Jun 25
11:23:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jun 27 11:08:04 2007
@@ -2475,7 +2475,7 @@
}
SDVTList SelectionDAG::getVTList(MVT::ValueType VT) {
- if (!MVT::isExtendedValueType(VT))
+ if (!MVT::isExtendedVT(VT))
return makeVTList(SDNode::getValueTypeList(VT), 1);
for (std::liststd::vectorMVT::ValueType ::iterator I = VTList.begin(),
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.498 - 1.499
TargetLowering.cpp updated: 1.120 - 1.121
---
Log message:
Tidy up ValueType names in comments.
---
Diffs of the changes: (+5 -5)
LegalizeDAG.cpp|4 ++--
TargetLowering.cpp |6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.498
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.499
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.498 Mon Jun 18 16:28:10 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jun 21 09:48:26 2007
@@ -5649,8 +5649,8 @@
/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
-/// equivalent operation that returns a scalar (e.g. F32) or packed value
-/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
+/// equivalent operation that returns a scalar (e.g. MVT::f32) or packed value
+/// (e.g. MVT::v4f32). When this is called, we know that PackedVT is the right
/// type for the result.
SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
MVT::ValueType NewVT) {
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.121
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120 Thu Jun 21
09:42:22 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppThu Jun 21 09:48:26 2007
@@ -243,10 +243,10 @@
else
TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
- // If the target does not have native F64 support, expand it to I64. We will
+ // If the target does not have native f64 support, expand it to i64. We will
// be generating soft float library calls. If the target does not have native
- // support for F32, promote it to F64 if it is legal. Otherwise, expand it to
- // I32.
+ // support for f32, promote it to f64 if it is legal. Otherwise, expand it to
+ // i32.
if (isTypeLegal(MVT::f64))
TransformToType[MVT::f64] = MVT::f64;
else {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.495 - 1.496
SelectionDAG.cpp updated: 1.405 - 1.406
SelectionDAGISel.cpp updated: 1.460 - 1.461
---
Log message:
Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.
This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.
---
Diffs of the changes: (+83 -21)
LegalizeDAG.cpp | 63 +++
SelectionDAG.cpp |2 +
SelectionDAGISel.cpp | 39 ++-
3 files changed, 83 insertions(+), 21 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.495
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.496
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.495 Mon Jun 4 11:17:33 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jun 13 10:12:02 2007
@@ -225,6 +225,7 @@
SDOperand Lo, SDOperand Hi);
SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
+ SDOperand LowerVEXTRACT_SUBVECTOR(SDOperand Op);
SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
SDOperand getIntPtrConstant(uint64_t Val) {
@@ -1178,6 +1179,10 @@
Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
break;
+ case ISD::VEXTRACT_SUBVECTOR:
+Result = LegalizeOp(LowerVEXTRACT_SUBVECTOR(Op));
+break;
+
case ISD::CALLSEQ_START: {
SDNode *CallEnd = FindCallEndFromCallStart(Node);
@@ -3561,6 +3566,9 @@
case ISD::VEXTRACT_VECTOR_ELT:
Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
break;
+ case ISD::VEXTRACT_SUBVECTOR:
+Result = PromoteOp(LowerVEXTRACT_SUBVECTOR(Op));
+break;
case ISD::EXTRACT_VECTOR_ELT:
Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
break;
@@ -3622,6 +3630,37 @@
}
}
+/// LowerVEXTRACT_SUBVECTOR - Lower a VEXTRACT_SUBVECTOR operation. For now
+/// we assume the operation can be split if it is not already legal.
+SDOperand SelectionDAGLegalize::LowerVEXTRACT_SUBVECTOR(SDOperand Op) {
+ // We know that operand #0 is the Vec vector. For now we assume the index
+ // is a constant and that the extracted result is a supported hardware type.
+ SDOperand Vec = Op.getOperand(0);
+ SDOperand Idx = LegalizeOp(Op.getOperand(1));
+
+ SDNode *InVal = Vec.Val;
+ unsigned NumElems = castConstantSDNode(*(InVal-op_end()-2))-getValue();
+
+ if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
+// This must be an access of the desired vector length. Return it.
+return PackVectorOp(Vec, Op.getValueType());
+ }
+
+ ConstantSDNode *CIdx = castConstantSDNode(Idx);
+ SDOperand Lo, Hi;
+ SplitVectorOp(Vec, Lo, Hi);
+ if (CIdx-getValue() NumElems/2) {
+Vec = Lo;
+ } else {
+Vec = Hi;
+Idx = DAG.getConstant(CIdx-getValue() - NumElems/2, Idx.getValueType());
+ }
+
+ // It's now an extract from the appropriate high or low part. Recurse.
+ Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
+ return LowerVEXTRACT_SUBVECTOR(Op);
+}
+
/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
/// memory traffic.
SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
@@ -5501,6 +5540,21 @@
Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps[0], HiOps.size());
break;
}
+ case ISD::VCONCAT_VECTORS: {
+unsigned NewNumSubvectors = (Node-getNumOperands() - 2) / 2;
+SmallVectorSDOperand, 8 LoOps(Node-op_begin(),
+Node-op_begin()+NewNumSubvectors);
+LoOps.push_back(NewNumEltsNode);
+LoOps.push_back(TypeNode);
+Lo = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, LoOps[0],
LoOps.size());
+
+SmallVectorSDOperand, 8 HiOps(Node-op_begin()+NewNumSubvectors,
+Node-op_end()-2);
+HiOps.push_back(NewNumEltsNode);
+HiOps.push_back(TypeNode);
+Hi = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, HiOps[0],
HiOps.size());
+break;
+ }
case ISD::VADD:
case ISD::VSUB:
case ISD::VMUL:
@@ -5655,6 +5709,11 @@
}
}
break;
+ case ISD::VCONCAT_VECTORS:
+assert(Node-getOperand(0).getValueType() == NewVT
+ Concat of non-legal vectors not yet supported!);
+Result = Node-getOperand(0);
+break;
case ISD::VINSERT_VECTOR_ELT:
if (!MVT::isVector(NewVT)) {
// Returning a scalar? Must be the inserted element.
@@ -5665,6 +5724,10 @@
Node-getOperand(1), Node-getOperand(2));
}
break;
+ case ISD::VEXTRACT_SUBVECTOR:
+Result =
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.494 - 1.495
---
Log message:
Pass the DAG to SDNode::dump to let it do more detailed dumps in some cases.
---
Diffs of the changes: (+5 -5)
LegalizeDAG.cpp | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.494
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.495
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.494 Fri May 18 12:52:13 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jun 4 11:17:33 2007
@@ -648,7 +648,7 @@
}
// Otherwise this is an unhandled builtin node. splat.
#ifndef NDEBUG
-cerr NODE: ; Node-dump(); cerr \n;
+cerr NODE: ; Node-dump(DAG); cerr \n;
#endif
assert(0 Do not know how to legalize this operator!);
abort();
@@ -3181,7 +3181,7 @@
assert(0 CopyFromReg must be legal!);
default:
#ifndef NDEBUG
-cerr NODE: ; Node-dump(); cerr \n;
+cerr NODE: ; Node-dump(DAG); cerr \n;
#endif
assert(0 Do not know how to promote this operator!);
abort();
@@ -4721,7 +4721,7 @@
assert(0 CopyFromReg must be legal!);
default:
#ifndef NDEBUG
-cerr NODE: ; Node-dump(); cerr \n;
+cerr NODE: ; Node-dump(DAG); cerr \n;
#endif
assert(0 Do not know how to expand this operator!);
abort();
@@ -5484,7 +5484,7 @@
switch (Node-getOpcode()) {
default:
#ifndef NDEBUG
-Node-dump();
+Node-dump(DAG);
#endif
assert(0 Unhandled operation in SplitVectorOp!);
case ISD::VBUILD_VECTOR: {
@@ -5606,7 +5606,7 @@
switch (Node-getOpcode()) {
default:
#ifndef NDEBUG
-Node-dump(); cerr \n;
+Node-dump(DAG); cerr \n;
#endif
assert(0 Unknown vector operation in PackVectorOp!);
case ISD::VADD:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp SelectionDAGPrinter.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.493 - 1.494
SelectionDAGISel.cpp updated: 1.451 - 1.452
SelectionDAGPrinter.cpp updated: 1.45 - 1.46
TargetLowering.cpp updated: 1.115 - 1.116
---
Log message:
Qualify several calls to functions in the MVT namespace, for consistency.
---
Diffs of the changes: (+25 -23)
LegalizeDAG.cpp | 28 +++-
SelectionDAGISel.cpp| 14 +++---
SelectionDAGPrinter.cpp |2 +-
TargetLowering.cpp |4 ++--
4 files changed, 25 insertions(+), 23 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.493
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.494
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.493 Thu May 17 13:15:41 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri May 18 12:52:13 2007
@@ -2722,7 +2722,7 @@
case TargetLowering::Promote: {
MVT::ValueType OVT = Tmp1.getValueType();
MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node-getOpcode(), OVT);
- unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
+ unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
@@ -2760,16 +2760,16 @@
case ISD::CTTZ:
//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
-DAG.getConstant(getSizeInBits(NVT), NVT),
+DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
- DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
+ DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
break;
case ISD::CTLZ:
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
- DAG.getConstant(getSizeInBits(NVT) -
- getSizeInBits(OVT), NVT));
+ DAG.getConstant(MVT::getSizeInBits(NVT) -
+ MVT::getSizeInBits(OVT), NVT));
break;
}
break;
@@ -3527,7 +3527,8 @@
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
- DAG.getConstant(getSizeInBits(NVT) -
getSizeInBits(VT),
+ DAG.getConstant(MVT::getSizeInBits(NVT) -
+ MVT::getSizeInBits(VT),
TLI.getShiftAmountTy()));
break;
case ISD::CTPOP:
@@ -3544,15 +3545,16 @@
case ISD::CTTZ:
// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
- DAG.getConstant(getSizeInBits(NVT), NVT),
ISD::SETEQ);
+ DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
+ ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
- DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
+ DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
break;
case ISD::CTLZ:
//Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
- DAG.getConstant(getSizeInBits(NVT) -
- getSizeInBits(VT), NVT));
+ DAG.getConstant(MVT::getSizeInBits(NVT) -
+ MVT::getSizeInBits(VT), NVT));
break;
}
break;
@@ -4639,7 +4641,7 @@
};
MVT::ValueType VT = Op.getValueType();
MVT::ValueType ShVT = TLI.getShiftAmountTy();
-unsigned len = getSizeInBits(VT);
+unsigned len = MVT::getSizeInBits(VT);
for (unsigned i = 0; (1U i) = (len / 2); ++i) {
//x = (x mask[i][len/8]) + (x (1 i) mask[i][len/8])
SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
@@ -4662,7 +4664,7 @@
// but see also: http://www.hackersdelight.org/HDcode/nlz.cc
MVT::ValueType VT = Op.getValueType();
MVT::ValueType ShVT = TLI.getShiftAmountTy();
-unsigned len = getSizeInBits(VT);
+unsigned len = MVT::getSizeInBits(VT);
for (unsigned i = 0; (1U i) = (len / 2); ++i) {
SDOperand Tmp3 = DAG.getConstant(1ULL i, ShVT);
Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
@@ -4684,7 +4686,7 @@
if (!TLI.isOperationLegal(ISD::CTPOP, VT)
TLI.isOperationLegal(ISD::CTLZ, VT))
return DAG.getNode(ISD::SUB, VT,
- DAG.getConstant(getSizeInBits(VT), VT),
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.492 - 1.493
---
Log message:
add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on
32-bit (or less) targets
---
Diffs of the changes: (+42 -0)
LegalizeDAG.cpp | 42 ++
1 files changed, 42 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.492
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.493
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.492 Sat May 5 14:39:05 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu May 17 13:15:41 2007
@@ -5222,6 +5222,48 @@
}
break;
}
+
+ case ISD::ADDC:
+ case ISD::SUBC: {
+// Expand the subcomponents.
+SDOperand LHSL, LHSH, RHSL, RHSH;
+ExpandOp(Node-getOperand(0), LHSL, LHSH);
+ExpandOp(Node-getOperand(1), RHSL, RHSH);
+SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
+SDOperand LoOps[2] = { LHSL, RHSL };
+SDOperand HiOps[3] = { LHSH, RHSH };
+
+if (Node-getOpcode() == ISD::ADDC) {
+ Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
+ HiOps[2] = Lo.getValue(1);
+ Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
+} else {
+ Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
+ HiOps[2] = Lo.getValue(1);
+ Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
+}
+// Remember that we legalized the flag.
+AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
+break;
+ }
+ case ISD::ADDE:
+ case ISD::SUBE: {
+// Expand the subcomponents.
+SDOperand LHSL, LHSH, RHSL, RHSH;
+ExpandOp(Node-getOperand(0), LHSL, LHSH);
+ExpandOp(Node-getOperand(1), RHSL, RHSH);
+SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
+SDOperand LoOps[3] = { LHSL, RHSL, Node-getOperand(2) };
+SDOperand HiOps[3] = { LHSH, RHSH };
+
+Lo = DAG.getNode(Node-getOpcode(), VTList, LoOps, 3);
+HiOps[2] = Lo.getValue(1);
+Hi = DAG.getNode(Node-getOpcode(), VTList, HiOps, 3);
+
+// Remember that we legalized the flag.
+AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
+break;
+ }
case ISD::MUL: {
// If the target wants to custom expand this, let them.
if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.491 - 1.492
---
Log message:
Propagate alignment/volatility in two places.
Implement support for expanding a bitcast from an illegal vector type to
a legal one (e.g. 4xi32 - 4xf32 in SSE1). This fixes PR1371:
http://llvm.org/PR1371 and
CodeGen/X86/2007-05-05-VecCastExpand.ll
---
Diffs of the changes: (+16 -4)
LegalizeDAG.cpp | 20
1 files changed, 16 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.491
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.492
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.491 Sat Apr 28 01:42:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat May 5 14:39:05 2007
@@ -1881,7 +1881,8 @@
}
Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST-getSrcValue(),
- ST-getSrcValueOffset());
+ ST-getSrcValueOffset(), ST-isVolatile(),
+ ST-getAlignment());
if (Hi.Val == NULL) {
// Must be int - float one-to-one expansion.
@@ -1896,7 +1897,8 @@
// FIXME: This sets the srcvalue of both halves to be the same, which
is
// wrong.
Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST-getSrcValue(),
- ST-getSrcValueOffset());
+ ST-getSrcValueOffset(), ST-isVolatile(),
+ std::min(ST-getAlignment(), IncrementSize));
Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
break;
}
@@ -5667,8 +5669,18 @@
PackVectorOp(Node-getOperand(0), EVT));
break;
} else {
-// FIXME: UNIMP!
-assert(0 Cast from unsupported vector type not implemented yet!);
+// If the input vector type isn't legal, then go through memory.
+SDOperand Ptr = CreateStackTemporary(NewVT);
+// Get the alignment for the store.
+const TargetData TD = *TLI.getTargetData();
+unsigned Align =
+ TD.getABITypeAlignment(MVT::getTypeForValueType(NewVT));
+
+SDOperand St = DAG.getStore(DAG.getEntryNode(),
+Node-getOperand(0), Ptr, NULL, 0, false,
+Align);
+Result = DAG.getLoad(NewVT, St, Ptr, 0, 0);
+break;
}
}
break;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.490 - 1.491
SelectionDAGISel.cpp updated: 1.433 - 1.434
---
Log message:
memory inputs to an inline asm are required to have an address available.
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.
This fixes PR1356: http://llvm.org/PR1356 and
CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
---
Diffs of the changes: (+34 -20)
LegalizeDAG.cpp |4 ++--
SelectionDAGISel.cpp | 50 --
2 files changed, 34 insertions(+), 20 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.490
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.491
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.490 Fri Apr 27 12:12:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 28 01:42:38 2007
@@ -3123,11 +3123,11 @@
// slots and always reusing the same one. We currently always create
// new ones, as reuse may inhibit scheduling.
const Type *Ty = MVT::getTypeForValueType(ExtraVT);
-unsigned TySize = (unsigned)TLI.getTargetData()-getTypeSize(Ty);
+uint64_t TySize = TLI.getTargetData()-getTypeSize(Ty);
unsigned Align = TLI.getTargetData()-getPrefTypeAlignment(Ty);
MachineFunction MF = DAG.getMachineFunction();
int SSFI =
- MF.getFrameInfo()-CreateStackObject((unsigned)TySize, Align);
+ MF.getFrameInfo()-CreateStackObject(TySize, Align);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Result = DAG.getTruncStore(DAG.getEntryNode(), Node-getOperand(0),
StackSlot, NULL, 0, ExtraVT);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.433
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.434
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.433Sat Apr 28
01:08:13 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 28 01:42:38 2007
@@ -3397,6 +3397,9 @@
CTy = TLI.getConstraintType(ConstraintCode);
if (CTy == TargetLowering::C_Other) {
+assert(!Constraints[i].isIndirect
+ Don't know how to handle indirect other inputs yet!);
+
InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
ConstraintCode[0], DAG);
if (!InOperandVal.Val) {
@@ -3411,26 +3414,35 @@
AsmNodeOperands.push_back(InOperandVal);
break;
} else if (CTy == TargetLowering::C_Memory) {
-// Memory input.
-
-// If the operand is a float, spill to a constant pool entry to get its
-// address.
-if (ConstantFP *Val = dyn_castConstantFP(I.getOperand(OpNum-1)))
- InOperandVal = DAG.getConstantPool(Val, TLI.getPointerTy());
-
-if (!MVT::isInteger(InOperandVal.getValueType())) {
- cerr Match failed, cannot handle this yet!\n;
- InOperandVal.Val-dump();
- exit(1);
+// Memory input. Memory operands really want the address of the value,
+// so we want an indirect input. If we don't have an indirect input,
+// spill the value somewhere if we can, otherwise spill it to a stack
+// slot.
+if (!Constraints[i].isIndirect) {
+ // If the operand is a float, integer, or vector constant, spill to a
+ // constant pool entry to get its address.
+ Value *OpVal = I.getOperand(OpNum-1);
+ if (isaConstantFP(OpVal) || isaConstantInt(OpVal) ||
+ isaConstantVector(OpVal)) {
+InOperandVal = DAG.getConstantPool(castConstant(OpVal),
+ TLI.getPointerTy());
+ } else {
+// Otherwise, create a stack slot and emit a store to it before the
+// asm.
+const Type *Ty = OpVal-getType();
+uint64_t TySize = TLI.getTargetData()-getTypeSize(Ty);
+unsigned Align = TLI.getTargetData()-getPrefTypeAlignment(Ty);
+MachineFunction MF = DAG.getMachineFunction();
+int SSFI = MF.getFrameInfo()-CreateStackObject(TySize, Align);
+SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
+Chain = DAG.getStore(Chain, InOperandVal, StackSlot, NULL, 0);
+InOperandVal = StackSlot;
+ }
}
-// Extend/truncate to the right pointer type if needed.
-MVT::ValueType PtrType = TLI.getPointerTy();
-if (InOperandVal.getValueType() PtrType)
- InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
-else if (InOperandVal.getValueType() PtrType)
- InOperandVal = DAG.getNode(ISD::TRUNCATE,
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.488 - 1.489
---
Log message:
Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not
available.
---
Diffs of the changes: (+25 -4)
LegalizeDAG.cpp | 29 +
1 files changed, 25 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.488
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.489
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.488 Fri Apr 20 18:02:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 27 02:33:31 2007
@@ -4270,11 +4270,10 @@
}
-/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
-/// destination type is legal.
+/// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
+///
SDOperand SelectionDAGLegalize::
ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
- assert(isTypeLegal(DestTy) Destination type is not legal!);
assert(getTypeAction(Source.getValueType()) == Expand
This is not an expansion!);
assert(Source.getValueType() == MVT::i64 Only handle expand from i64!);
@@ -4310,9 +4309,21 @@
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
else {
assert(DestTy == MVT::f64 Unexpected conversion);
+ // FIXME: Avoid the extend by construction the right constantpool?
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
CPIdx, NULL, 0, MVT::f32);
}
+MVT::ValueType SCVT = SignedConv.getValueType();
+if (SCVT != DestTy) {
+ // Destination type needs to be expanded as well. The FADD now we are
+ // constructing will be expanded into a libcall.
+ if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
+assert(SCVT == MVT::i32 DestTy == MVT::f64);
+SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
+ SignedConv, SignedConv.getValue(1));
+ }
+ SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
+}
return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
}
@@ -4345,6 +4356,7 @@
LC = RTLIB::SINTTOFP_I64_F64;
}
+ assert(TLI.getLibcallName(LC) Don't know how to expand this
SINT_TO_FP!);
Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
SDOperand UnusedHiPart;
return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
@@ -5370,7 +5382,16 @@
: DAG.getZeroExtendInReg(Tmp, SrcVT);
Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
}
-Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
+
+const char *LibCall = TLI.getLibcallName(LC);
+if (LibCall)
+ Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
+else {
+ Lo = ExpandIntToFP(Node-getOpcode() == ISD::SINT_TO_FP, VT,
+ Node-getOperand(0));
+ if (getTypeAction(Lo.getValueType()) == Expand)
+ExpandOp(Lo, Lo, Hi);
+}
break;
}
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.489 - 1.490
---
Log message:
Fix incorrect legalization of EHSELECTOR. This fixes
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326:
http://llvm.org/PR1326
---
Diffs of the changes: (+10 -6)
LegalizeDAG.cpp | 16 ++--
1 files changed, 10 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.489
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.490
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.489 Fri Apr 27 02:33:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 27 12:12:52 2007
@@ -692,12 +692,14 @@
Result = TLI.LowerOperation(Op, DAG);
if (Result.Val) break;
// Fall Thru
-case TargetLowering::Legal:
- Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT),
Tmp1).
- getValue(Op.ResNo);
+case TargetLowering::Legal: {
+ SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
+ Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
+ Ops, 2).getValue(Op.ResNo);
break;
}
}
+}
break;
case ISD::EHSELECTION: {
Tmp1 = LegalizeOp(Node-getOperand(0));
@@ -714,12 +716,14 @@
Result = TLI.LowerOperation(Op, DAG);
if (Result.Val) break;
// Fall Thru
-case TargetLowering::Legal:
- Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT),
Tmp2).
- getValue(Op.ResNo);
+case TargetLowering::Legal: {
+ SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
+ Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
+ Ops, 2).getValue(Op.ResNo);
break;
}
}
+}
break;
case ISD::AssertSext:
case ISD::AssertZext:
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.486 - 1.487
SelectionDAG.cpp updated: 1.397 - 1.398
---
Log message:
Implement general dynamic, initial exec and local exec TLS models for
X86 32 bits.
---
Diffs of the changes: (+22 -2)
LegalizeDAG.cpp |2 ++
SelectionDAG.cpp | 22 --
2 files changed, 22 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.486
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.487
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.486 Mon Apr 2 16:36:32 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 20 16:38:10 2007
@@ -622,6 +622,7 @@
case ISD::TargetConstantFP:
case ISD::TargetConstantPool:
case ISD::TargetGlobalAddress:
+ case ISD::TargetGlobalTLSAddress:
case ISD::TargetExternalSymbol:
case ISD::VALUETYPE:
case ISD::SRCVALUE:
@@ -653,6 +654,7 @@
assert(0 Do not know how to legalize this operator!);
abort();
case ISD::GlobalAddress:
+ case ISD::GlobalTLSAddress:
case ISD::ExternalSymbol:
case ISD::ConstantPool:
case ISD::JumpTable: // Nothing to do.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.397
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.398
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.397Thu Apr 12
00:58:43 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Apr 20 16:38:10 2007
@@ -14,6 +14,7 @@
#include llvm/CodeGen/SelectionDAG.h
#include llvm/Constants.h
#include llvm/GlobalValue.h
+#include llvm/GlobalVariable.h
#include llvm/Intrinsics.h
#include llvm/Assembly/Writer.h
#include llvm/CodeGen/MachineBasicBlock.h
@@ -296,7 +297,9 @@
ID.AddDouble(castConstantFPSDNode(N)-getValue());
break;
case ISD::TargetGlobalAddress:
- case ISD::GlobalAddress: {
+ case ISD::GlobalAddress:
+ case ISD::TargetGlobalTLSAddress:
+ case ISD::GlobalTLSAddress: {
GlobalAddressSDNode *GA = castGlobalAddressSDNode(N);
ID.AddPointer(GA-getGlobal());
ID.AddInteger(GA-getOffset());
@@ -692,7 +695,12 @@
SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV,
MVT::ValueType VT, int Offset,
bool isTargetGA) {
- unsigned Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
+ const GlobalVariable *GVar = dyn_castGlobalVariable(GV);
+ unsigned Opc;
+ if (GVar GVar-isThreadLocal())
+Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
+ else
+Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
ID.AddPointer(GV);
@@ -2282,6 +2290,14 @@
SDOperand Ops[] = { Op1, Op2 };
return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, 2).Val;
}
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+MVT::ValueType VT2, MVT::ValueType VT3,
+SDOperand Op1, SDOperand Op2,
+SDOperand Op3) {
+ const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2, VT3);
+ SDOperand Ops[] = { Op1, Op2, Op3 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, 3).Val;
+}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
const SDOperand *Ops, unsigned NumOps) {
@@ -2702,6 +2718,7 @@
case ISD::Constant: return Constant;
case ISD::ConstantFP:return ConstantFP;
case ISD::GlobalAddress: return GlobalAddress;
+ case ISD::GlobalTLSAddress: return GlobalTLSAddress;
case ISD::FrameIndex:return FrameIndex;
case ISD::JumpTable: return JumpTable;
case ISD::GLOBAL_OFFSET_TABLE: return GLOBAL_OFFSET_TABLE;
@@ -2725,6 +2742,7 @@
case ISD::TargetConstant: return TargetConstant;
case ISD::TargetConstantFP:return TargetConstantFP;
case ISD::TargetGlobalAddress: return TargetGlobalAddress;
+ case ISD::TargetGlobalTLSAddress: return TargetGlobalTLSAddress;
case ISD::TargetFrameIndex: return TargetFrameIndex;
case ISD::TargetJumpTable: return TargetJumpTable;
case ISD::TargetConstantPool: return TargetConstantPool;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.487 - 1.488 --- Log message: Allow the lowering of ISD::GLOBAL_OFFSET_TABLE. --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.487 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.488 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.487 Fri Apr 20 16:38:10 2007 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 20 18:02:39 2007 @@ -628,7 +628,6 @@ case ISD::SRCVALUE: case ISD::STRING: case ISD::CONDCODE: - case ISD::GLOBAL_OFFSET_TABLE: // Primitives must all be legal. assert(TLI.isOperationLegal(Node-getValueType(0), Node-getValueType(0)) This must be legal!); @@ -653,6 +652,7 @@ #endif assert(0 Do not know how to legalize this operator!); abort(); + case ISD::GLOBAL_OFFSET_TABLE: case ISD::GlobalAddress: case ISD::GlobalTLSAddress: case ISD::ExternalSymbol: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp
@@ -14,6 +14,7 @@ #include llvm/CodeGen/SelectionDAG.h #include llvm/Constants.h #include llvm/GlobalValue.h +#include llvm/GlobalVariable.h Please drop the #include of GlobalValue since GlobalVariable.h brings it in. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.484 - 1.485
---
Log message:
don't rely on ADL
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.484
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.485
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.484 Wed Mar 7 10:25:08 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 24 12:37:03 2007
@@ -484,7 +484,7 @@
unsigned NumElements =
castConstantSDNode(N-getOperand(NumOps-2))-getValue();
MVT::ValueType EVT = castVTSDNode(N-getOperand(NumOps-1))-getVT();
- MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
+ MVT::ValueType PackedVT = MVT::getVectorType(EVT, NumElements);
if (PackedVT != MVT::Other TLI.isTypeLegal(PackedVT)) {
// In the common case, this is a legal vector type, convert it to the
// packed operation and type now.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.483 - 1.484
SelectionDAGISel.cpp updated: 1.381 - 1.382
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+31 -31)
LegalizeDAG.cpp | 11 ---
SelectionDAGISel.cpp | 51 +++
2 files changed, 31 insertions(+), 31 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.483
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.484
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.483 Tue Mar 6 14:01:06 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Mar 7 10:25:08 2007
@@ -2242,8 +2242,7 @@
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
-Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
-Entry.isInReg = false; Entry.isSRet = false;
+Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
@@ -2251,17 +2250,15 @@
Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
else
Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
-Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
-Entry.isInReg = false; Entry.isSRet = false;
+Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
Args.push_back(Entry);
-Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
Args.push_back(Entry);
FnName = memset;
} else if (Node-getOpcode() == ISD::MEMCPY ||
Node-getOpcode() == ISD::MEMMOVE) {
Entry.Ty = IntPtrTy;
-Entry.isSigned = false; Entry.isInReg = false; Entry.isSRet = false;
Entry.Node = Tmp2; Args.push_back(Entry);
Entry.Node = Tmp3; Args.push_back(Entry);
Entry.Node = Tmp4; Args.push_back(Entry);
@@ -4228,7 +4225,7 @@
MVT::ValueType ArgVT = Node-getOperand(i).getValueType();
const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
Entry.Node = Node-getOperand(i); Entry.Ty = ArgTy;
-Entry.isSigned = isSigned; Entry.isInReg = false; Entry.isSRet = false;
+Entry.isSExt = isSigned;
Args.push_back(Entry);
}
SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.381
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.382
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.381Tue Mar 6
00:10:33 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Mar 7 10:25:08 2007
@@ -2279,7 +2279,8 @@
Value *Arg = I.getOperand(i);
SDOperand ArgNode = getValue(Arg);
Entry.Node = ArgNode; Entry.Ty = Arg-getType();
-Entry.isSigned = FTy-paramHasAttr(i, FunctionType::SExtAttribute);
+Entry.isSExt = FTy-paramHasAttr(i, FunctionType::SExtAttribute);
+Entry.isZExt = FTy-paramHasAttr(i, FunctionType::ZExtAttribute);
Entry.isInReg = FTy-paramHasAttr(i, FunctionType::InRegAttribute);
Entry.isSRet = FTy-paramHasAttr(i, FunctionType::StructRetAttribute);
Args.push_back(Entry);
@@ -2983,9 +2984,6 @@
TargetLowering::ArgListEntry Entry;
Entry.Node = Src;
Entry.Ty = TLI.getTargetData()-getIntPtrType();
- Entry.isSigned = false;
- Entry.isInReg = false;
- Entry.isSRet = false;
Args.push_back(Entry);
std::pairSDOperand,SDOperand Result =
@@ -3001,9 +2999,6 @@
TargetLowering::ArgListEntry Entry;
Entry.Node = getValue(I.getOperand(0));
Entry.Ty = TLI.getTargetData()-getIntPtrType();
- Entry.isSigned = false;
- Entry.isInReg = false;
- Entry.isSRet = false;
Args.push_back(Entry);
MVT::ValueType IntPtr = TLI.getPointerTy();
std::pairSDOperand,SDOperand Result =
@@ -3099,21 +3094,21 @@
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++j) {
MVT::ValueType VT = getValueType(I-getType());
-unsigned Flags = SDISelParamFlags::NoFlagSet;
+unsigned Flags = ISD::ParamFlags::NoFlagSet;
unsigned OriginalAlignment =
getTargetData()-getABITypeAlignment(I-getType());
// FIXME: Distinguish between a formal with no [sz]ext attribute from one
// that is zero extended!
if (FTy-paramHasAttr(j, FunctionType::ZExtAttribute))
- Flags = ~(SDISelParamFlags::Signed);
+ Flags = ~(ISD::ParamFlags::SExt);
if (FTy-paramHasAttr(j, FunctionType::SExtAttribute))
- Flags |= SDISelParamFlags::Signed;
+ Flags |= ISD::ParamFlags::SExt;
if (FTy-paramHasAttr(j, FunctionType::InRegAttribute))
- Flags |= SDISelParamFlags::InReg;
+ Flags |=
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.482 - 1.483
---
Log message:
big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not
the lo-reg first. This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx
---
Diffs of the changes: (+5 -0)
LegalizeDAG.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.482
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.483
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.482 Sat Mar 3 17:43:21 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 6 14:01:06 2007
@@ -1675,6 +1675,11 @@
if (Tmp2.getValueType() != MVT::Vector) {
SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
+
+ // Big endian systems want the hi reg first.
+ if (!TLI.isLittleEndian())
+std::swap(Lo, Hi);
+
if (Hi.Val)
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3,
Hi,Tmp3);
else
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.480 - 1.481 --- Log message: Add an expand action for ISD label which just deletes the label. This fixes PR1238: http://llvm.org/PR1238 . --- Diffs of the changes: (+3 -0) LegalizeDAG.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.480 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.481 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.480 Wed Feb 28 14:43:58 2007 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 3 13:21:38 2007 @@ -879,6 +879,9 @@ Tmp2 = LegalizeOp(Node-getOperand(1)); // Legalize the label id. Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); break; +case TargetLowering::Expand: + Result = LegalizeOp(Node-getOperand(0)); + break; } break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.479 - 1.480
---
Log message:
Chain is on second operand.
---
Diffs of the changes: (+23 -4)
LegalizeDAG.cpp | 27 +++
1 files changed, 23 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.479
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.480
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.479 Sat Feb 24 03:44:17 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 28 14:43:58 2007
@@ -676,16 +676,13 @@
else
Result = DAG.getConstant(0, TLI.getPointerTy());
break;
- case ISD::EHSELECTION:
case ISD::EXCEPTIONADDR: {
Tmp1 = LegalizeOp(Node-getOperand(0));
MVT::ValueType VT = Node-getValueType(0);
switch (TLI.getOperationAction(Node-getOpcode(), VT)) {
default: assert(0 This action is not supported yet!);
case TargetLowering::Expand: {
-unsigned Reg = Node-getOpcode() == ISD::EXCEPTIONADDR ?
- TLI.getExceptionAddressRegister() :
- TLI.getExceptionSelectorRegister();
+unsigned Reg = TLI.getExceptionAddressRegister();
Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
}
break;
@@ -700,6 +697,28 @@
}
}
break;
+ case ISD::EHSELECTION: {
+Tmp1 = LegalizeOp(Node-getOperand(0));
+Tmp2 = LegalizeOp(Node-getOperand(1));
+MVT::ValueType VT = Node-getValueType(0);
+switch (TLI.getOperationAction(Node-getOpcode(), VT)) {
+default: assert(0 This action is not supported yet!);
+case TargetLowering::Expand: {
+unsigned Reg = TLI.getExceptionSelectorRegister();
+Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
+ }
+ break;
+case TargetLowering::Custom:
+ Result = TLI.LowerOperation(Op, DAG);
+ if (Result.Val) break;
+ // Fall Thru
+case TargetLowering::Legal:
+ Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT),
Tmp2).
+ getValue(Op.ResNo);
+ break;
+}
+}
+break;
case ISD::AssertSext:
case ISD::AssertZext:
Tmp1 = LegalizeOp(Node-getOperand(0));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.478 - 1.479
---
Log message:
Drop unused operand.
---
Diffs of the changes: (+0 -2)
LegalizeDAG.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.478
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.479
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.478 Thu Feb 22 09:37:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 24 03:44:17 2007
@@ -677,8 +677,6 @@
Result = DAG.getConstant(0, TLI.getPointerTy());
break;
case ISD::EHSELECTION:
-LegalizeOp(Node-getOperand(1));
-// Fall Thru
case ISD::EXCEPTIONADDR: {
Tmp1 = LegalizeOp(Node-getOperand(0));
MVT::ValueType VT = Node-getValueType(0);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.477 - 1.478
---
Log message:
Simplify lowering and selection of exception ops.
---
Diffs of the changes: (+26 -2)
LegalizeDAG.cpp | 28 ++--
1 files changed, 26 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.477
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.478
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.477 Wed Feb 21 16:53:45 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 22 09:37:19 2007
@@ -668,8 +668,6 @@
break;
case ISD::FRAMEADDR:
case ISD::RETURNADDR:
- case ISD::EXCEPTIONADDR:
- case ISD::EHSELECTION:
// The only option for these nodes is to custom lower them. If the target
// does not custom lower them, then return zero.
Tmp1 = TLI.LowerOperation(Op, DAG);
@@ -678,6 +676,32 @@
else
Result = DAG.getConstant(0, TLI.getPointerTy());
break;
+ case ISD::EHSELECTION:
+LegalizeOp(Node-getOperand(1));
+// Fall Thru
+ case ISD::EXCEPTIONADDR: {
+Tmp1 = LegalizeOp(Node-getOperand(0));
+MVT::ValueType VT = Node-getValueType(0);
+switch (TLI.getOperationAction(Node-getOpcode(), VT)) {
+default: assert(0 This action is not supported yet!);
+case TargetLowering::Expand: {
+unsigned Reg = Node-getOpcode() == ISD::EXCEPTIONADDR ?
+ TLI.getExceptionAddressRegister() :
+ TLI.getExceptionSelectorRegister();
+Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
+ }
+ break;
+case TargetLowering::Custom:
+ Result = TLI.LowerOperation(Op, DAG);
+ if (Result.Val) break;
+ // Fall Thru
+case TargetLowering::Legal:
+ Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT),
Tmp1).
+ getValue(Op.ResNo);
+ break;
+}
+}
+break;
case ISD::AssertSext:
case ISD::AssertZext:
Tmp1 = LegalizeOp(Node-getOperand(0));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.476 - 1.477
SelectionDAG.cpp updated: 1.389 - 1.390
SelectionDAGISel.cpp updated: 1.369 - 1.370
---
Log message:
Selection and lowering for exception handling.
---
Diffs of the changes: (+141 -2)
LegalizeDAG.cpp |2
SelectionDAG.cpp |2
SelectionDAGISel.cpp | 139 ++-
3 files changed, 141 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.476
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.477
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.476 Wed Feb 14 21:39:18 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 21 16:53:45 2007
@@ -668,6 +668,8 @@
break;
case ISD::FRAMEADDR:
case ISD::RETURNADDR:
+ case ISD::EXCEPTIONADDR:
+ case ISD::EHSELECTION:
// The only option for these nodes is to custom lower them. If the target
// does not custom lower them, then return zero.
Tmp1 = TLI.LowerOperation(Op, DAG);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.389
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.390
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.389Sun Feb 4
02:35:21 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 21 16:53:45 2007
@@ -2679,6 +2679,8 @@
case ISD::GLOBAL_OFFSET_TABLE: return GLOBAL_OFFSET_TABLE;
case ISD::RETURNADDR: return RETURNADDR;
case ISD::FRAMEADDR: return FRAMEADDR;
+ case ISD::EXCEPTIONADDR: return EXCEPTIONADDR;
+ case ISD::EHSELECTION: return EHSELECTION;
case ISD::ConstantPool: return ConstantPool;
case ISD::ExternalSymbol: return ExternalSymbol;
case ISD::INTRINSIC_WO_CHAIN: {
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.369
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.370
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.369Wed Feb 14
21:39:18 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 21 16:53:45 2007
@@ -496,8 +496,8 @@
void visitJumpTable(SelectionDAGISel::JumpTable JT);
// These all get lowered before this pass.
- void visitInvoke(InvokeInst I) { assert(0 TODO); }
- void visitUnwind(UnwindInst I) { assert(0 TODO); }
+ void visitInvoke(InvokeInst I);
+ void visitUnwind(UnwindInst I);
void visitScalarBinary(User I, unsigned OpCode);
void visitVectorBinary(User I, unsigned OpCode);
@@ -1101,6 +1101,56 @@
return;
}
+void SelectionDAGLowering::visitInvoke(InvokeInst I) {
+ // Retrieve successors.
+ MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
+ MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
+
+ // Mark landing pad so that it doesn't get deleted in branch folding.
+ LandingPad-setIsLandingPad();
+
+ // Insert a label before the invoke call to mark the try range.
+ // This can be used to detect deletion of the invoke via the
+ // MachineModuleInfo.
+ MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
+ unsigned BeginLabel = MMI-NextLabelID();
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+ DAG.getConstant(BeginLabel, MVT::i32)));
+
+ // Insert a normal call instruction.
+ std::vectorValue* Args;
+ for (InvokeInst::op_iterator OI = I.op_begin() + 3, E = I.op_end();
+ OI != E; ++OI) {
+Args.push_back(*OI);
+ }
+ CallInst *NewCall = new CallInst(I.getCalledValue(), Args[0], Args.size(),
+ I.getName(), I);
+ NewCall-setCallingConv(I.getCallingConv());
+ I.replaceAllUsesWith(NewCall);
+ visitCall(*NewCall);
+
+ // Insert a label before the invoke call to mark the try range.
+ // This can be used to detect deletion of the invoke via the
+ // MachineModuleInfo.
+ unsigned EndLabel = MMI-NextLabelID();
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+ DAG.getConstant(EndLabel, MVT::i32)));
+
+ // Inform MachineModuleInfo of range.
+ MMI-addInvoke(LandingPad, BeginLabel, EndLabel);
+
+ // Drop into normal successor.
+ DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
+ DAG.getBasicBlock(Return)));
+
+ // Update successor info
+ CurMBB-addSuccessor(Return);
+ CurMBB-addSuccessor(LandingPad);
+}
+
+void SelectionDAGLowering::visitUnwind(UnwindInst I) {
+}
+
void SelectionDAGLowering::visitSwitch(SwitchInst I) {
// Figure out which block is immediately after the current one.
MachineBasicBlock *NextBlock = 0;
@@ -2033,6 +2083,91 @@
return 0;
}
+ case Intrinsic::eh_exception: {
+MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
+
+// Add a label to mark the beginning of the landing pad. Deletion of the
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.474 - 1.475
SelectionDAGISel.cpp updated: 1.367 - 1.368
TargetLowering.cpp updated: 1.90 - 1.91
---
Log message:
For PR1195: http://llvm.org/PR1195 :
Rename PackedType - VectorType, ConstantPacked - ConstantVector, and
PackedTyID - VectorTyID. No functional changes.
---
Diffs of the changes: (+33 -33)
LegalizeDAG.cpp |2 -
SelectionDAGISel.cpp | 58 +--
TargetLowering.cpp |6 ++---
3 files changed, 33 insertions(+), 33 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.474
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.475
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.474 Tue Feb 13 23:52:17 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 14 20:26:09 2007
@@ -3874,7 +3874,7 @@
CV.push_back(UndefValue::get(OpNTy));
}
}
-Constant *CP = ConstantPacked::get(CV);
+Constant *CP = ConstantVector::get(CV);
SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.367
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.368
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.367Wed Feb 14
01:34:56 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 14 20:26:09 2007
@@ -281,7 +281,7 @@
else {
MVT::ValueType VT1,VT2;
NumElements =
- TLI.getPackedTypeBreakdown(castPackedType(PN-getType()),
+ TLI.getVectorTypeBreakdown(castVectorType(PN-getType()),
VT1, VT2);
}
unsigned PHIReg = ValueMap[PN];
@@ -306,7 +306,7 @@
// If this is a packed type, figure out what type it will decompose into
// and how many of the elements it will use.
if (VT == MVT::Vector) {
-const PackedType *PTy = castPackedType(V-getType());
+const VectorType *PTy = castVectorType(V-getType());
unsigned NumElts = PTy-getNumElements();
MVT::ValueType EltTy = TLI.getValueType(PTy-getElementType());
@@ -504,7 +504,7 @@
void visitEitherBinary(User I, unsigned ScalarOp, unsigned VectorOp);
void visitShift(User I, unsigned Opcode);
void visitAdd(User I) {
-if (isaPackedType(I.getType()))
+if (isaVectorType(I.getType()))
visitVectorBinary(I, ISD::VADD);
else if (I.getType()-isFloatingPoint())
visitScalarBinary(I, ISD::FADD);
@@ -513,7 +513,7 @@
}
void visitSub(User I);
void visitMul(User I) {
-if (isaPackedType(I.getType()))
+if (isaVectorType(I.getType()))
visitVectorBinary(I, ISD::VMUL);
else if (I.getType()-isFloatingPoint())
visitScalarBinary(I, ISD::FMUL);
@@ -601,11 +601,11 @@
} else if (isaConstantPointerNull(C)) {
return N = DAG.getConstant(0, TLI.getPointerTy());
} else if (isaUndefValue(C)) {
- if (!isaPackedType(VTy))
+ if (!isaVectorType(VTy))
return N = DAG.getNode(ISD::UNDEF, VT);
// Create a VBUILD_VECTOR of undef nodes.
- const PackedType *PTy = castPackedType(VTy);
+ const VectorType *PTy = castVectorType(VTy);
unsigned NumElements = PTy-getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy-getElementType());
@@ -619,7 +619,7 @@
Ops[0], Ops.size());
} else if (ConstantFP *CFP = dyn_castConstantFP(C)) {
return N = DAG.getConstantFP(CFP-getValue(), VT);
-} else if (const PackedType *PTy = dyn_castPackedType(VTy)) {
+} else if (const VectorType *PTy = dyn_castVectorType(VTy)) {
unsigned NumElements = PTy-getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy-getElementType());
@@ -627,7 +627,7 @@
// Constant or ConstantFP node onto the ops list for each element of
// the packed constant.
SmallVectorSDOperand, 8 Ops;
- if (ConstantPacked *CP = dyn_castConstantPacked(C)) {
+ if (ConstantVector *CP = dyn_castConstantVector(C)) {
for (unsigned i = 0; i != NumElements; ++i)
Ops.push_back(getValue(CP-getOperand(i)));
} else {
@@ -691,8 +691,8 @@
// Otherwise, if this is a vector, make it available as a generic vector
// here.
MVT::ValueType PTyElementVT, PTyLegalElementVT;
-const PackedType *PTy = castPackedType(VTy);
-unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
+const VectorType *PTy = castVectorType(VTy);
+unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT,
PTyLegalElementVT);
// Build a VBUILD_VECTOR with the input registers.
@@ -1377,7 +1377,7 @@
void SelectionDAGLowering::visitSub(User I) {
// -0.0 - X -- fneg
const Type *Ty =
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp ScheduleDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.475 - 1.476
ScheduleDAG.cpp updated: 1.118 - 1.119
SelectionDAGISel.cpp updated: 1.368 - 1.369
---
Log message:
For PR1195: http://llvm.org/PR1195 :
Change use of packed term to vector in comments, strings, variable
names, etc.
---
Diffs of the changes: (+17 -17)
LegalizeDAG.cpp | 16
ScheduleDAG.cpp |2 +-
SelectionDAGISel.cpp | 16
3 files changed, 17 insertions(+), 17 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.475
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.476
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.475 Wed Feb 14 20:26:09 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 14 21:39:18 2007
@@ -112,7 +112,7 @@
std::mapSDOperand, std::pairSDOperand, SDOperand SplitNodes;
/// PackedNodes - For nodes that need to be packed from MVT::Vector types to
- /// concrete packed types, this contains the mapping of ones we have already
+ /// concrete vector types, this contains the mapping of ones we have already
/// processed to the result.
std::mapSDOperand, SDOperand PackedNodes;
@@ -1641,10 +1641,10 @@
MVT::ValueType EVT = castVTSDNode(*(InVal-op_end()-1))-getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other TLI.isTypeLegal(TVT)) {
-// Turn this into a return of the packed type.
+// Turn this into a return of the vector type.
Tmp2 = PackVectorOp(Tmp2, TVT);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
} else if (NumElems == 1) {
@@ -1793,10 +1793,10 @@
MVT::ValueType EVT = castVTSDNode(*(InVal-op_end()-1))-getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other TLI.isTypeLegal(TVT)) {
-// Turn this into a normal store of the packed type.
+// Turn this into a normal store of the vector type.
Tmp3 = PackVectorOp(Node-getOperand(1), TVT);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST-getSrcValue(),
ST-getSrcValueOffset());
@@ -2810,7 +2810,7 @@
MVT::ValueType EVT = castVTSDNode(*(InVal-op_end()-1))-getVT();
// Figure out if there is a Packed type corresponding to this Vector
-// type. If so, convert to the packed type.
+// type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the packed input.
@@ -3508,7 +3508,7 @@
MVT::ValueType EVT = castVTSDNode(*(InVal-op_end()-1))-getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other TLI.isTypeLegal(TVT)) {
// Turn this into a packed extract_vector_elt operation.
@@ -5553,7 +5553,7 @@
MVT::ValueType EVT = castVTSDNode(*(InVal-op_end()-1))-getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the packed input.
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.118
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.119
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.118 Sun Feb 4 02:47:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Feb 14 21:39:18 2007
@@ -332,7 +332,7 @@
if (Align == 0) {
Align = TM.getTargetData()-getPreferredTypeAlignmentShift(Type);
if (Align == 0) {
-// Alignment of packed types. FIXME!
+// Alignment of vector types. FIXME!
Align = TM.getTargetData()-getTypeSize(Type);
Align = Log2_64(Align);
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.368
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.369
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.368Wed Feb 14
20:26:09 2007
+++
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.472 - 1.473
---
Log message:
implement expand of truncate. This allows truncates from i128 to i64 to
be supported on 32-bit hosts.
---
Diffs of the changes: (+13 -0)
LegalizeDAG.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.472
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.473
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.472 Thu Feb 8 16:16:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Feb 13 17:55:16 2007
@@ -4859,6 +4859,19 @@
Hi = DAG.getConstant(0, NVT);
break;
+ case ISD::TRUNCATE: {
+// The input value must be larger than this value. Expand *it*.
+SDOperand NewLo;
+ExpandOp(Node-getOperand(0), NewLo, Hi);
+
+// The low part is now either the right size, or it is closer. If not the
+// right size, make an illegal truncate so we recursively expand it.
+if (NewLo.getValueType() != Node-getValueType(0))
+ NewLo = DAG.getNode(ISD::TRUNCATE, Node-getValueType(0), NewLo);
+ExpandOp(NewLo, Lo, Hi);
+break;
+ }
+
case ISD::BIT_CONVERT: {
SDOperand Tmp;
if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) ==
TargetLowering::Custom){
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.473 - 1.474 SelectionDAGISel.cpp updated: 1.364 - 1.365 --- Log message: Generalize TargetData strings, to support more interesting forms of data. Patch by Scott Michel. --- Diffs of the changes: (+7 -7) LegalizeDAG.cpp |6 +++--- SelectionDAGISel.cpp |8 2 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.473 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.474 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.473 Tue Feb 13 17:55:16 2007 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Feb 13 23:52:17 2007 @@ -3056,7 +3056,7 @@ // new ones, as reuse may inhibit scheduling. const Type *Ty = MVT::getTypeForValueType(ExtraVT); unsigned TySize = (unsigned)TLI.getTargetData()-getTypeSize(Ty); -unsigned Align = TLI.getTargetData()-getTypeAlignmentPref(Ty); +unsigned Align = TLI.getTargetData()-getPrefTypeAlignment(Ty); MachineFunction MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()-CreateStackObject((unsigned)TySize, Align); @@ -3979,7 +3979,7 @@ MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); unsigned ByteSize = MVT::getSizeInBits(VT)/8; const Type *Ty = MVT::getTypeForValueType(VT); - unsigned StackAlign = (unsigned)TLI.getTargetData()-getTypeAlignmentPref(Ty); + unsigned StackAlign = (unsigned)TLI.getTargetData()-getPrefTypeAlignment(Ty); int FrameIdx = FrameInfo-CreateStackObject(ByteSize, StackAlign); return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); } @@ -4289,7 +4289,7 @@ MachineFunction MF = DAG.getMachineFunction(); const Type *F64Type = MVT::getTypeForValueType(MVT::f64); unsigned StackAlign = - (unsigned)TLI.getTargetData()-getTypeAlignmentPref(F64Type); + (unsigned)TLI.getTargetData()-getPrefTypeAlignment(F64Type); int SSFI = MF.getFrameInfo()-CreateStackObject(8, StackAlign); // get address of 8 byte buffer SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.364 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.365 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.364Tue Feb 13 14:09:07 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Feb 13 23:52:17 2007 @@ -244,7 +244,7 @@ const Type *Ty = AI-getAllocatedType(); uint64_t TySize = TLI.getTargetData()-getTypeSize(Ty); unsigned Align = - std::max((unsigned)TLI.getTargetData()-getTypeAlignmentPref(Ty), + std::max((unsigned)TLI.getTargetData()-getPrefTypeAlignment(Ty), AI-getAlignment()); TySize *= CUI-getZExtValue(); // Get total allocated size. @@ -1733,7 +1733,7 @@ const Type *Ty = I.getAllocatedType(); uint64_t TySize = TLI.getTargetData()-getTypeSize(Ty); unsigned Align = -std::max((unsigned)TLI.getTargetData()-getTypeAlignmentPref(Ty), +std::max((unsigned)TLI.getTargetData()-getPrefTypeAlignment(Ty), I.getAlignment()); SDOperand AllocSize = getValue(I.getArraySize()); @@ -2934,7 +2934,7 @@ bool isInReg = FTy-paramHasAttr(j, FunctionType::InRegAttribute); bool isSRet = FTy-paramHasAttr(j, FunctionType::StructRetAttribute); unsigned OriginalAlignment = - getTargetData()-getTypeAlignmentABI(I-getType()); + getTargetData()-getABITypeAlignment(I-getType()); // Flags[31:27] - OriginalAlignment // Flags[2] - isSRet // Flags[1] - isInReg @@ -3120,7 +3120,7 @@ bool isInReg = Args[i].isInReg; bool isSRet = Args[i].isSRet; unsigned OriginalAlignment = - getTargetData()-getTypeAlignmentABI(Args[i].Ty); + getTargetData()-getABITypeAlignment(Args[i].Ty); // Flags[31:27] - OriginalAlignment // Flags[2] - isSRet // Flags[1] - isInReg ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.471 - 1.472
---
Log message:
Make use of TLI.SimplifySetCC() in LegalizeSetCCOperands().
---
Diffs of the changes: (+36 -8)
LegalizeDAG.cpp | 44
1 files changed, 36 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.471
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.472
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.471 Sat Feb 3 19:20:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 8 16:16:19 2007
@@ -3732,7 +3732,8 @@
// FIXME: This generated code sucks.
ISD::CondCode LowCC;
- switch (castCondCodeSDNode(CC)-get()) {
+ ISD::CondCode CCCode = castCondCodeSDNode(CC)-get();
+ switch (CCCode) {
default: assert(0 Unknown integer setcc!);
case ISD::SETLT:
case ISD::SETULT: LowCC = ISD::SETULT; break;
@@ -3750,13 +3751,40 @@
// NOTE: on targets without efficient SELECT of bools, we can always use
// this identity: (B1 ? B2 : B3) -- (B1 B2)|(!B1B3)
- Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
- Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
- Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
- Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
- Result, Tmp1, Tmp2));
- Tmp1 = Result;
- Tmp2 = SDOperand();
+ TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
+ Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
+ false, DagCombineInfo);
+ if (!Tmp1.Val)
+Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
+ Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
+ CCCode, false, DagCombineInfo);
+ if (!Tmp2.Val)
+Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,
CC);
+
+ ConstantSDNode *Tmp1C = dyn_castConstantSDNode(Tmp1.Val);
+ ConstantSDNode *Tmp2C = dyn_castConstantSDNode(Tmp2.Val);
+ if ((Tmp1C Tmp1C-getValue() == 0) ||
+ (Tmp2C Tmp2C-getValue() == 0
+ (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
+CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
+ (Tmp2C Tmp2C-getValue() == 1
+ (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
+CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
+// low part is known false, returns high part.
+// For LE / GE, if high part is known false, ignore the low part.
+// For LT / GT, if high part is known true, ignore the low part.
+Tmp1 = Tmp2;
+Tmp2 = SDOperand();
+ } else {
+Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
+ ISD::SETEQ, false, DagCombineInfo);
+if (!Result.Val)
+ Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
ISD::SETEQ);
+Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
+Result, Tmp1, Tmp2));
+Tmp1 = Result;
+Tmp2 = SDOperand();
+ }
}
}
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.467 - 1.468
---
Log message:
Eliminate some malloc traffic from LegalizeAllNodesNotLeadingTo, speeding
up isel on kimwitu by 0.7%.
---
Diffs of the changes: (+5 -4)
LegalizeDAG.cpp |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.467
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.468
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.467 Fri Feb 2 19:12:36 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 3 18:27:56 2007
@@ -27,6 +27,7 @@
#include llvm/Support/Compiler.h
#include llvm/ADT/DenseMap.h
#include llvm/ADT/SmallVector.h
+#include llvm/ADT/SmallPtrSet.h
#include map
using namespace llvm;
@@ -182,7 +183,7 @@
SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
-std::setSDNode* NodesLeadingTo);
+SmallPtrSetSDNode*, 32 NodesLeadingTo);
void LegalizeSetCCOperands(SDOperand LHS, SDOperand RHS, SDOperand CC);
@@ -416,7 +417,7 @@
/// NodesLeadingTo. This avoids retraversing them exponential number of times.
///
bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode
*Dest,
-std::setSDNode* NodesLeadingTo)
{
+ SmallPtrSetSDNode*, 32 NodesLeadingTo)
{
if (N == Dest) return true; // N certainly leads to Dest :)
// If we've already processed this node and it does lead to Dest, there is no
@@ -1119,7 +1120,7 @@
// Recursively Legalize all of the inputs of the call end that do not lead
// to this call start. This ensures that any libcalls that need be
inserted
// are inserted *before* the CALLSEQ_START.
-{std::setSDNode* NodesLeadingTo;
+{SmallPtrSetSDNode*, 32 NodesLeadingTo;
for (unsigned i = 0, e = CallEnd-getNumOperands(); i != e; ++i)
LegalizeAllNodesNotLeadingTo(CallEnd-getOperand(i).Val, Node,
NodesLeadingTo);
@@ -2072,7 +2073,7 @@
// Allow SETCC to not be supported for all legal data types
// Mostly this targets FP
MVT::ValueType NewInTy = Node-getOperand(0).getValueType();
- MVT::ValueType OldVT = NewInTy;
+ MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
// Scan for the appropriate larger type to use.
while (1) {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.468 - 1.469
---
Log message:
switch LegalizedNodes from std::map to a DenseMap. This speeds up isel
time as a whole on kc++ by 11%.
---
Diffs of the changes: (+15 -3)
LegalizeDAG.cpp | 18 +++---
1 files changed, 15 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.468
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.469
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.468 Sat Feb 3 18:27:56 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 3 18:50:02 2007
@@ -39,6 +39,18 @@
static const bool ViewLegalizeDAGs = 0;
#endif
+namespace llvm {
+template
+struct DenseMapKeyInfoSDOperand {
+ static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); }
+ static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1,
0);}
+ static unsigned getHashValue(const SDOperand Val) {
+return DenseMapKeyInfovoid*::getHashValue(Val.Val) + Val.ResNo;
+ }
+ static bool isPod() { return true; }
+};
+}
+
//===--===//
/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
/// hacks on it until the target machine can handle it. This involves
@@ -82,7 +94,7 @@
/// LegalizedNodes - For nodes that are of legal width, and that have more
/// than one use, this map indicates what regularized operand to use. This
/// allows us to avoid legalizing the same thing more than once.
- std::mapSDOperand, SDOperand LegalizedNodes;
+ DenseMapSDOperand, SDOperand LegalizedNodes;
/// PromotedNodes - For nodes that are below legal width, and that have more
/// than one use, this map indicates what promoted value to use. This allows
@@ -592,7 +604,7 @@
// Note that LegalizeOp may be reentered even from single-use nodes, which
// means that we always must cache transformed nodes.
- std::mapSDOperand, SDOperand::iterator I = LegalizedNodes.find(Op);
+ DenseMapSDOperand, SDOperand::iterator I = LegalizedNodes.find(Op);
if (I != LegalizedNodes.end()) return I-second;
SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
@@ -1169,7 +1181,7 @@
// will cause this node to be legalized as well as handling libcalls right.
if (LastCALLSEQ_END.Val != Node) {
LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
- std::mapSDOperand, SDOperand::iterator I = LegalizedNodes.find(Op);
+ DenseMapSDOperand, SDOperand::iterator I = LegalizedNodes.find(Op);
assert(I != LegalizedNodes.end()
Legalizing the call start should have legalized this node!);
return I-second;
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.469 - 1.470
---
Log message:
Switch promoted/expanded ops over to using a DenseMap. Vector related maps
aren't worth it.
---
Diffs of the changes: (+7 -8)
LegalizeDAG.cpp | 15 +++
1 files changed, 7 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.469
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.470
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.469 Sat Feb 3 18:50:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 3 19:17:38 2007
@@ -99,12 +99,12 @@
/// PromotedNodes - For nodes that are below legal width, and that have more
/// than one use, this map indicates what promoted value to use. This allows
/// us to avoid promoting the same thing more than once.
- std::mapSDOperand, SDOperand PromotedNodes;
+ DenseMapSDOperand, SDOperand PromotedNodes;
/// ExpandedNodes - For nodes that need to be expanded this map indicates
/// which which operands are the expanded version of the input. This allows
/// us to avoid expanding the same node more than once.
- std::mapSDOperand, std::pairSDOperand, SDOperand ExpandedNodes;
+ DenseMapSDOperand, std::pairSDOperand, SDOperand ExpandedNodes;
/// SplitNodes - For vector nodes that need to be split, this map indicates
/// which which operands are the split version of the input. This allows us
@@ -123,7 +123,7 @@
LegalizedNodes.insert(std::make_pair(To, To));
}
void AddPromotedOperand(SDOperand From, SDOperand To) {
-bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
+bool isNew = PromotedNodes.insert(std::make_pair(From, To));
assert(isNew Got into the map somehow?);
// If someone requests legalization of the new node, return itself.
LegalizedNodes.insert(std::make_pair(To, To));
@@ -3103,7 +3103,7 @@
SDOperand Result;
SDNode *Node = Op.Val;
- std::mapSDOperand, SDOperand::iterator I = PromotedNodes.find(Op);
+ DenseMapSDOperand, SDOperand::iterator I = PromotedNodes.find(Op);
if (I != PromotedNodes.end()) return I-second;
switch (Node-getOpcode()) {
@@ -4584,7 +4584,7 @@
Cannot expand to FP value or to larger int value!);
// See if we already expanded it.
- std::mapSDOperand, std::pairSDOperand, SDOperand ::iterator I
+ DenseMapSDOperand, std::pairSDOperand, SDOperand ::iterator I
= ExpandedNodes.find(Op);
if (I != ExpandedNodes.end()) {
Lo = I-second.first;
@@ -5268,8 +5268,7 @@
}
// Remember in a map if the values will be reused later.
- bool isNew =
-ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
+ bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo,
Hi)));
assert(isNew Value already expanded?!?);
}
@@ -5396,7 +5395,7 @@
}
// Remember in a map if the values will be reused later.
- bool isNew =
+ bool isNew =
SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
assert(isNew Value already expanded?!?);
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.470 - 1.471
---
Log message:
swtich vector- smallvector, speeding up selectiondag stuff 1%
---
Diffs of the changes: (+2 -2)
LegalizeDAG.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.470
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.471
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.470 Sat Feb 3 19:17:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 3 19:20:02 2007
@@ -303,7 +303,7 @@
/// ComputeTopDownOrdering - Add the specified node to the Order list if it has
/// not been visited yet and if all of its operands have already been visited.
-static void ComputeTopDownOrdering(SDNode *N, std::vectorSDNode* Order,
+static void ComputeTopDownOrdering(SDNode *N, SmallVectorSDNode*, 64 Order,
DenseMapSDNode*, unsigned Visited) {
if (++Visited[N] != N-getNumOperands())
return; // Haven't visited all operands yet
@@ -333,7 +333,7 @@
// blocks. To avoid this problem, compute an ordering of the nodes where
each
// node is only legalized after all of its operands are legalized.
DenseMapSDNode*, unsigned Visited;
- std::vectorSDNode* Order;
+ SmallVectorSDNode*, 64 Order;
// Compute ordering from all of the leaves in the graphs, those (like the
// entry node) that have no operands.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.465 - 1.466 --- Log message: Pasto --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.465 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.466 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.465 Thu Feb 1 02:39:52 2007 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Feb 2 18:43:46 2007 @@ -3634,7 +3634,7 @@ LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; break; case ISD::SETO: -LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; +LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; break; default: LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.466 - 1.467
---
Log message:
Switch ComputeTopDownOrdering over to using a densemap. This speeds up
isel as a whole by 3.3%.
---
Diffs of the changes: (+3 -2)
LegalizeDAG.cpp |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.466
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.467
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.466 Fri Feb 2 18:43:46 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Feb 2 19:12:36 2007
@@ -25,6 +25,7 @@
#include llvm/Support/MathExtras.h
#include llvm/Support/CommandLine.h
#include llvm/Support/Compiler.h
+#include llvm/ADT/DenseMap.h
#include llvm/ADT/SmallVector.h
#include map
using namespace llvm;
@@ -290,7 +291,7 @@
/// ComputeTopDownOrdering - Add the specified node to the Order list if it has
/// not been visited yet and if all of its operands have already been visited.
static void ComputeTopDownOrdering(SDNode *N, std::vectorSDNode* Order,
- std::mapSDNode*, unsigned Visited) {
+ DenseMapSDNode*, unsigned Visited) {
if (++Visited[N] != N-getNumOperands())
return; // Haven't visited all operands yet
@@ -318,7 +319,7 @@
// practice however, this causes us to run out of stack space on large basic
// blocks. To avoid this problem, compute an ordering of the nodes where
each
// node is only legalized after all of its operands are legalized.
- std::mapSDNode*, unsigned Visited;
+ DenseMapSDNode*, unsigned Visited;
std::vectorSDNode* Order;
// Compute ordering from all of the leaves in the graphs, those (like the
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.464 - 1.465
---
Log message:
Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only
affected part is codegen of memove inside x86 backend. This fixes
PR1144: http://llvm.org/PR1144
---
Diffs of the changes: (+5 -4)
LegalizeDAG.cpp |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.464
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.465
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.464 Wed Jan 31 22:55:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 1 02:39:52 2007
@@ -2178,7 +2178,7 @@
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
-Entry.isInReg = false;
+Entry.isInReg = false; Entry.isSRet = false;
Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
@@ -2187,7 +2187,7 @@
else
Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
-Entry.isInReg = false;
+Entry.isInReg = false; Entry.isSRet = false;
Args.push_back(Entry);
Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
Args.push_back(Entry);
@@ -2195,7 +2195,8 @@
FnName = memset;
} else if (Node-getOpcode() == ISD::MEMCPY ||
Node-getOpcode() == ISD::MEMMOVE) {
-Entry.Ty = IntPtrTy; Entry.isSigned = false; Entry.isInReg = false;
+Entry.Ty = IntPtrTy;
+Entry.isSigned = false; Entry.isInReg = false; Entry.isSRet = false;
Entry.Node = Tmp2; Args.push_back(Entry);
Entry.Node = Tmp3; Args.push_back(Entry);
Entry.Node = Tmp4; Args.push_back(Entry);
@@ -4122,7 +4123,7 @@
MVT::ValueType ArgVT = Node-getOperand(i).getValueType();
const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
Entry.Node = Node-getOperand(i); Entry.Ty = ArgTy;
-Entry.isSigned = isSigned; Entry.isInReg = false;
+Entry.isSigned = isSigned; Entry.isInReg = false; Entry.isSRet = false;
Args.push_back(Entry);
}
SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.462 - 1.463
TargetLowering.cpp updated: 1.86 - 1.87
---
Log message:
Allow the target to override the ISD::CondCode that's to be used to test the
result of the comparison libcall against zero.
---
Diffs of the changes: (+29 -18)
LegalizeDAG.cpp| 22 --
TargetLowering.cpp | 25 +
2 files changed, 29 insertions(+), 18 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.462
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.463
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.462 Mon Jan 29 16:58:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 31 03:29:11 2007
@@ -3604,72 +3604,58 @@
if (VT == MVT::f32 || VT == MVT::f64) {
// Expand into one or more soft-fp libcall(s).
RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
- ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
switch (castCondCodeSDNode(CC)-get()) {
case ISD::SETEQ:
case ISD::SETOEQ:
LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
-CC1 = ISD::SETEQ;
break;
case ISD::SETNE:
case ISD::SETUNE:
LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
-CC1 = ISD::SETNE;
break;
case ISD::SETGE:
case ISD::SETOGE:
LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
-CC1 = ISD::SETGE;
break;
case ISD::SETLT:
case ISD::SETOLT:
LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
-CC1 = ISD::SETLT;
break;
case ISD::SETLE:
case ISD::SETOLE:
LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
-CC1 = ISD::SETLE;
break;
case ISD::SETGT:
case ISD::SETOGT:
LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
-CC1 = ISD::SETGT;
break;
case ISD::SETUO:
+LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+break;
case ISD::SETO:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
-CC1 = castCondCodeSDNode(CC)-get() == ISD::SETO
- ? ISD::SETEQ : ISD::SETNE;
break;
default:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
-CC1 = ISD::SETNE;
switch (castCondCodeSDNode(CC)-get()) {
case ISD::SETONE:
// SETONE = SETOLT | SETOGT
LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
- CC1 = ISD::SETLT;
// Fallthrough
case ISD::SETUGT:
LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
- CC2 = ISD::SETGT;
break;
case ISD::SETUGE:
LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
- CC2 = ISD::SETGE;
break;
case ISD::SETULT:
LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
- CC2 = ISD::SETLT;
break;
case ISD::SETULE:
LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
- CC2 = ISD::SETLE;
break;
case ISD::SETUEQ:
LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
- CC2 = ISD::SETEQ;
break;
default: assert(0 Unsupported FP setcc!);
}
@@ -3680,14 +3666,14 @@
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
- CC = DAG.getCondCode(CC1);
+ CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
LHS = ExpandLibCall(TLI.getLibcallName(LC2),
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
- DAG.getCondCode(CC2));
+ DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp2 = SDOperand();
}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.86
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.87
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.86 Fri Jan 12
17:30:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppWed Jan 31 03:29:11 2007
@@ -94,6 +94,30 @@
Names[RTLIB::OGT_F64] = __gtdf2;
Names[RTLIB::UO_F32] = __unordsf2;
Names[RTLIB::UO_F64] = __unorddf2;
+ Names[RTLIB::O_F32] = __unordsf2;
+ Names[RTLIB::O_F64] = __unorddf2;
+}
+
+/// InitCmpLibcallCCs - Set default comparison
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp ScheduleDAGRRList.cpp ScheduleDAGSimple.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.463 - 1.464
ScheduleDAGRRList.cpp updated: 1.25 - 1.26
ScheduleDAGSimple.cpp updated: 1.23 - 1.24
SelectionDAG.cpp updated: 1.379 - 1.380
SelectionDAGISel.cpp updated: 1.353 - 1.354
TargetLowering.cpp updated: 1.87 - 1.88
---
Log message:
Fit in 80 columns
---
Diffs of the changes: (+19 -15)
LegalizeDAG.cpp |8
ScheduleDAGRRList.cpp | 12 +++-
ScheduleDAGSimple.cpp |4 ++--
SelectionDAG.cpp |6 --
SelectionDAGISel.cpp |2 +-
TargetLowering.cpp|2 +-
6 files changed, 19 insertions(+), 15 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.463
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.464
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.463 Wed Jan 31 03:29:11 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 31 22:55:59 2007
@@ -1516,7 +1516,7 @@
Tmp2 = LegalizeOp(Load.getValue(1));
break;
}
-assert(ExtType != ISD::EXTLOAD EXTLOAD should always be
supported!);
+assert(ExtType != ISD::EXTLOAD EXTLOAD should always be
supported!);
// Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg.
Result = DAG.getExtLoad(ISD::EXTLOAD, Node-getValueType(0),
@@ -1649,7 +1649,7 @@
// type should be returned by reference!
SDOperand Lo, Hi;
SplitVectorOp(Tmp2, Lo, Hi);
-Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,
Tmp3);
+Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3,
Hi,Tmp3);
Result = LegalizeOp(Result);
}
}
@@ -4689,7 +4689,7 @@
ISD::LoadExtType ExtType = LD-getExtensionType();
if (ExtType == ISD::NON_EXTLOAD) {
- Lo = DAG.getLoad(NVT, Ch, Ptr, LD-getSrcValue(),
LD-getSrcValueOffset());
+ Lo = DAG.getLoad(NVT, Ch, Ptr,
LD-getSrcValue(),LD-getSrcValueOffset());
if (VT == MVT::f32 || VT == MVT::f64) {
// f32-i32 or f64-i64 one to one expansion.
// Remember that we legalized the chain.
@@ -4705,7 +4705,7 @@
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
getIntPtrConstant(IncrementSize));
// FIXME: This creates a bogus srcvalue!
- Hi = DAG.getLoad(NVT, Ch, Ptr, LD-getSrcValue(),
LD-getSrcValueOffset());
+ Hi = DAG.getLoad(NVT, Ch, Ptr,
LD-getSrcValue(),LD-getSrcValueOffset());
// Build a factor node to remember that this load is independent of the
// other one.
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.25
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.26
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.25Mon Jan 8
17:55:53 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Jan 31 22:55:59 2007
@@ -696,7 +696,8 @@
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
/// Smaller number is the higher priority.
templateclass SF
-unsigned BURegReductionPriorityQueueSF::CalcNodeSethiUllmanNumber(const
SUnit *SU) {
+unsigned BURegReductionPriorityQueueSF::
+CalcNodeSethiUllmanNumber(const SUnit *SU) {
unsigned SethiUllmanNumber = SethiUllmanNumbers[SU-NodeNum];
if (SethiUllmanNumber != 0)
return SethiUllmanNumber;
@@ -805,7 +806,8 @@
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
/// Smaller number is the higher priority.
templateclass SF
-unsigned TDRegReductionPriorityQueueSF::CalcNodeSethiUllmanNumber(const
SUnit *SU) {
+unsigned TDRegReductionPriorityQueueSF::
+CalcNodeSethiUllmanNumber(const SUnit *SU) {
unsigned SethiUllmanNumber = SethiUllmanNumbers[SU-NodeNum];
if (SethiUllmanNumber != 0)
return SethiUllmanNumber;
@@ -816,8 +818,8 @@
else if (SU-NumSuccsLeft == 0)
// If SU does not have a use, i.e. it doesn't produce a value that would
// be consumed (e.g. store), then it terminates a chain of computation.
-// Give it a small SethiUllman number so it will be scheduled right before
its
-// predecessors that it doesn't lengthen their live ranges.
+// Give it a small SethiUllman number so it will be scheduled right before
+// its predecessors that it doesn't lengthen their live ranges.
SethiUllmanNumber = 0;
else if (SU-NumPredsLeft == 0
(Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
@@ -868,6 +870,6 @@
SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGRRList(*DAG, BB, DAG-getTarget(), false,
- new
TDRegReductionPriorityQueuetd_ls_rr_sort());
+ new
TDRegReductionPriorityQueuetd_ls_rr_sort());
}
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.461 - 1.462
SelectionDAG.cpp updated: 1.378 - 1.379
SelectionDAGISel.cpp updated: 1.349 - 1.350
---
Log message:
Finish off bug 680: http://llvm.org/PR680 , allowing targets to custom lower
frame and return
address nodes.
---
Diffs of the changes: (+20 -24)
LegalizeDAG.cpp | 10 ++
SelectionDAG.cpp |2 ++
SelectionDAGISel.cpp | 32
3 files changed, 20 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.461
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.462
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.461 Sun Jan 28 10:04:40 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jan 29 16:58:52 2007
@@ -652,6 +652,16 @@
break;
}
break;
+ case ISD::FRAMEADDR:
+ case ISD::RETURNADDR:
+// The only option for these nodes is to custom lower them. If the target
+// does not custom lower them, then return zero.
+Tmp1 = TLI.LowerOperation(Op, DAG);
+if (Tmp1.Val)
+ Result = Tmp1;
+else
+ Result = DAG.getConstant(0, TLI.getPointerTy());
+break;
case ISD::AssertSext:
case ISD::AssertZext:
Tmp1 = LegalizeOp(Node-getOperand(0));
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.378
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.379
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.378Fri Jan 26
08:34:51 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jan 29 16:58:52 2007
@@ -2665,6 +2665,8 @@
case ISD::FrameIndex:return FrameIndex;
case ISD::JumpTable: return JumpTable;
case ISD::GLOBAL_OFFSET_TABLE: return GLOBAL_OFFSET_TABLE;
+ case ISD::RETURNADDR: return RETURNADDR;
+ case ISD::FRAMEADDR: return FRAMEADDR;
case ISD::ConstantPool: return ConstantPool;
case ISD::ExternalSymbol: return ExternalSymbol;
case ISD::INTRINSIC_WO_CHAIN: {
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.349
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.350
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.349Sun Jan 28
12:01:49 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Jan 29 16:58:52 2007
@@ -570,7 +570,6 @@
void visitVAArg(VAArgInst I);
void visitVAEnd(CallInst I);
void visitVACopy(CallInst I);
- void visitFrameReturnAddress(CallInst I, bool isFrameAddress);
void visitMemIntrinsic(CallInst I, unsigned Op);
@@ -1932,8 +1931,14 @@
case Intrinsic::vastart: visitVAStart(I); return 0;
case Intrinsic::vaend:visitVAEnd(I); return 0;
case Intrinsic::vacopy: visitVACopy(I); return 0;
- case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
- case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
+ case Intrinsic::returnaddress:
+setValue(I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
+ getValue(I.getOperand(1;
+return 0;
+ case Intrinsic::frameaddress:
+setValue(I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
+ getValue(I.getOperand(1;
+return 0;
case Intrinsic::setjmp:
return _setjmp+!TLI.usesUnderscoreSetJmp();
break;
@@ -3207,19 +3212,6 @@
return std::make_pair(ResVal, Res.getValue(Res.Val-getNumValues()-1));
}
-
-
-// It is always conservatively correct for llvm.returnaddress and
-// llvm.frameaddress to return 0.
-//
-// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
-// expanded to 0 if the target wants.
-std::pairSDOperand, SDOperand
-TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
-unsigned Depth, SelectionDAG DAG) {
- return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
-}
-
SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
assert(0 LowerOperation not implemented for this target!);
abort();
@@ -3233,14 +3225,6 @@
return SDOperand();
}
-void SelectionDAGLowering::visitFrameReturnAddress(CallInst I, bool isFrame) {
- unsigned Depth =
(unsigned)castConstantInt(I.getOperand(1))-getZExtValue();
- std::pairSDOperand,SDOperand Result =
-TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
- setValue(I, Result.first);
- DAG.setRoot(Result.second);
-}
-
/// getMemsetValue - Vectorized representation of the memset value
/// operand.
static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.459 - 1.460
SelectionDAGISel.cpp updated: 1.346 - 1.347
---
Log message:
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning place this
parameter in registers, if possible. This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret = sret.
Before this, there will be some unexpected test fails.
---
Diffs of the changes: (+33 -13)
LegalizeDAG.cpp |6 --
SelectionDAGISel.cpp | 40 +---
2 files changed, 33 insertions(+), 13 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.459
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.460
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.459 Fri Jan 26 15:22:28 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jan 28 07:31:35 2007
@@ -2168,6 +2168,7 @@
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
+ Entry.isInReg = false;
Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
@@ -2176,6 +2177,7 @@
else
Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
+ Entry.isInReg = false;
Args.push_back(Entry);
Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
Args.push_back(Entry);
@@ -2183,7 +2185,7 @@
FnName = memset;
} else if (Node-getOpcode() == ISD::MEMCPY ||
Node-getOpcode() == ISD::MEMMOVE) {
-Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Entry.Ty = IntPtrTy; Entry.isSigned = false; Entry.isInReg = false;
Entry.Node = Tmp2; Args.push_back(Entry);
Entry.Node = Tmp3; Args.push_back(Entry);
Entry.Node = Tmp4; Args.push_back(Entry);
@@ -4124,7 +4126,7 @@
MVT::ValueType ArgVT = Node-getOperand(i).getValueType();
const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
Entry.Node = Node-getOperand(i); Entry.Ty = ArgTy;
-Entry.isSigned = isSigned;
+Entry.isSigned = isSigned; Entry.isInReg = false;
Args.push_back(Entry);
}
SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.346
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.347
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.346Fri Jan 26
15:22:28 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jan 28 07:31:35 2007
@@ -2167,6 +2167,8 @@
SDOperand ArgNode = getValue(Arg);
Entry.Node = ArgNode; Entry.Ty = Arg-getType();
Entry.isSigned = FTy-paramHasAttr(i, FunctionType::SExtAttribute);
+Entry.isInReg = FTy-paramHasAttr(i, FunctionType::InRegAttribute);
+Entry.isSRet = FTy-paramHasAttr(i, FunctionType::StructRetAttribute);
Args.push_back(Entry);
}
@@ -2761,6 +2763,8 @@
Entry.Node = Src;
Entry.Ty = TLI.getTargetData()-getIntPtrType();
Entry.isSigned = false;
+ Entry.isInReg = false;
+ Entry.isSRet = false;
Args.push_back(Entry);
std::pairSDOperand,SDOperand Result =
@@ -2777,6 +2781,8 @@
Entry.Node = getValue(I.getOperand(0));
Entry.Ty = TLI.getTargetData()-getIntPtrType();
Entry.isSigned = false;
+ Entry.isInReg = false;
+ Entry.isSRet = false;
Args.push_back(Entry);
MVT::ValueType IntPtr = TLI.getPointerTy();
std::pairSDOperand,SDOperand Result =
@@ -2859,6 +2865,7 @@
/// integrated into SDISel.
std::vectorSDOperand
TargetLowering::LowerArguments(Function F, SelectionDAG DAG) {
+ const FunctionType *FTy = F.getFunctionType();
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
std::vectorSDOperand Ops;
Ops.push_back(DAG.getRoot());
@@ -2867,16 +2874,22 @@
// Add one result value for each formal argument.
std::vectorMVT::ValueType RetVals;
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jan 28
07:31:35 2007
@@ -2168,6 +2168,7 @@
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty =
IntPtrTy;
+ Entry.isInReg = false;
Please remove the tabs here and elsewhere.
// Add one result value for each formal argument.
std::vectorMVT::ValueType RetVals;
+ unsigned j = 0;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I) {
MVT::ValueType VT = getValueType(I-getType());
+bool isInReg = FTy-paramHasAttr(++j,
FunctionType::InRegAttribute);
Please increment j in the for loop, e.g. ++I, ++j to make it more
clear how j is evolving.
Overall, this is a great patch, nice work!
-Chris
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.460 - 1.461
SelectionDAGISel.cpp updated: 1.347 - 1.348
---
Log message:
More cleanup
---
Diffs of the changes: (+5 -4)
LegalizeDAG.cpp |4 ++--
SelectionDAGISel.cpp |5 +++--
2 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.460
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.461
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.460 Sun Jan 28 07:31:35 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jan 28 10:04:40 2007
@@ -2168,7 +2168,7 @@
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
- Entry.isInReg = false;
+Entry.isInReg = false;
Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
@@ -2177,7 +2177,7 @@
else
Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
- Entry.isInReg = false;
+Entry.isInReg = false;
Args.push_back(Entry);
Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
Args.push_back(Entry);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.347
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.348
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.347Sun Jan 28
07:31:35 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jan 28 10:04:40 2007
@@ -2875,9 +2875,10 @@
// Add one result value for each formal argument.
std::vectorMVT::ValueType RetVals;
unsigned j = 0;
- for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
{
+ for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
+ I != E; ++I, ++j) {
MVT::ValueType VT = getValueType(I-getType());
-bool isInReg = FTy-paramHasAttr(++j, FunctionType::InRegAttribute);
+bool isInReg = FTy-paramHasAttr(j, FunctionType::InRegAttribute);
bool isSRet = FTy-paramHasAttr(j, FunctionType::StructRetAttribute);
unsigned Flags = (isInReg 1) | (isSRet 2);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp ScheduleDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.457 - 1.458
ScheduleDAG.cpp updated: 1.116 - 1.117
SelectionDAG.cpp updated: 1.377 - 1.378
SelectionDAGISel.cpp updated: 1.344 - 1.345
---
Log message:
Make LABEL a builtin opcode.
---
Diffs of the changes: (+11 -10)
LegalizeDAG.cpp | 12 ++--
ScheduleDAG.cpp |1 +
SelectionDAG.cpp |2 +-
SelectionDAGISel.cpp |6 +++---
4 files changed, 11 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.457
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.458
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.457 Sat Jan 20 16:35:55 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 26 08:34:51 2007
@@ -737,9 +737,9 @@
case TargetLowering::Expand: {
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
- bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
+ bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
- if (DebugInfo (useDEBUG_LOC || useDEBUG_LABEL)) {
+ if (DebugInfo (useDEBUG_LOC || useLABEL)) {
const std::string FName =
castStringSDNode(Node-getOperand(3))-getValue();
const std::string DirName =
@@ -761,7 +761,7 @@
unsigned Col = castConstantSDNode(ColOp)-getValue();
unsigned ID = DebugInfo-RecordLabel(Line, Col, SrcFile);
Ops.push_back(DAG.getConstant(ID, MVT::i32));
- Result = DAG.getNode(ISD::DEBUG_LABEL,
MVT::Other,Ops[0],Ops.size());
+ Result = DAG.getNode(ISD::LABEL, MVT::Other,Ops[0],Ops.size());
}
} else {
Result = Tmp1; // chain
@@ -803,9 +803,9 @@
}
break;
- case ISD::DEBUG_LABEL:
-assert(Node-getNumOperands() == 2 Invalid DEBUG_LABEL node!);
-switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
+ case ISD::LABEL:
+assert(Node-getNumOperands() == 2 Invalid LABEL node!);
+switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
default: assert(0 This action is not supported yet!);
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node-getOperand(0)); // Legalize the chain.
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.116
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.117
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.116 Wed Jan 24 01:03:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Jan 26 08:34:51 2007
@@ -452,6 +452,7 @@
assert(0 This target-independent node should have been selected!);
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
+case ISD::LABEL:
break;
case ISD::CopyToReg: {
unsigned InReg;
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.377
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.378
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.377Thu Dec 7
14:28:15 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jan 26 08:34:51 2007
@@ -2691,6 +2691,7 @@
case ISD::UNDEF: return undef;
case ISD::MERGE_VALUES: return mergevalues;
case ISD::INLINEASM: return inlineasm;
+ case ISD::LABEL: return label;
case ISD::HANDLENODE:return handlenode;
case ISD::FORMAL_ARGUMENTS: return formal_arguments;
case ISD::CALL: return call;
@@ -2811,7 +2812,6 @@
// Debug info
case ISD::LOCATION: return location;
case ISD::DEBUG_LOC: return debug_loc;
- case ISD::DEBUG_LABEL: return debug_label;
case ISD::CONDCODE:
switch (castCondCodeSDNode(this)-get()) {
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.344
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.345
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.344Sat Jan 20
18:29:25 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jan 26 08:34:51 2007
@@ -1980,7 +1980,7 @@
DbgRegionStartInst RSI = castDbgRegionStartInst(I);
if (DebugInfo RSI.getContext() DebugInfo-Verify(RSI.getContext())) {
unsigned LabelID = DebugInfo-RecordRegionStart(RSI.getContext());
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
DAG.getConstant(LabelID, MVT::i32)));
}
@@ -1991,7 +1991,7 @@
DbgRegionEndInst REI = castDbgRegionEndInst(I);
if (DebugInfo REI.getContext() DebugInfo-Verify(REI.getContext())) {
unsigned LabelID = DebugInfo-RecordRegionEnd(REI.getContext());
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+ DAG.setRoot(DAG.getNode(ISD::LABEL,
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.458 - 1.459
SelectionDAGISel.cpp updated: 1.345 - 1.346
---
Log message:
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
for debugging and exception handling.
---
Diffs of the changes: (+24 -24)
LegalizeDAG.cpp |8
SelectionDAGISel.cpp | 40
2 files changed, 24 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.458
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.459
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.458 Fri Jan 26 08:34:51 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 26 15:22:28 2007
@@ -735,16 +735,16 @@
case TargetLowering::Promote:
default: assert(0 This action is not supported yet!);
case TargetLowering::Expand: {
- MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
+ MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
- if (DebugInfo (useDEBUG_LOC || useLABEL)) {
+ if (MMI (useDEBUG_LOC || useLABEL)) {
const std::string FName =
castStringSDNode(Node-getOperand(3))-getValue();
const std::string DirName =
castStringSDNode(Node-getOperand(4))-getValue();
-unsigned SrcFile = DebugInfo-RecordSource(DirName, FName);
+unsigned SrcFile = MMI-RecordSource(DirName, FName);
SmallVectorSDOperand, 8 Ops;
Ops.push_back(Tmp1); // chain
@@ -759,7 +759,7 @@
} else {
unsigned Line = castConstantSDNode(LineOp)-getValue();
unsigned Col = castConstantSDNode(ColOp)-getValue();
- unsigned ID = DebugInfo-RecordLabel(Line, Col, SrcFile);
+ unsigned ID = MMI-RecordLabel(Line, Col, SrcFile);
Ops.push_back(DAG.getConstant(ID, MVT::i32));
Result = DAG.getNode(ISD::LABEL, MVT::Other,Ops[0],Ops.size());
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.345
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.346
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.345Fri Jan 26
08:34:51 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jan 26 15:22:28 2007
@@ -24,7 +24,7 @@
#include llvm/Instructions.h
#include llvm/Intrinsics.h
#include llvm/IntrinsicInst.h
-#include llvm/CodeGen/MachineDebugInfo.h
+#include llvm/CodeGen/MachineModuleInfo.h
#include llvm/CodeGen/MachineFunction.h
#include llvm/CodeGen/MachineFrameInfo.h
#include llvm/CodeGen/MachineJumpTableInfo.h
@@ -1954,16 +1954,16 @@
return 0;
case Intrinsic::dbg_stoppoint: {
-MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
+MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
DbgStopPointInst SPI = castDbgStopPointInst(I);
-if (DebugInfo SPI.getContext() DebugInfo-Verify(SPI.getContext())) {
+if (MMI SPI.getContext() MMI-Verify(SPI.getContext())) {
SDOperand Ops[5];
Ops[0] = getRoot();
Ops[1] = getValue(SPI.getLineValue());
Ops[2] = getValue(SPI.getColumnValue());
- DebugInfoDesc *DD = DebugInfo-getDescFor(SPI.getContext());
+ DebugInfoDesc *DD = MMI-getDescFor(SPI.getContext());
assert(DD Not a debug information descriptor);
CompileUnitDesc *CompileUnit = castCompileUnitDesc(DD);
@@ -1976,10 +1976,10 @@
return 0;
}
case Intrinsic::dbg_region_start: {
-MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
+MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
DbgRegionStartInst RSI = castDbgRegionStartInst(I);
-if (DebugInfo RSI.getContext() DebugInfo-Verify(RSI.getContext())) {
- unsigned LabelID = DebugInfo-RecordRegionStart(RSI.getContext());
+if (MMI RSI.getContext() MMI-Verify(RSI.getContext())) {
+ unsigned LabelID = MMI-RecordRegionStart(RSI.getContext());
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
DAG.getConstant(LabelID, MVT::i32)));
}
@@ -1987,10 +1987,10 @@
return 0;
}
case Intrinsic::dbg_region_end: {
-MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
+MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
DbgRegionEndInst REI = castDbgRegionEndInst(I);
-if (DebugInfo REI.getContext() DebugInfo-Verify(REI.getContext())) {
- unsigned LabelID = DebugInfo-RecordRegionEnd(REI.getContext());
+if (MMI REI.getContext() MMI-Verify(REI.getContext())) {
+ unsigned LabelID = MMI-RecordRegionEnd(REI.getContext());
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.456 - 1.457
SelectionDAGISel.cpp updated: 1.342 - 1.343
---
Log message:
Teach TargetData to handle 'preferred' alignment for each target, and use
these alignment amounts to align scalars when we can. Patch by Scott Michel!
---
Diffs of the changes: (+13 -15)
LegalizeDAG.cpp | 13 +
SelectionDAGISel.cpp | 15 ---
2 files changed, 13 insertions(+), 15 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.456
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.457
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.456 Fri Jan 19 15:13:56 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jan 20 16:35:55 2007
@@ -3029,7 +3029,7 @@
// new ones, as reuse may inhibit scheduling.
const Type *Ty = MVT::getTypeForValueType(ExtraVT);
unsigned TySize = (unsigned)TLI.getTargetData()-getTypeSize(Ty);
-unsigned Align = TLI.getTargetData()-getTypeAlignment(Ty);
+unsigned Align = TLI.getTargetData()-getTypeAlignmentPref(Ty);
MachineFunction MF = DAG.getMachineFunction();
int SSFI =
MF.getFrameInfo()-CreateStackObject((unsigned)TySize, Align);
@@ -3937,7 +3937,9 @@
SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
unsigned ByteSize = MVT::getSizeInBits(VT)/8;
- int FrameIdx = FrameInfo-CreateStackObject(ByteSize, ByteSize);
+ const Type *Ty = MVT::getTypeForValueType(VT);
+ unsigned StackAlign =
(unsigned)TLI.getTargetData()-getTypeAlignmentPref(Ty);
+ int FrameIdx = FrameInfo-CreateStackObject(ByteSize, StackAlign);
return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
}
@@ -4242,9 +4244,12 @@
if (Op0.getValueType() == MVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
-// get the stack frame index of a 8 byte buffer
+// get the stack frame index of a 8 byte buffer, pessimistically aligned
MachineFunction MF = DAG.getMachineFunction();
-int SSFI = MF.getFrameInfo()-CreateStackObject(8, 8);
+const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
+unsigned StackAlign =
+ (unsigned)TLI.getTargetData()-getTypeAlignmentPref(F64Type);
+int SSFI = MF.getFrameInfo()-CreateStackObject(8, StackAlign);
// get address of 8 byte buffer
SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
// word offset constant for Hi/Lo address computation
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.342
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.343
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.342Thu Jan 11
06:24:14 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Jan 20 16:35:55 2007
@@ -244,17 +244,9 @@
const Type *Ty = AI-getAllocatedType();
uint64_t TySize = TLI.getTargetData()-getTypeSize(Ty);
unsigned Align =
- std::max((unsigned)TLI.getTargetData()-getTypeAlignment(Ty),
+ std::max((unsigned)TLI.getTargetData()-getTypeAlignmentPref(Ty),
AI-getAlignment());
-// If the alignment of the value is smaller than the size of the
-// value, and if the size of the value is particularly small
-// (= 8 bytes), round up to the size of the value for potentially
-// better performance.
-//
-// FIXME: This could be made better with a preferred alignment hook in
-// TargetData. It serves primarily to 8-byte align doubles for X86.
-if (Align TySize TySize = 8) Align = TySize;
TySize *= CUI-getZExtValue(); // Get total allocated size.
if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
StaticAllocaMap[AI] =
@@ -1729,8 +1721,9 @@
const Type *Ty = I.getAllocatedType();
uint64_t TySize = TLI.getTargetData()-getTypeSize(Ty);
- unsigned Align =
std::max((unsigned)TLI.getTargetData()-getTypeAlignment(Ty),
-I.getAlignment());
+ unsigned Align =
+std::max((unsigned)TLI.getTargetData()-getTypeAlignmentPref(Ty),
+ I.getAlignment());
SDOperand AllocSize = getValue(I.getArraySize());
MVT::ValueType IntPtr = TLI.getPointerTy();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.455 - 1.456 --- Log message: For PR1043: http://llvm.org/PR1043 : This is the final patch for this PR. It implements some minor cleanup in the use of IntegerType, to wit: 1. Type::getIntegerTypeMask - IntegerType::getBitMask 2. Type::Int*Ty changed to IntegerType* from Type* 3. ConstantInt::getType() returns IntegerType* now, not Type* This also fixes PR1120: http://llvm.org/PR1120 . Patch by Sheng Zhou. --- Diffs of the changes: (+1 -0) LegalizeDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.455 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.456 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.455 Thu Jan 11 20:11:51 2007 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 19 15:13:56 2007 @@ -21,6 +21,7 @@ #include llvm/Target/TargetOptions.h #include llvm/CallingConv.h #include llvm/Constants.h +#include llvm/DerivedTypes.h #include llvm/Support/MathExtras.h #include llvm/Support/CommandLine.h #include llvm/Support/Compiler.h ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.454 - 1.455
TargetLowering.cpp updated: 1.83 - 1.84
---
Log message:
Store default libgcc routine names and allow them to be redefined by target.
---
Diffs of the changes: (+205 -82)
LegalizeDAG.cpp| 210 -
TargetLowering.cpp | 77 +++
2 files changed, 205 insertions(+), 82 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.454
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.455
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.454 Fri Jan 5 17:33:44 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jan 11 20:11:51 2007
@@ -2284,11 +2284,11 @@
default: assert(0 Do not know how to expand this integer BinOp!);
case ISD::UDIV:
case ISD::SDIV:
- const char *FnName = Node-getOpcode() == ISD::UDIV
-? __udivsi3 : __divsi3;
+ RTLIB::Libcall LC = Node-getOpcode() == ISD::UDIV
+? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
SDOperand Dummy;
bool isSigned = Node-getOpcode() == ISD::SDIV;
- Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
+ Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned,
Dummy);
};
break;
}
@@ -2470,16 +2470,18 @@
} else {
assert(Node-getValueType(0) == MVT::i32
Cannot expand this binary operator!);
- const char *FnName = Node-getOpcode() == ISD::UREM
-? __umodsi3 : __modsi3;
+ RTLIB::Libcall LC = Node-getOpcode() == ISD::UREM
+? RTLIB::UREM_I32 : RTLIB::SREM_I32;
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
+ Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned,
Dummy);
}
} else {
// Floating point mod - fmod libcall.
-const char *FnName = Node-getValueType(0) == MVT::f32 ?
fmodf:fmod;
+RTLIB::Libcall LC = Node-getValueType(0) == MVT::f32
+ ? RTLIB::REM_F32 : RTLIB::REM_F64;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
+Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
+ false/*sign irrelevant*/, Dummy);
}
break;
}
@@ -2720,15 +2722,22 @@
case ISD::FSIN:
case ISD::FCOS: {
MVT::ValueType VT = Node-getValueType(0);
-const char *FnName = 0;
+RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
switch(Node-getOpcode()) {
-case ISD::FSQRT: FnName = VT == MVT::f32 ? sqrtf : sqrt; break;
-case ISD::FSIN: FnName = VT == MVT::f32 ? sinf : sin; break;
-case ISD::FCOS: FnName = VT == MVT::f32 ? cosf : cos; break;
+case ISD::FSQRT:
+ LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
+ break;
+case ISD::FSIN:
+ LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
+ break;
+case ISD::FCOS:
+ LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
+ break;
default: assert(0 Unreachable!);
}
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
+Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
+ false/*sign irrelevant*/, Dummy);
break;
}
}
@@ -2737,10 +2746,11 @@
break;
case ISD::FPOWI: {
// We always lower FPOWI into a libcall. No target support it yet.
-const char *FnName = Node-getValueType(0) == MVT::f32
-? __powisf2 : __powidf2;
+RTLIB::Libcall LC = Node-getValueType(0) == MVT::f32
+ ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
+Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
+ false/*sign irrelevant*/, Dummy);
break;
}
case ISD::BIT_CONVERT:
@@ -2909,24 +2919,29 @@
case Expand: {
// Convert f32 / f64 to i32 / i64.
MVT::ValueType VT = Op.getValueType();
- const char *FnName = 0;
+ RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
switch (Node-getOpcode()) {
case ISD::FP_TO_SINT:
if (Node-getOperand(0).getValueType() == MVT::f32)
- FnName = (VT == MVT::i32) ? __fixsfsi : __fixsfdi;
+ LC = (VT == MVT::i32)
+? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
else
- FnName = (VT == MVT::i32) ? __fixdfsi : __fixdfdi;
+ LC = (VT == MVT::i32)
+? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
break;
case ISD::FP_TO_UINT:
if (Node-getOperand(0).getValueType() == MVT::f32)
- FnName = (VT
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.452 - 1.453
---
Log message:
Bug in ExpandFCOPYSIGNToBitwiseOps(). Clear the old sign bit of operand 0
before or'ing in the sign bit of operand 1.
---
Diffs of the changes: (+14 -4)
LegalizeDAG.cpp | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.452
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.453
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.452 Thu Jan 4 15:56:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 5 15:31:51 2007
@@ -533,15 +533,17 @@
static
SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
SelectionDAG DAG, TargetLowering TLI) {
+ MVT::ValueType VT = Node-getValueType(0);
MVT::ValueType SrcVT = Node-getOperand(1).getValueType();
MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
+
// First get the sign bit of second operand.
- SDOperand Mask = (SrcVT == MVT::f64)
+ SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U 31), SrcVT);
- Mask = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask);
+ Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT,
Node-getOperand(1));
- SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask);
+ SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
// Shift right or sign-extend it if the two operands have different types.
int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
if (SizeDiff 0) {
@@ -550,8 +552,16 @@
SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
} else if (SizeDiff 0)
SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
- // Or the first operand with the sign bit.
+
+ // Clear the sign bit of first operand.
+ SDOperand Mask2 = (VT == MVT::f64)
+? DAG.getConstantFP(BitsToDouble(~(1ULL 63)), VT)
+: DAG.getConstantFP(BitsToFloat(~(1U 31)), VT);
+ Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
+ Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
+
+ // Or the value with the sign bit.
Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
return Result;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.451 - 1.452
---
Log message:
Expand fcopysign to a series of bitwise of operations when it's profitable to
do so.
---
Diffs of the changes: (+46 -19)
LegalizeDAG.cpp | 65 +++-
1 files changed, 46 insertions(+), 19 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.451
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.452
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.451 Tue Jan 2 22:22:32 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jan 4 15:56:39 2007
@@ -528,6 +528,35 @@
}
+/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
+/// operations.
+static
+SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
+ SelectionDAG DAG, TargetLowering TLI) {
+ MVT::ValueType SrcVT = Node-getOperand(1).getValueType();
+ MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
+ // First get the sign bit of second operand.
+ SDOperand Mask = (SrcVT == MVT::f64)
+? DAG.getConstantFP(BitsToDouble(1ULL 63), SrcVT)
+: DAG.getConstantFP(BitsToFloat(1U 31), SrcVT);
+ Mask = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask);
+ SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT,
Node-getOperand(1));
+ SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask);
+ // Shift right or sign-extend it if the two operands have different types.
+ int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
+ if (SizeDiff 0) {
+SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
+ DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
+SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
+ } else if (SizeDiff 0)
+SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
+ // Or the first operand with the sign bit.
+ SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
+ Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
+ return Result;
+}
+
+
/// LegalizeOp - We know that the specified value has a legal type.
/// Recursively ensure that the operands have legal types, then return the
/// result.
@@ -2314,10 +2343,12 @@
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Legal: break;
-case TargetLowering::Expand:
+case TargetLowering::Expand: {
// If this target supports fabs/fneg natively, do this efficiently.
- if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType())
- TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
+ if (TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
+ TargetLowering::Legal
+ TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
+ TargetLowering::Legal) {
// Get the sign bit of the RHS.
MVT::ValueType IVT =
Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
@@ -2337,24 +2368,14 @@
}
// Otherwise, do bitwise ops!
-
- // copysign - copysignf/copysign libcall.
- const char *FnName;
- if (Node-getValueType(0) == MVT::f32) {
-FnName = copysignf;
-if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
- Result = DAG.UpdateNodeOperands(Result, Tmp1,
-DAG.getNode(ISD::FP_ROUND, MVT::f32,
Tmp2));
- } else {
-FnName = copysign;
-if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
- Result = DAG.UpdateNodeOperands(Result, Tmp1,
- DAG.getNode(ISD::FP_EXTEND, MVT::f64,
Tmp2));
- }
- SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
+ MVT::ValueType NVT =
+Node-getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
+ Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
+ Result = DAG.getNode(ISD::BIT_CONVERT, Node-getValueType(0), Result);
+ Result = LegalizeOp(Result);
break;
}
+}
break;
case ISD::ADDC:
@@ -5123,6 +5144,12 @@
ExpandOp(Lo, Lo, Hi);
break;
}
+ case ISD::FCOPYSIGN: {
+Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
+if (getTypeAction(NVT) == Expand)
+ ExpandOp(Lo, Lo, Hi);
+break;
+ }
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: {
bool isSigned = Node-getOpcode() == ISD::SINT_TO_FP;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.450 - 1.451
---
Log message:
Clean up from recent changes. Comment the new parameter to ExpandLibCall.
Consolidate some lines of code and remove duplication.
---
Diffs of the changes: (+20 -24)
LegalizeDAG.cpp | 44
1 files changed, 20 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.450
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.451
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.450 Sat Dec 30 23:55:36 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 2 22:22:32 2007
@@ -2127,9 +2127,7 @@
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
-Entry.Node = Tmp2;
-Entry.Ty = IntPtrTy;
-Entry.isSigned = false;
+Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
@@ -2145,12 +2143,10 @@
FnName = memset;
} else if (Node-getOpcode() == ISD::MEMCPY ||
Node-getOpcode() == ISD::MEMMOVE) {
-Entry.Node = Tmp2; Entry.Ty = IntPtrTy; Entry.isSigned = false;
-Args.push_back(Entry);
-Entry.Node = Tmp3; Entry.Ty = IntPtrTy; Entry.isSigned = false;
-Args.push_back(Entry);
-Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
-Args.push_back(Entry);
+Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Entry.Node = Tmp2; Args.push_back(Entry);
+Entry.Node = Tmp3; Args.push_back(Entry);
+Entry.Node = Tmp4; Args.push_back(Entry);
FnName = Node-getOpcode() == ISD::MEMMOVE ? memmove : memcpy;
} else {
assert(0 Unknown op!);
@@ -2356,7 +2352,7 @@
DAG.getNode(ISD::FP_EXTEND, MVT::f64,
Tmp2));
}
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, false, Dummy);
+ Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
break;
@@ -2450,7 +2446,7 @@
// Floating point mod - fmod libcall.
const char *FnName = Node-getValueType(0) == MVT::f32 ?
fmodf:fmod;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false, Dummy);
+Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
}
break;
}
@@ -2699,7 +2695,7 @@
default: assert(0 Unreachable!);
}
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false, Dummy);
+Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
}
@@ -2711,7 +2707,7 @@
const char *FnName = Node-getValueType(0) == MVT::f32
? __powisf2 : __powidf2;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false, Dummy);
+Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
case ISD::BIT_CONVERT:
@@ -2897,7 +2893,7 @@
default: assert(0 Unreachable!);
}
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, false, Dummy);
+ Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
case Promote:
@@ -3621,14 +3617,14 @@
SDOperand Dummy;
Tmp1 = ExpandLibCall(FnName1,
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
- false, Dummy);
+ false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
CC = DAG.getCondCode(CC1);
if (FnName2) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
LHS = ExpandLibCall(FnName2,
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
-false, Dummy);
+false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
DAG.getCondCode(CC2));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
@@ -4836,9 +4832,9 @@
}
if (Node-getOperand(0).getValueType() == MVT::f32)
- Lo = ExpandLibCall(__fixsfdi, Node, false, Hi);
+ Lo = ExpandLibCall(__fixsfdi, Node, false/*sign irrelevant*/, Hi);
else
- Lo = ExpandLibCall(__fixdfdi, Node, false, Hi);
+ Lo = ExpandLibCall(__fixdfdi, Node, false/*sign irrelevant*/, Hi);
break;
case ISD::FP_TO_UINT:
@@ -4860,9 +4856,9 @@
}
if (Node-getOperand(0).getValueType() == MVT::f32)
- Lo = ExpandLibCall(__fixunssfdi, Node, false, Hi);
+ Lo = ExpandLibCall(__fixunssfdi, Node, false/*sign irrelevant*/, Hi);
else
- Lo =
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.449 - 1.450
SelectionDAGISel.cpp updated: 1.334 - 1.335
---
Log message:
For PR950: http://llvm.org/PR950 :
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
---
Diffs of the changes: (+119 -97)
LegalizeDAG.cpp | 108 ++-
SelectionDAGISel.cpp | 108 +--
2 files changed, 119 insertions(+), 97 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.449
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.450
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.449 Mon Dec 18 19:44:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Dec 30 23:55:36 2006
@@ -186,7 +186,7 @@
SDOperand CreateStackTemporary(MVT::ValueType VT);
- SDOperand ExpandLibCall(const char *Name, SDNode *Node,
+ SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
SDOperand Hi);
SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
SDOperand Source);
@@ -2122,33 +2122,42 @@
// operation to an explicit libcall as appropriate.
MVT::ValueType IntPtr = TLI.getPointerTy();
const Type *IntPtrTy = TLI.getTargetData()-getIntPtrType();
- std::vectorstd::pairSDOperand, const Type* Args;
+ TargetLowering::ArgListTy Args;
+ TargetLowering::ArgListEntry Entry;
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
-Args.push_back(std::make_pair(Tmp2, IntPtrTy));
+Entry.Node = Tmp2;
+Entry.Ty = IntPtrTy;
+Entry.isSigned = false;
+Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
if (Tmp3.getValueType() MVT::i32)
Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
else
Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
-Args.push_back(std::make_pair(Tmp3, Type::IntTy));
-Args.push_back(std::make_pair(Tmp4, IntPtrTy));
+Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
+Args.push_back(Entry);
+Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Args.push_back(Entry);
FnName = memset;
} else if (Node-getOpcode() == ISD::MEMCPY ||
Node-getOpcode() == ISD::MEMMOVE) {
-Args.push_back(std::make_pair(Tmp2, IntPtrTy));
-Args.push_back(std::make_pair(Tmp3, IntPtrTy));
-Args.push_back(std::make_pair(Tmp4, IntPtrTy));
+Entry.Node = Tmp2; Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Args.push_back(Entry);
+Entry.Node = Tmp3; Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Args.push_back(Entry);
+Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Args.push_back(Entry);
FnName = Node-getOpcode() == ISD::MEMMOVE ? memmove : memcpy;
} else {
assert(0 Unknown op!);
}
std::pairSDOperand,SDOperand CallResult =
-TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
+TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C,
false,
DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
Result = CallResult.second;
break;
@@ -2243,7 +2252,8 @@
const char *FnName = Node-getOpcode() == ISD::UDIV
? __udivsi3 : __divsi3;
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, Dummy);
+ bool isSigned = Node-getOpcode() == ISD::SDIV;
+ Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
};
break;
}
@@ -2346,7 +2356,7 @@
DAG.getNode(ISD::FP_EXTEND, MVT::f64,
Tmp2));
}
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, Dummy);
+ Result = ExpandLibCall(FnName, Node, false, Dummy);
break;
}
break;
@@ -2419,6 +2429,7 @@
break;
case TargetLowering::Expand:
unsigned DivOpc=
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.443 - 1.444
---
Log message:
Fix select_cc, select expansion to soft-fp bugs.
---
Diffs of the changes: (+11 -3)
LegalizeDAG.cpp | 14 +++---
1 files changed, 11 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.443
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.444
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.443 Fri Dec 15 01:36:19 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 15 16:42:55 2006
@@ -4705,18 +4705,24 @@
SDOperand LL, LH, RL, RH;
ExpandOp(Node-getOperand(1), LL, LH);
ExpandOp(Node-getOperand(2), RL, RH);
+if (getTypeAction(NVT) == Expand)
+ NVT = TLI.getTypeToExpandTo(NVT);
Lo = DAG.getNode(ISD::SELECT, NVT, Node-getOperand(0), LL, RL);
-Hi = DAG.getNode(ISD::SELECT, NVT, Node-getOperand(0), LH, RH);
+if (VT != MVT::f32)
+ Hi = DAG.getNode(ISD::SELECT, NVT, Node-getOperand(0), LH, RH);
break;
}
case ISD::SELECT_CC: {
SDOperand TL, TH, FL, FH;
ExpandOp(Node-getOperand(2), TL, TH);
ExpandOp(Node-getOperand(3), FL, FH);
+if (getTypeAction(NVT) == Expand)
+ NVT = TLI.getTypeToExpandTo(NVT);
Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node-getOperand(0),
Node-getOperand(1), TL, FL, Node-getOperand(4));
-Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node-getOperand(0),
- Node-getOperand(1), TH, FH, Node-getOperand(4));
+if (VT != MVT::f32)
+ Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node-getOperand(0),
+ Node-getOperand(1), TH, FH, Node-getOperand(4));
break;
}
case ISD::ANY_EXTEND:
@@ -4761,6 +4767,8 @@
// f32 / f64 must be expanded to i32 / i64.
if (VT == MVT::f32 || VT == MVT::f64) {
Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
+ if (getTypeAction(NVT) == Expand)
+ExpandOp(Lo, Lo, Hi);
break;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.444 - 1.445
---
Log message:
Expand fabs / fneg to and / xor.
---
Diffs of the changes: (+22 -3)
LegalizeDAG.cpp | 25 ++---
1 files changed, 22 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.444
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.445
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.444 Fri Dec 15 16:42:55 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 15 18:52:40 2006
@@ -5055,9 +5055,6 @@
case ISD::SREM: Lo = ExpandLibCall(__moddi3 , Node, Hi); break;
case ISD::UREM: Lo = ExpandLibCall(__umoddi3, Node, Hi); break;
- case ISD::FNEG:
-Lo = ExpandLibCall(((VT == MVT::f32) ? __negsf2 : __negdf2), Node, Hi);
-break;
case ISD::FADD:
Lo = ExpandLibCall(((VT == MVT::f32) ? __addsf3 : __adddf3), Node, Hi);
break;
@@ -5107,6 +5104,28 @@
Lo = ExpandLibCall(FnName, Node, Hi);
break;
}
+ case ISD::FABS: {
+SDOperand Mask = (VT == MVT::f64)
+ ? DAG.getConstantFP(BitsToDouble(~(1ULL 63)), VT)
+ : DAG.getConstantFP(BitsToFloat(~(1U 31)), VT);
+Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
+Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
+Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
+if (getTypeAction(NVT) == Expand)
+ ExpandOp(Lo, Lo, Hi);
+break;
+ }
+ case ISD::FNEG: {
+SDOperand Mask = (VT == MVT::f64)
+ ? DAG.getConstantFP(BitsToDouble(1ULL 63), VT)
+ : DAG.getConstantFP(BitsToFloat(1U 31), VT);
+Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
+Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
+Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
+if (getTypeAction(NVT) == Expand)
+ ExpandOp(Lo, Lo, Hi);
+break;
+ }
}
// Make sure the resultant values have been legalized themselves, unless this
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.445 - 1.446
---
Log message:
Allow promoted FP_TO_UINT / FP_TO_SINT to expand operand.
---
Diffs of the changes: (+1 -2)
LegalizeDAG.cpp |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.445
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.446
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.445 Fri Dec 15 18:52:40 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 15 20:10:30 2006
@@ -3155,6 +3155,7 @@
case ISD::FP_TO_UINT:
switch (getTypeAction(Node-getOperand(0).getValueType())) {
case Legal:
+case Expand:
Tmp1 = Node-getOperand(0);
break;
case Promote:
@@ -3162,8 +3163,6 @@
// special.
Tmp1 = PromoteOp(Node-getOperand(0));
break;
-case Expand:
- assert(0 not implemented);
}
// If we're promoting a UINT to a larger size, check to see if the new node
// will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.446 - 1.447 --- Log message: Expand FP undef --- Diffs of the changes: (+1 -0) LegalizeDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.446 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.447 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.446 Fri Dec 15 20:10:30 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 15 20:20:50 2006 @@ -4523,6 +4523,7 @@ assert(0 Do not know how to expand this operator!); abort(); case ISD::UNDEF: +NVT = TLI.getTypeToExpandTo(VT); Lo = DAG.getNode(ISD::UNDEF, NVT); Hi = DAG.getNode(ISD::UNDEF, NVT); break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.441 - 1.442
---
Log message:
Expand FP compares to soft-fp call(s)
---
Diffs of the changes: (+102 -7)
LegalizeDAG.cpp | 109
1 files changed, 102 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.441
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.442
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.441 Thu Dec 14 13:17:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Dec 14 20:59:56 2006
@@ -2011,10 +2011,10 @@
isCustom = true;
// FALLTHROUGH.
case TargetLowering::Legal:
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node-getOperand(2));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
if (isCustom) {
-Tmp3 = TLI.LowerOperation(Result, DAG);
-if (Tmp3.Val) Result = Tmp3;
+Tmp4 = TLI.LowerOperation(Result, DAG);
+if (Tmp4.Val) Result = Tmp4;
}
break;
case TargetLowering::Promote: {
@@ -2045,7 +2045,7 @@
}
Tmp1 = LegalizeOp(Tmp1);
Tmp2 = LegalizeOp(Tmp2);
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node-getOperand(2));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
Result = LegalizeOp(Result);
break;
}
@@ -2055,7 +2055,7 @@
MVT::ValueType VT = Node-getValueType(0);
Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
- Node-getOperand(2));
+ Tmp3);
break;
}
break;
@@ -3533,10 +3533,104 @@
}
}
break;
- case Expand:
+ case Expand: {
+MVT::ValueType VT = LHS.getValueType();
+if (VT == MVT::f32 || VT == MVT::f64) {
+ // Expand into one or more soft-fp libcall(s).
+ const char *FnName1 = NULL, *FnName2 = NULL;
+ ISD::CondCode CC1, CC2;
+ switch (castCondCodeSDNode(CC)-get()) {
+ case ISD::SETEQ:
+ case ISD::SETOEQ:
+FnName1 = (VT == MVT::f32) ? __eqsf2 : __eqdf2;
+CC1 = ISD::SETEQ;
+break;
+ case ISD::SETNE:
+ case ISD::SETUNE:
+FnName1 = (VT == MVT::f32) ? __nesf2 : __nedf2;
+CC1 = ISD::SETNE;
+break;
+ case ISD::SETGE:
+ case ISD::SETOGE:
+FnName1 = (VT == MVT::f32) ? __gesf2 : __gedf2;
+CC1 = ISD::SETGE;
+break;
+ case ISD::SETLT:
+ case ISD::SETOLT:
+FnName1 = (VT == MVT::f32) ? __ltsf2 : __ltdf2;
+CC1 = ISD::SETLT;
+break;
+ case ISD::SETLE:
+ case ISD::SETOLE:
+FnName1 = (VT == MVT::f32) ? __lesf2 : __ledf2;
+CC1 = ISD::SETLE;
+break;
+ case ISD::SETGT:
+ case ISD::SETOGT:
+FnName1 = (VT == MVT::f32) ? __gtsf2 : __gtdf2;
+CC1 = ISD::SETGT;
+break;
+ case ISD::SETUO:
+ case ISD::SETO:
+FnName1 = (VT == MVT::f32) ? __unordsf2 : __unorddf2;
+CC1 = castCondCodeSDNode(CC)-get() == ISD::SETO
+ ? ISD::SETEQ : ISD::SETNE;
+break;
+ default:
+FnName1 = (VT == MVT::f32) ? __unordsf2 : __unorddf2;
+CC1 = ISD::SETNE;
+switch (castCondCodeSDNode(CC)-get()) {
+case ISD::SETONE:
+ // SETONE = SETOLT | SETOGT
+ FnName1 = (VT == MVT::f32) ? __ltsf2 : __ltdf2;
+ CC1 = ISD::SETLT;
+ // Fallthrough
+case ISD::SETUGT:
+ FnName2 = (VT == MVT::f32) ? __gtsf2 : __gtdf2;
+ CC2 = ISD::SETGT;
+ break;
+case ISD::SETUGE:
+ FnName2 = (VT == MVT::f32) ? __gesf2 : __gedf2;
+ CC2 = ISD::SETGE;
+ break;
+case ISD::SETULT:
+ FnName2 = (VT == MVT::f32) ? __ltsf2 : __ltdf2;
+ CC2 = ISD::SETLT;
+ break;
+case ISD::SETULE:
+ FnName2 = (VT == MVT::f32) ? __lesf2 : __ledf2;
+ CC2 = ISD::SETLE;
+ break;
+ case ISD::SETUEQ:
+FnName2 = (VT == MVT::f32) ? __eqsf2 : __eqdf2;
+CC2 = ISD::SETEQ;
+break;
+default: assert(0 Unsupported FP setcc!);
+}
+ }
+
+ SDOperand Dummy;
+ Tmp1 = ExpandLibCall(FnName1,
+ DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
Dummy);
+ Tmp2 = DAG.getConstant(0, MVT::i32);
+ CC = DAG.getCondCode(CC1);
+ if (FnName2) {
+Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
+LHS = ExpandLibCall(FnName2,
+ DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
Dummy);
+Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
+ DAG.getCondCode(CC2));
+Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.442 - 1.443
---
Log message:
silence a bogus warning
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.442
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.443
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.442 Thu Dec 14 20:59:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 15 01:36:19 2006
@@ -3538,7 +3538,7 @@
if (VT == MVT::f32 || VT == MVT::f64) {
// Expand into one or more soft-fp libcall(s).
const char *FnName1 = NULL, *FnName2 = NULL;
- ISD::CondCode CC1, CC2;
+ ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
switch (castCondCodeSDNode(CC)-get()) {
case ISD::SETEQ:
case ISD::SETOEQ:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.439 - 1.440
SelectionDAGISel.cpp updated: 1.330 - 1.331
---
Log message:
More soft-fp work.
---
Diffs of the changes: (+41 -37)
LegalizeDAG.cpp | 13 +++---
SelectionDAGISel.cpp | 65 +--
2 files changed, 41 insertions(+), 37 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.439
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.440
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.439 Tue Dec 12 21:19:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Dec 13 14:57:08 2006
@@ -488,9 +488,9 @@
}
}
-/// ExpandConstantFP - Expands the ConstantFP node by either converting it to
-/// integer constant or spilling the constant to memory.
-static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool ToMem,
+/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
+/// a load from the constant pool.
+static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
SelectionDAG DAG, TargetLowering TLI) {
bool Extend = false;
@@ -502,7 +502,7 @@
bool isDouble = VT == MVT::f64;
ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
Type::FloatTy, CFP-getValue());
- if (!ToMem) {
+ if (!UseCP) {
double Val = LLVMC-getValue();
return isDouble
? DAG.getConstant(DoubleToBits(Val), MVT::i64)
@@ -4434,6 +4434,8 @@
case ISD::ConstantFP: {
ConstantFPSDNode *CFP = castConstantFPSDNode(Node);
Lo = ExpandConstantFP(CFP, false, DAG, TLI);
+if (getTypeAction(Lo.getValueType()) == Expand)
+ ExpandOp(Lo, Lo, Hi);
break;
}
case ISD::BUILD_PAIR:
@@ -4526,6 +4528,9 @@
// f32-i32 or f64-i64 one to one expansion.
// Remember that we legalized the chain.
AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
+// Recursively expand the new load.
+if (getTypeAction(NVT) == Expand)
+ ExpandOp(Lo, Lo, Hi);
break;
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.330
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.331
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.330Tue Dec 12
18:50:17 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Dec 13 14:57:08 2006
@@ -346,13 +346,10 @@
// If this value is represented with multiple target registers, make sure
// to create enough consecutive registers of the right (smaller) type.
- unsigned NT = VT-1; // Find the type to use.
- while (TLI.getNumElements((MVT::ValueType)NT) != 1)
---NT;
-
- unsigned R = MakeReg((MVT::ValueType)NT);
+ VT = TLI.getTypeToExpandTo(VT);
+ unsigned R = MakeReg(VT);
for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
-MakeReg((MVT::ValueType)NT);
+MakeReg(VT);
return R;
}
@@ -689,19 +686,26 @@
// If this type is not legal, make it so now.
if (VT != MVT::Vector) {
-MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
-
-N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
-if (DestVT VT) {
+if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
// Source must be expanded. This input value is actually coming from the
// register pair VMI-second and VMI-second+1.
- N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
- DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
-} else if (DestVT VT) { // Promotion case
- if (MVT::isFloatingPoint(VT))
-N = DAG.getNode(ISD::FP_ROUND, VT, N);
- else
-N = DAG.getNode(ISD::TRUNCATE, VT, N);
+ MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
+ unsigned NumVals = TLI.getNumElements(VT);
+ N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+ if (NumVals == 1)
+N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
+ else {
+assert(NumVals == 2 1 to 4 (and more) expansion not implemented!);
+N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
+ DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1,
DestVT));
+ }
+} else {
+ MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
+ N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+ if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
+N = MVT::isFloatingPoint(VT)
+ ? DAG.getNode(ISD::FP_ROUND, VT, N)
+ : DAG.getNode(ISD::TRUNCATE, VT, N);
}
} else {
// Otherwise, if this is a vector, make it available as a generic vector
@@ -2916,12 +2920,8 @@
// If this is a large integer, it needs to be broken up into small
// integers. Figure out what the destination type is and how many
small
// integers it
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.432 - 1.433
---
Log message:
- When expanding a bit_convert whose src operand is also to be expanded and
its expansion result type is equal to the result type of the bit_convert,
e.g. (i64 bit_convert (f64 op)) if FP is not legal
returns the result of the expanded source operand.
- Store f32 / f64 may be expanded to a single store i32/i64.
---
Diffs of the changes: (+16 -2)
LegalizeDAG.cpp | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.432
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.433
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.432 Mon Dec 11 23:22:21 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 12 13:53:13 2006
@@ -1735,7 +1735,7 @@
}
} else {
ExpandOp(Node-getOperand(1), Lo, Hi);
- IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
+ IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
if (!TLI.isLittleEndian())
std::swap(Lo, Hi);
@@ -1743,6 +1743,13 @@
Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST-getSrcValue(),
ST-getSrcValueOffset());
+
+if (Hi.Val == NULL) {
+ // Must be int - float one-to-one expansion.
+ Result = Lo;
+ break;
+}
+
Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
getIntPtrConstant(IncrementSize));
assert(isTypeLegal(Tmp2.getValueType())
@@ -4593,7 +4600,14 @@
// f32 / f64 must be expanded to i32 / i64.
if (VT == MVT::f32 || VT == MVT::f64) {
Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
- Hi = SDOperand();
+ break;
+}
+
+// If source operand will be expanded to the same type as VT, i.e.
+// i64 - f64, i32 - f32, expand the source operand instead.
+MVT::ValueType VT0 = Node-getOperand(0).getValueType();
+if (getTypeAction(VT0) == Expand TLI.getTypeToTransformTo(VT0) == VT) {
+ ExpandOp(Node-getOperand(0), Lo, Hi);
break;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.433 - 1.434
---
Log message:
Expand ConstantFP to load from CP if float types are being expanded.
---
Diffs of the changes: (+44 -27)
LegalizeDAG.cpp | 71 ++--
1 files changed, 44 insertions(+), 27 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.433
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.434
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.433 Tue Dec 12 13:53:13 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 12 15:32:44 2006
@@ -488,6 +488,37 @@
}
}
+/// ExpandConstantFP - Expands the ConstantFP node by spilling the constant to
+/// memory.
+static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, SelectionDAG DAG,
+ TargetLowering TLI) {
+ bool Extend = false;
+
+ // If a FP immediate is precise when represented as a float and if the
+ // target can do an extending load from float to double, we put it into
+ // the constant pool as a float, even if it's is statically typed as a
+ // double.
+ MVT::ValueType VT = CFP-getValueType(0);
+ bool isDouble = VT == MVT::f64;
+ ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
+ Type::FloatTy, CFP-getValue());
+ if (isDouble CFP-isExactlyValue((float)CFP-getValue())
+ // Only do this if the target has a native EXTLOAD instruction from f32.
+ TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
+LLVMC = castConstantFP(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
+VT = MVT::f32;
+Extend = true;
+ }
+
+ SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
+ if (Extend) {
+return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
+ CPIdx, NULL, 0, MVT::f32);
+ } else {
+return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
+ }
+}
+
/// LegalizeOp - We know that the specified value has a legal type.
/// Recursively ensure that the operands have legal types, then return the
@@ -775,33 +806,7 @@
}
// FALLTHROUGH
case TargetLowering::Expand:
- // Otherwise we need to spill the constant to memory.
- bool Extend = false;
-
- // If a FP immediate is precise when represented as a float and if the
- // target can do an extending load from float to double, we put it into
- // the constant pool as a float, even if it's is statically typed as a
- // double.
- MVT::ValueType VT = CFP-getValueType(0);
- bool isDouble = VT == MVT::f64;
- ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
- Type::FloatTy, CFP-getValue());
- if (isDouble CFP-isExactlyValue((float)CFP-getValue())
- // Only do this if the target has a native EXTLOAD instruction from
- // f32.
- TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
-LLVMC =
castConstantFP(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
-VT = MVT::f32;
-Extend = true;
- }
-
- SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
- if (Extend) {
-Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
-CPIdx, NULL, 0, MVT::f32);
- } else {
-Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
- }
+ Result = ExpandConstantFP(CFP, DAG, TLI);
}
break;
}
@@ -4398,6 +4403,12 @@
Hi = DAG.getConstant(Cst MVT::getSizeInBits(NVT), NVT);
break;
}
+ case ISD::ConstantFP: {
+ConstantFPSDNode *CFP = castConstantFPSDNode(Node);
+SDOperand Tmp = ExpandConstantFP(CFP, DAG, TLI);
+ExpandOp(Tmp, Lo, Hi);
+break;
+ }
case ISD::BUILD_PAIR:
// Return the operands.
Lo = Node-getOperand(0);
@@ -4484,6 +4495,12 @@
if (ExtType == ISD::NON_EXTLOAD) {
Lo = DAG.getLoad(NVT, Ch, Ptr, LD-getSrcValue(),
LD-getSrcValueOffset());
+ if (VT == MVT::f32 || VT == MVT::f64) {
+// f32-i32 or f64-i64 one to one expansion.
+// Remember that we legalized the chain.
+AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
+break;
+ }
// Increment the pointer to the other half.
unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.434 - 1.435 --- Log message: Soft fp FNEG, SINT_TO_FP, UINT_TO_FP libcall expansion. --- Diffs of the changes: (+20 -1) LegalizeDAG.cpp | 21 - 1 files changed, 20 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.434 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.435 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.434 Tue Dec 12 15:32:44 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 12 15:51:17 2006 @@ -4902,7 +4902,10 @@ case ISD::UDIV: Lo = ExpandLibCall(__udivdi3, Node, Hi); break; case ISD::SREM: Lo = ExpandLibCall(__moddi3 , Node, Hi); break; case ISD::UREM: Lo = ExpandLibCall(__umoddi3, Node, Hi); break; - + + case ISD::FNEG: +Lo = ExpandLibCall(((VT == MVT::f32) ? __negsf2 : __negdf2), Node, Hi); +break; case ISD::FADD: Lo = ExpandLibCall(((VT == MVT::f32) ? __addsf3 : __adddf3), Node, Hi); break; @@ -4921,6 +4924,22 @@ case ISD::FP_ROUND: Lo = ExpandLibCall(__truncdfsf2, Node, Hi); break; + case ISD::SINT_TO_FP: +if (Node-getOperand(0).getValueType() == MVT::i64) + Lo = ExpandLibCall(((VT == MVT::f32) ? __floatdisf : __floatdidf), + Node, Hi); +else + Lo = ExpandLibCall(((VT == MVT::f32) ? __floatsisf : __floatsidf), + Node, Hi); +break; + case ISD::UINT_TO_FP: +if (Node-getOperand(0).getValueType() == MVT::i64) + Lo = ExpandLibCall(((VT == MVT::f32) ? __floatundisf : __floatundidf), + Node, Hi); +else + Lo = ExpandLibCall(((VT == MVT::f32) ? __floatunsisf : __floatunsidf), + Node, Hi); +break; } // Make sure the resultant values have been legalized themselves, unless this ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.435 - 1.436
---
Log message:
Expand FP constant to integers if FP types are not legal.
---
Diffs of the changes: (+13 -7)
LegalizeDAG.cpp | 20 +---
1 files changed, 13 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.435
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.436
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.435 Tue Dec 12 15:51:17 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 12 16:19:28 2006
@@ -488,10 +488,10 @@
}
}
-/// ExpandConstantFP - Expands the ConstantFP node by spilling the constant to
-/// memory.
-static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, SelectionDAG DAG,
- TargetLowering TLI) {
+/// ExpandConstantFP - Expands the ConstantFP node by either converting it to
+/// integer constant or spilling the constant to memory.
+static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool ToMem,
+ SelectionDAG DAG, TargetLowering TLI) {
bool Extend = false;
// If a FP immediate is precise when represented as a float and if the
@@ -502,6 +502,13 @@
bool isDouble = VT == MVT::f64;
ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
Type::FloatTy, CFP-getValue());
+ if (!ToMem) {
+double Val = LLVMC-getValue();
+return isDouble
+ ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
+ : DAG.getConstant(FloatToBits(Val), MVT::i32);
+ }
+
if (isDouble CFP-isExactlyValue((float)CFP-getValue())
// Only do this if the target has a native EXTLOAD instruction from f32.
TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
@@ -806,7 +813,7 @@
}
// FALLTHROUGH
case TargetLowering::Expand:
- Result = ExpandConstantFP(CFP, DAG, TLI);
+ Result = ExpandConstantFP(CFP, true, DAG, TLI);
}
break;
}
@@ -4405,8 +4412,7 @@
}
case ISD::ConstantFP: {
ConstantFPSDNode *CFP = castConstantFPSDNode(Node);
-SDOperand Tmp = ExpandConstantFP(CFP, DAG, TLI);
-ExpandOp(Tmp, Lo, Hi);
+Lo = ExpandConstantFP(CFP, false, DAG, TLI);
break;
}
case ISD::BUILD_PAIR:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.436 - 1.437
---
Log message:
Expand f32 / f64 to i32 / i64 conversion to soft-fp library calls.
---
Diffs of the changes: (+23 -2)
LegalizeDAG.cpp | 25 +++--
1 files changed, 23 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.436
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.437
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.436 Tue Dec 12 16:19:28 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 12 19:57:55 2006
@@ -2860,8 +2860,29 @@
break;
}
break;
-case Expand:
- assert(0 Shouldn't need to expand other operators here!);
+case Expand: {
+ // Convert f32 / f64 to i32 / i64.
+ MVT::ValueType VT = Op.getValueType();
+ const char *FnName = 0;
+ switch (Node-getOpcode()) {
+ case ISD::FP_TO_SINT:
+if (Node-getOperand(0).getValueType() == MVT::f32)
+ FnName = (VT == MVT::i32) ? __fixsfsi : __fixsfdi;
+else
+ FnName = (VT == MVT::i32) ? __fixdfsi : __fixdfdi;
+break;
+ case ISD::FP_TO_UINT:
+if (Node-getOperand(0).getValueType() == MVT::f32)
+ FnName = (VT == MVT::i32) ? __fixunssfsi : __fixunssfdi;
+else
+ FnName = (VT == MVT::i32) ? __fixunsdfsi : __fixunsdfdi;
+break;
+ default: assert(0 Unreachable!);
+ }
+ SDOperand Dummy;
+ Result = ExpandLibCall(FnName, Node, Dummy);
+ break;
+}
case Promote:
Tmp1 = PromoteOp(Node-getOperand(0));
Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.437 - 1.438
---
Log message:
Expand fsqrt, fsin, and fcos to libcalls.
---
Diffs of the changes: (+25 -10)
LegalizeDAG.cpp | 35 +--
1 files changed, 25 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.437
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.438
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.437 Tue Dec 12 19:57:55 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 12 20:38:13 2006
@@ -4951,23 +4951,38 @@
case ISD::FP_ROUND:
Lo = ExpandLibCall(__truncdfsf2, Node, Hi);
break;
- case ISD::SINT_TO_FP:
+ case ISD::SINT_TO_FP: {
+const char *FnName = 0;
if (Node-getOperand(0).getValueType() == MVT::i64)
- Lo = ExpandLibCall(((VT == MVT::f32) ? __floatdisf : __floatdidf),
- Node, Hi);
+ FnName = (VT == MVT::f32) ? __floatdisf : __floatdidf;
else
- Lo = ExpandLibCall(((VT == MVT::f32) ? __floatsisf : __floatsidf),
- Node, Hi);
+ FnName = (VT == MVT::f32) ? __floatsisf : __floatsidf;
+Lo = ExpandLibCall(FnName, Node, Hi);
break;
- case ISD::UINT_TO_FP:
+ }
+ case ISD::UINT_TO_FP: {
+const char *FnName = 0;
if (Node-getOperand(0).getValueType() == MVT::i64)
- Lo = ExpandLibCall(((VT == MVT::f32) ? __floatundisf :
__floatundidf),
- Node, Hi);
+ FnName = (VT == MVT::f32) ? __floatundisf : __floatundidf;
else
- Lo = ExpandLibCall(((VT == MVT::f32) ? __floatunsisf :
__floatunsidf),
- Node, Hi);
+ FnName = (VT == MVT::f32) ? __floatunsisf : __floatunsidf;
+Lo = ExpandLibCall(FnName, Node, Hi);
break;
}
+ case ISD::FSQRT:
+ case ISD::FSIN:
+ case ISD::FCOS: {
+const char *FnName = 0;
+switch(Node-getOpcode()) {
+case ISD::FSQRT: FnName = (VT == MVT::f32) ? sqrtf : sqrt; break;
+case ISD::FSIN: FnName = (VT == MVT::f32) ? sinf : sin; break;
+case ISD::FCOS: FnName = (VT == MVT::f32) ? cosf : cos; break;
+default: assert(0 Unreachable!);
+}
+Lo = ExpandLibCall(FnName, Node, Hi);
+break;
+ }
+ }
// Make sure the resultant values have been legalized themselves, unless this
// is a type that requires multi-step expansion.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.438 - 1.439
---
Log message:
Expand (f64 extload f32) to (f64 fp_ext (load f32)) if f64 type action is
expand.
---
Diffs of the changes: (+10 -0)
LegalizeDAG.cpp | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.438
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.439
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.438 Tue Dec 12 20:38:13 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 12 21:19:57 2006
@@ -4547,6 +4547,16 @@
std::swap(Lo, Hi);
} else {
MVT::ValueType EVT = LD-getLoadedVT();
+
+ if (VT == MVT::f64 EVT == MVT::f32) {
+// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
+SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD-getSrcValue(),
+ LD-getSrcValueOffset());
+// Remember that we legalized the chain.
+AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
+ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
+break;
+ }
if (EVT == NVT)
Lo = DAG.getLoad(NVT, Ch, Ptr, LD-getSrcValue(),
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.426 - 1.427
---
Log message:
Revert changes that broke oggenc on ppc
---
Diffs of the changes: (+9 -14)
LegalizeDAG.cpp | 23 +--
1 files changed, 9 insertions(+), 14 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.426
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.427
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.426 Mon Dec 11 00:50:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 12:53:38 2006
@@ -1547,10 +1547,7 @@
if (Tmp2.getValueType() != MVT::Vector) {
SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
- if (Hi.Val)
-Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3,
Hi,Tmp3);
- else
-Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
+ Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
Result = LegalizeOp(Result);
} else {
SDNode *InVal = Tmp2.Val;
@@ -1612,10 +1609,8 @@
ExpandOp(Node-getOperand(i), Lo, Hi);
NewValues.push_back(Lo);
NewValues.push_back(Node-getOperand(i+1));
- if (Hi.Val) {
-NewValues.push_back(Hi);
-NewValues.push_back(Node-getOperand(i+1));
- }
+ NewValues.push_back(Hi);
+ NewValues.push_back(Node-getOperand(i+1));
break;
}
case Promote:
@@ -4572,10 +4567,12 @@
Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
}
+MVT::ValueType NVT = Node-getValueType(0);
// f32 / f64 must be expanded to i32 / i64.
-if (VT == MVT::f32 || VT == MVT::f64) {
- Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
- Hi = SDOperand();
+if (NVT == MVT::f32 || NVT == MVT::f64) {
+ Lo = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToTransformTo(NVT),
+ Node-getOperand(0));
+ Hi = DAG.getConstant(0, TLI.getTypeToTransformTo(NVT));
break;
}
@@ -4878,9 +4875,7 @@
// is a type that requires multi-step expansion.
if (getTypeAction(NVT) != Expand NVT != MVT::isVoid) {
Lo = LegalizeOp(Lo);
-if (Hi.Val)
- // Don't legalize the high part if it is expanded to a single node.
- Hi = LegalizeOp(Hi);
+Hi = LegalizeOp(Hi);
}
// Remember in a map if the values will be reused later.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.427 - 1.428
---
Log message:
Re-apply changes that were backed out and fix a naughty typo.
---
Diffs of the changes: (+15 -10)
LegalizeDAG.cpp | 25 +++--
1 files changed, 15 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.427
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.428
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.427 Mon Dec 11 12:53:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 13:27:14 2006
@@ -1547,7 +1547,10 @@
if (Tmp2.getValueType() != MVT::Vector) {
SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
- Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
+ if (Hi.Val)
+Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3,
Hi,Tmp3);
+ else
+Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
Result = LegalizeOp(Result);
} else {
SDNode *InVal = Tmp2.Val;
@@ -1609,8 +1612,10 @@
ExpandOp(Node-getOperand(i), Lo, Hi);
NewValues.push_back(Lo);
NewValues.push_back(Node-getOperand(i+1));
- NewValues.push_back(Hi);
- NewValues.push_back(Node-getOperand(i+1));
+ if (Hi.Val) {
+NewValues.push_back(Hi);
+NewValues.push_back(Node-getOperand(i+1));
+ }
break;
}
case Promote:
@@ -4567,18 +4572,16 @@
Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
}
-MVT::ValueType NVT = Node-getValueType(0);
// f32 / f64 must be expanded to i32 / i64.
-if (NVT == MVT::f32 || NVT == MVT::f64) {
- Lo = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToTransformTo(NVT),
- Node-getOperand(0));
- Hi = DAG.getConstant(0, TLI.getTypeToTransformTo(NVT));
+if (VT == MVT::f32 || VT == MVT::f64) {
+ Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
+ Hi = SDOperand();
break;
}
// Turn this into a load/store pair by default.
if (Tmp.Val == 0)
- Tmp = ExpandBIT_CONVERT(NVT, Node-getOperand(0));
+ Tmp = ExpandBIT_CONVERT(VT, Node-getOperand(0));
ExpandOp(Tmp, Lo, Hi);
break;
@@ -4875,7 +4878,9 @@
// is a type that requires multi-step expansion.
if (getTypeAction(NVT) != Expand NVT != MVT::isVoid) {
Lo = LegalizeOp(Lo);
-Hi = LegalizeOp(Hi);
+if (Hi.Val)
+ // Don't legalize the high part if it is expanded to a single node.
+ Hi = LegalizeOp(Hi);
}
// Remember in a map if the values will be reused later.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.428 - 1.429
---
Log message:
Change inferred cast creation calls to more specific cast creations.
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.428
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.429
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.428 Mon Dec 11 13:27:14 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 19:17:40 2006
@@ -790,7 +790,7 @@
// Only do this if the target has a native EXTLOAD instruction from
// f32.
TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
-LLVMC = castConstantFP(ConstantExpr::getCast(LLVMC, Type::FloatTy));
+LLVMC = castConstantFP(ConstantExpr::getFPCast(LLVMC,
Type::FloatTy));
VT = MVT::f32;
Extend = true;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.429 - 1.430
---
Log message:
Revert Nate's patch to fix X86/store-fp-constant.ll. With the dag combiner
and legalizer separated like they currently are, I don't see a way to handle
this xform.
---
Diffs of the changes: (+18 -0)
LegalizeDAG.cpp | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.429
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.430
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.429 Mon Dec 11 19:17:40 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 22:18:56 2006
@@ -1648,6 +1648,24 @@
Tmp2 = LegalizeOp(ST-getBasePtr()); // Legalize the pointer.
if (!ST-isTruncatingStore()) {
+ // Turn 'store float 1.0, Ptr' - 'store int 0x12345678, Ptr'
+ // FIXME: We shouldn't do this for TargetConstantFP's.
+ // FIXME: move this to the DAG Combiner! Note that we can't regress due
+ // to phase ordering between legalized code and the dag combiner. This
+ // probably means that we need to integrate dag combiner and legalizer
+ // together.
+ if (ConstantFPSDNode *CFP = dyn_castConstantFPSDNode(ST-getValue())) {
+if (CFP-getValueType(0) == MVT::f32) {
+ Tmp3 = DAG.getConstant(FloatToBits(CFP-getValue()), MVT::i32);
+} else {
+ assert(CFP-getValueType(0) == MVT::f64 Unknown FP type!);
+ Tmp3 = DAG.getConstant(DoubleToBits(CFP-getValue()), MVT::i64);
+}
+Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST-getSrcValue(),
+ ST-getSrcValueOffset());
+break;
+ }
+
switch (getTypeAction(ST-getStoredVT())) {
case Legal: {
Tmp3 = LegalizeOp(ST-getValue());
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.431 - 1.432
---
Log message:
fit in 80 cols
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.431
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.432
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.431 Mon Dec 11 23:21:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 23:22:21 2006
@@ -790,7 +790,7 @@
// Only do this if the target has a native EXTLOAD instruction from
// f32.
TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
-LLVMC = castConstantFP(ConstantExpr::getFPTrunc(LLVMC,
Type::FloatTy));
+LLVMC =
castConstantFP(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
VT = MVT::f32;
Extend = true;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.430 - 1.431
---
Log message:
this can only be fptrunc.
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.430
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.431
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.430 Mon Dec 11 22:18:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 23:21:51 2006
@@ -790,7 +790,7 @@
// Only do this if the target has a native EXTLOAD instruction from
// f32.
TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
-LLVMC = castConstantFP(ConstantExpr::getFPCast(LLVMC,
Type::FloatTy));
+LLVMC = castConstantFP(ConstantExpr::getFPTrunc(LLVMC,
Type::FloatTy));
VT = MVT::f32;
Extend = true;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.424 - 1.425
---
Log message:
Clean up some bad code.
---
Diffs of the changes: (+3 -5)
LegalizeDAG.cpp |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.424
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.425
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.424 Sun Dec 10 20:23:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 00:25:26 2006
@@ -4567,12 +4567,10 @@
Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
}
-MVT::ValueType NVT = Node-getValueType(0);
// f32 / f64 must be expanded to i32 / i64.
-if (NVT == MVT::f32 || NVT == MVT::f64) {
- Lo = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToTransformTo(NVT),
- Node-getOperand(0));
- Hi = DAG.getConstant(0, TLI.getTypeToTransformTo(NVT));
+if (VT == MVT::f32 || VT == MVT::f64) {
+ Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
+ Hi = DAG.getConstant(0, NVT);
break;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.425 - 1.426
---
Log message:
f32 / f64 node is expanded to one i32 / i64 node.
---
Diffs of the changes: (+12 -5)
LegalizeDAG.cpp | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.425
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.426
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.425 Mon Dec 11 00:25:26 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 11 00:50:04 2006
@@ -1547,7 +1547,10 @@
if (Tmp2.getValueType() != MVT::Vector) {
SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
- Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
+ if (Hi.Val)
+Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3,
Hi,Tmp3);
+ else
+Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
Result = LegalizeOp(Result);
} else {
SDNode *InVal = Tmp2.Val;
@@ -1609,8 +1612,10 @@
ExpandOp(Node-getOperand(i), Lo, Hi);
NewValues.push_back(Lo);
NewValues.push_back(Node-getOperand(i+1));
- NewValues.push_back(Hi);
- NewValues.push_back(Node-getOperand(i+1));
+ if (Hi.Val) {
+NewValues.push_back(Hi);
+NewValues.push_back(Node-getOperand(i+1));
+ }
break;
}
case Promote:
@@ -4570,7 +4575,7 @@
// f32 / f64 must be expanded to i32 / i64.
if (VT == MVT::f32 || VT == MVT::f64) {
Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node-getOperand(0));
- Hi = DAG.getConstant(0, NVT);
+ Hi = SDOperand();
break;
}
@@ -4873,7 +4878,9 @@
// is a type that requires multi-step expansion.
if (getTypeAction(NVT) != Expand NVT != MVT::isVoid) {
Lo = LegalizeOp(Lo);
-Hi = LegalizeOp(Hi);
+if (Hi.Val)
+ // Don't legalize the high part if it is expanded to a single node.
+ Hi = LegalizeOp(Hi);
}
// Remember in a map if the values will be reused later.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.422 - 1.423
SelectionDAGISel.cpp updated: 1.325 - 1.326
TargetLowering.cpp updated: 1.81 - 1.82
---
Log message:
Preliminary soft float support.
---
Diffs of the changes: (+74 -19)
LegalizeDAG.cpp | 35 +++
SelectionDAGISel.cpp | 15 ---
TargetLowering.cpp | 43 +++
3 files changed, 74 insertions(+), 19 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.422
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.423
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.422 Thu Dec 7 14:04:42 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 8 20:42:38 2006
@@ -4351,9 +4351,8 @@
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
SDNode *Node = Op.Val;
assert(getTypeAction(VT) == Expand Not an expanded type!);
- assert((MVT::isInteger(VT) || VT == MVT::Vector)
- Cannot expand FP values!);
- assert(((MVT::isInteger(NVT) NVT VT) || VT == MVT::Vector)
+ assert(((MVT::isInteger(NVT) NVT VT) || MVT::isFloatingPoint(VT) ||
+ VT == MVT::Vector)
Cannot expand to FP value or to larger int value!);
// See if we already expanded it.
@@ -4583,9 +4582,18 @@
Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
}
+MVT::ValueType NVT = Node-getValueType(0);
+// f32 / f64 must be expanded to i32 / i64.
+if (NVT == MVT::f32 || NVT == MVT::f64) {
+ Lo = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToTransformTo(NVT),
+ Node-getOperand(0));
+ Hi = DAG.getConstant(0, TLI.getTypeToTransformTo(NVT));
+ break;
+}
+
// Turn this into a load/store pair by default.
if (Tmp.Val == 0)
- Tmp = ExpandBIT_CONVERT(Node-getValueType(0), Node-getOperand(0));
+ Tmp = ExpandBIT_CONVERT(NVT, Node-getOperand(0));
ExpandOp(Tmp, Lo, Hi);
break;
@@ -4858,6 +4866,25 @@
case ISD::UDIV: Lo = ExpandLibCall(__udivdi3, Node, Hi); break;
case ISD::SREM: Lo = ExpandLibCall(__moddi3 , Node, Hi); break;
case ISD::UREM: Lo = ExpandLibCall(__umoddi3, Node, Hi); break;
+
+ case ISD::FADD:
+Lo = ExpandLibCall(((VT == MVT::f32) ? __addsf3 : __adddf3), Node, Hi);
+break;
+ case ISD::FSUB:
+Lo = ExpandLibCall(((VT == MVT::f32) ? __subsf3 : __subdf3), Node, Hi);
+break;
+ case ISD::FMUL:
+Lo = ExpandLibCall(((VT == MVT::f32) ? __mulsf3 : __muldf3), Node, Hi);
+break;
+ case ISD::FDIV:
+Lo = ExpandLibCall(((VT == MVT::f32) ? __divsf3 : __divdf3), Node, Hi);
+break;
+ case ISD::FP_EXTEND:
+Lo = ExpandLibCall(__extendsfdf2, Node, Hi);
+break;
+ case ISD::FP_ROUND:
+Lo = ExpandLibCall(__truncdfsf2, Node, Hi);
+break;
}
// Make sure the resultant values have been legalized themselves, unless this
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.325
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.326
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.325Thu Dec 7
14:04:42 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Dec 8 20:42:38 2006
@@ -2954,7 +2954,10 @@
// integers it is.
MVT::ValueType NVT = getTypeToTransformTo(VT);
unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
-if (NumVals == 2) {
+if (NumVals == 1) {
+ SDOperand Tmp = SDOperand(Result, i++);
+ Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp));
+} else if (NumVals == 2) {
SDOperand Lo = SDOperand(Result, i++);
SDOperand Hi = SDOperand(Result, i++);
@@ -3040,7 +3043,10 @@
// integers it is.
MVT::ValueType NVT = getTypeToTransformTo(VT);
unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
-if (NumVals == 2) {
+if (NumVals == 1) {
+ Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, VT, Op));
+ Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
+} else if (NumVals == 2) {
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
DAG.getConstant(0, getPointerTy()));
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
@@ -3166,7 +3172,10 @@
ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
} else {
assert(MVT::isFloatingPoint(VT));
- ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
+ if (getTypeAction(VT) == Expand)
+ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
+ else
+ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
}
}
} else if (RetTys.size() == 3) {
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.420 - 1.421
---
Log message:
Avoid inifinite looping if READCYCLECOUNTER isn't custom lowered.
---
Diffs of the changes: (+8 -3)
LegalizeDAG.cpp | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.420
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.421
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.420 Wed Nov 29 02:26:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Nov 29 13:13:47 2006
@@ -1850,16 +1850,21 @@
switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
Node-getValueType(0))) {
default: assert(0 This action is not supported yet!);
-case TargetLowering::Legal: break;
+case TargetLowering::Legal:
+ Tmp1 = Result.getValue(0);
+ Tmp2 = Result.getValue(1);
+ break;
case TargetLowering::Custom:
Result = TLI.LowerOperation(Result, DAG);
+ Tmp1 = LegalizeOp(Result.getValue(0));
+ Tmp2 = LegalizeOp(Result.getValue(1));
break;
}
// Since rdcc produce two values, make sure to remember that we legalized
// both of them.
-AddLegalizedOperand(SDOperand(Node, 0), LegalizeOp(Result.getValue(0)));
-AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Result.getValue(1)));
+AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
+AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
return Result;
case ISD::SELECT:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.418 - 1.419
---
Log message:
Fix PR1016: http://llvm.org/PR1016
---
Diffs of the changes: (+4 -5)
LegalizeDAG.cpp |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.418
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.419
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.418 Sun Nov 26 22:39:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 27 19:03:30 2006
@@ -1862,6 +1862,10 @@
break;
case Promote:
Tmp1 = PromoteOp(Node-getOperand(0)); // Promote the condition.
+ // Make sure the condition is either zero or one.
+ if (!TLI.MaskedValueIsZero(Tmp1,
+ MVT::getIntVTBitMask(Tmp1.getValueType())^1))
+Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
break;
}
Tmp2 = LegalizeOp(Node-getOperand(1)); // TrueVal
@@ -1883,11 +1887,6 @@
Tmp2, Tmp3,
castCondCodeSDNode(Tmp1.getOperand(2))-get());
} else {
-// Make sure the condition is either zero or one. It may have been
-// promoted from something else.
-unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
-if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL (64-NumBits))^1))
- Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
Result = DAG.getSelectCC(Tmp1,
DAG.getConstant(0, Tmp1.getValueType()),
Tmp2, Tmp3, ISD::SETNE);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.417 - 1.418
---
Log message:
If a brcond condition is promoted, make sure to zero extend it, even if not
expanded into BR_CC.
---
Diffs of the changes: (+6 -6)
LegalizeDAG.cpp | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.417
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.418
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.417 Mon Nov 6 22:11:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Nov 26 22:39:56 2006
@@ -1302,6 +1302,12 @@
break;
case Promote:
Tmp2 = PromoteOp(Node-getOperand(1)); // Promote the condition.
+
+ // The top bits of the promoted condition are not necessarily zero,
ensure
+ // that the value is properly zero extended.
+ if (!TLI.MaskedValueIsZero(Tmp2,
+ MVT::getIntVTBitMask(Tmp2.getValueType())^1))
+Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
break;
}
@@ -1323,12 +1329,6 @@
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node-getOperand(2));
} else {
-// Make sure the condition is either zero or one. It may have been
-// promoted from something else.
-unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
-if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL (64-NumBits))^1))
- Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
-
Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.416 - 1.417
---
Log message:
Fix PR988: http://llvm.org/PR988 and
CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll.
The low part goes in the first operand of expandop, not the second one.
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.416
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.417
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.416 Thu Nov 2 14:25:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 6 22:11:44 2006
@@ -2039,7 +2039,7 @@
case Expand: {
// Length is too big, just take the lo-part of the length.
SDOperand HiPart;
- ExpandOp(Node-getOperand(3), HiPart, Tmp4);
+ ExpandOp(Node-getOperand(3), Tmp4, HiPart);
break;
}
case Legal:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.413 - 1.414
SelectionDAGISel.cpp updated: 1.307 - 1.308
---
Log message:
Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the
target custom lower it.
---
Diffs of the changes: (+55 -28)
LegalizeDAG.cpp | 48
SelectionDAGISel.cpp | 35 +++
2 files changed, 55 insertions(+), 28 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.413
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.414
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.413 Fri Oct 20 02:07:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Oct 30 02:00:44 2006
@@ -16,6 +16,7 @@
#include llvm/CodeGen/MachineFrameInfo.h
#include llvm/Target/TargetLowering.h
#include llvm/Target/TargetData.h
+#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
#include llvm/CallingConv.h
#include llvm/Constants.h
@@ -1240,6 +1241,53 @@
}
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
break;
+ case ISD::BR_JT:
+Tmp1 = LegalizeOp(Node-getOperand(0)); // Legalize the chain.
+// Ensure that libcalls are emitted before a branch.
+Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+Tmp1 = LegalizeOp(Tmp1);
+LastCALLSEQ_END = DAG.getEntryNode();
+
+Tmp2 = LegalizeOp(Node-getOperand(1)); // Legalize the jumptable node.
+Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node-getOperand(2));
+
+switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
+default: assert(0 This action is not supported yet!);
+case TargetLowering::Legal: break;
+case TargetLowering::Custom:
+ Tmp1 = TLI.LowerOperation(Result, DAG);
+ if (Tmp1.Val) Result = Tmp1;
+ break;
+case TargetLowering::Expand: {
+ SDOperand Chain = Result.getOperand(0);
+ SDOperand Table = Result.getOperand(1);
+ SDOperand Index = Result.getOperand(2);
+
+ MVT::ValueType PTy = TLI.getPointerTy();
+ bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
+ // PIC jump table entries are 32-bit values.
+ unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
+ Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize,
PTy));
+ SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
+ SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
+ if (isPIC) {
+// For PIC, the sequence is:
+// BRIND(load(Jumptable + index) + RelocBase)
+// RelocBase is the JumpTable on PPC and X86, GOT on Alpha
+SDOperand Reloc;
+if (TLI.usesGlobalOffsetTable())
+ Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
+else
+ Reloc = Table;
+Addr= (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) :
Addr;
+Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
+Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
+ } else {
+Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
+ }
+}
+}
+break;
case ISD::BRCOND:
Tmp1 = LegalizeOp(Node-getOperand(0)); // Legalize the chain.
// Ensure that libcalls are emitted before a return.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.307
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.308
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.307Sun Oct 29
15:01:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Oct 30 02:00:44 2006
@@ -1070,33 +1070,11 @@
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable JT) {
// Emit the code for the jump table
MVT::ValueType PTy = TLI.getPointerTy();
- assert((PTy == MVT::i32 || PTy == MVT::i64)
- Jump table entries are 32-bit values);
- bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
- // PIC jump table entries are 32-bit values.
- unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
- SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
- SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
- DAG.getConstant(EntrySize, PTy));
- SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy);
- SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB);
- SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD,
- NULL, 0);
- if (isPIC) {
-// For Pic, the sequence is:
-// BRIND(load(Jumptable + index) + RelocBase)
-// RelocBase is the JumpTable on PPC and X86, GOT on Alpha
-SDOperand Reloc;
-if (TLI.usesGlobalOffsetTable())
- Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
-else
- Reloc = TAB;
-ADD = (PTy !=
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.414 - 1.415
---
Log message:
Fix a typo which can break jumptables.
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.414
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.415
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.414 Mon Oct 30 02:00:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Oct 30 20:31:00 2006
@@ -1279,7 +1279,7 @@
Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
else
Reloc = Table;
-Addr= (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) :
Addr;
+Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
} else {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.412 - 1.413
SelectionDAGISel.cpp updated: 1.290 - 1.291
---
Log message:
For PR950: http://llvm.org/PR950 :
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
---
Diffs of the changes: (+39 -37)
LegalizeDAG.cpp |6 ++--
SelectionDAGISel.cpp | 70 ++-
2 files changed, 39 insertions(+), 37 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.412
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.413
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.412 Fri Oct 13 16:12:22 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 20 02:07:24 2006
@@ -3562,7 +3562,7 @@
CV.push_back(ConstantFP::get(OpNTy, V-getValue()));
} else if (ConstantSDNode *V =
dyn_castConstantSDNode(Node-getOperand(i))) {
-CV.push_back(ConstantUInt::get(OpNTy, V-getValue()));
+CV.push_back(ConstantInt::get(OpNTy, V-getValue()));
} else {
assert(Node-getOperand(i).getOpcode() == ISD::UNDEF);
CV.push_back(UndefValue::get(OpNTy));
@@ -3915,7 +3915,7 @@
SignSet, Four, Zero);
uint64_t FF = 0x5f80ULL;
if (TLI.isLittleEndian()) FF = 32;
-static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
+static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
@@ -4046,7 +4046,7 @@
case MVT::i64: FF = 0x5F80ULL; break; // 2^64 (as a float)
}
if (TLI.isLittleEndian()) FF = 32;
- static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
+ static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.290
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.291
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.290Thu Oct 19
16:46:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Oct 20 02:07:24 2006
@@ -236,21 +236,22 @@
Function::iterator BB = Fn.begin(), EB = Fn.end();
for (BasicBlock::iterator I = BB-begin(), E = BB-end(); I != E; ++I)
if (AllocaInst *AI = dyn_castAllocaInst(I))
- if (ConstantUInt *CUI = dyn_castConstantUInt(AI-getArraySize())) {
+ if (ConstantInt *CUI = dyn_castConstantInt(AI-getArraySize())) {
const Type *Ty = AI-getAllocatedType();
uint64_t TySize = TLI.getTargetData()-getTypeSize(Ty);
unsigned Align =
std::max((unsigned)TLI.getTargetData()-getTypeAlignment(Ty),
AI-getAlignment());
-// If the alignment of the value is smaller than the size of the value,
-// and if the size of the value is particularly small (= 8 bytes),
-// round up to the size of the value for potentially better
performance.
+// If the alignment of the value is smaller than the size of the
+// value, and if the size of the value is particularly small
+// (= 8 bytes), round up to the size of the value for potentially
+// better performance.
//
// FIXME: This could be made better with a preferred alignment hook in
// TargetData. It serves primarily to 8-byte align doubles for X86.
if (Align TySize TySize = 8) Align = TySize;
-TySize *= CUI-getValue(); // Get total allocated size.
+TySize *= CUI-getZExtValue(); // Get total allocated size.
if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
StaticAllocaMap[AI] =
MF.getFrameInfo()-CreateStackObject((unsigned)TySize, Align);
@@ -393,11 +394,13 @@
/// The comparison function for sorting Case values.
struct CaseCmp {
bool operator () (const Case C1, const Case C2) {
- if (const ConstantUInt* U1 = dyn_castconst ConstantUInt(C1.first))
-return U1-getValue() castconst ConstantUInt(C2.first)-getValue();
+ if (const ConstantInt* I1 = dyn_castconst ConstantInt(C1.first))
+if (I1-getType()-isUnsigned())
+ return I1-getZExtValue()
+castconst ConstantInt(C2.first)-getZExtValue();
- const ConstantSInt* S1 = dyn_castconst ConstantSInt(C1.first);
- return S1-getValue() castconst ConstantSInt(C2.first)-getValue();
+ return castconst ConstantInt(C1.first)-getSExtValue()
+ castconst
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.410 - 1.411
---
Log message:
Typo
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.410
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.411
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.410 Wed Oct 11 02:09:31 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Oct 11 12:52:19 2006
@@ -2851,7 +2851,7 @@
Result = DAG.getNode(ISD::SRA, Node-getValueType(0),
Result, ShiftCst);
} else if (Node-getOpcode() == ISD::FP_ROUND_INREG) {
-// The only way we can lower this is to turn it into a STORETRUNC,
+// The only way we can lower this is to turn it into a TRUNCSTORE,
// EXTLOAD pair, targetting a temporary location (a stack slot).
// NOTE: there is a choice here between constantly creating new stack
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.406 - 1.407
---
Log message:
Fix a bug introduced by my LOAD/LOADX changes.
---
Diffs of the changes: (+4 -2)
LegalizeDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.406
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.407
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.406 Mon Oct 9 15:57:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 10 02:51:21 2006
@@ -2433,7 +2433,6 @@
// This defaults to loading a pointer from the input and storing it to
the
// output, returning the chain.
SrcValueSDNode *SVD = castSrcValueSDNode(Node-getOperand(3));
- SrcValueSDNode *SVS = castSrcValueSDNode(Node-getOperand(4));
Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD-getValue(),
SVD-getOffset());
Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, Node-getOperand(4));
@@ -3234,7 +3233,10 @@
case ISD::LOAD: {
LoadSDNode *LD = castLoadSDNode(Node);
-Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, LD-getChain(),
LD-getBasePtr(),
+ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
+ ? ISD::EXTLOAD : LD-getExtensionType();
+Result = DAG.getExtLoad(ExtType, NVT,
+LD-getChain(), LD-getBasePtr(),
LD-getSrcValue(), LD-getSrcValueOffset(), VT);
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.407 - 1.408 --- Log message: Fix another bug in extload promotion. --- Diffs of the changes: (+2 -1) LegalizeDAG.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.407 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.408 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.407 Tue Oct 10 02:51:21 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 10 13:54:19 2006 @@ -3237,7 +3237,8 @@ ? ISD::EXTLOAD : LD-getExtensionType(); Result = DAG.getExtLoad(ExtType, NVT, LD-getChain(), LD-getBasePtr(), -LD-getSrcValue(), LD-getSrcValueOffset(), VT); +LD-getSrcValue(), LD-getSrcValueOffset(), +LD-getLoadVT()); // Remember that we legalized the chain. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.403 - 1.404
---
Log message:
Fix a miscompilation of:
long long foo(long long X) {
return (long long)(signed char)(int)X;
}
Instead of:
_foo:
extsb r2, r4
srawi r3, r4, 31
mr r4, r2
blr
we now produce:
_foo:
extsb r4, r4
srawi r3, r4, 31
blr
This fixes a miscompilation in ConstantFolding.cpp.
---
Diffs of the changes: (+5 -3)
LegalizeDAG.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.403
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.403 Thu Oct 5 17:57:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 6 12:34:12 2006
@@ -4349,12 +4349,14 @@
case ISD::SIGN_EXTEND_INREG:
ExpandOp(Node-getOperand(0), Lo, Hi);
-// Sign extend the lo-part.
+// sext_inreg the low part if needed.
+Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node-getOperand(1));
+
+// The high part gets the sign extension from the lo-part. This handles
+// things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, NVT, Lo,
DAG.getConstant(MVT::getSizeInBits(NVT)-1,
TLI.getShiftAmountTy()));
-// sext_inreg the low part if needed.
-Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node-getOperand(1));
break;
case ISD::BSWAP: {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.404 - 1.405 --- Log message: Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom part was always forced to be sextload, even when we needed an zextload. --- Diffs of the changes: (+2 -3) LegalizeDAG.cpp |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.405 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404 Fri Oct 6 12:34:12 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 6 19:58:36 2006 @@ -4474,13 +4474,12 @@ SDOperand Chain = Node-getOperand(0); SDOperand Ptr = Node-getOperand(1); MVT::ValueType EVT = castVTSDNode(Node-getOperand(3))-getVT(); -unsigned LType = Node-getConstantOperandVal(4); +ISD::LoadExtType LType = (ISD::LoadExtType)Node-getConstantOperandVal(4); if (EVT == NVT) Lo = DAG.getLoad(NVT, Chain, Ptr, Node-getOperand(2)); else - Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node-getOperand(2), - EVT); + Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node-getOperand(2), EVT); // Remember that we legalized the chain. AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.400 - 1.401
---
Log message:
Fix an obvious typo.
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.400
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.401
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.400 Sun Sep 24 14:44:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 3 18:08:27 2006
@@ -1398,7 +1398,7 @@
Tmp2 = Result.getValue(1);
if (isCustom) {
-Tmp3 = TLI.LowerOperation(Tmp3, DAG);
+Tmp3 = TLI.LowerOperation(Result, DAG);
if (Tmp3.Val) {
Tmp1 = LegalizeOp(Tmp3);
Tmp2 = LegalizeOp(Tmp3.getValue(1));
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.399 - 1.400
SelectionDAGISel.cpp updated: 1.278 - 1.279
---
Log message:
Add support for other relocation bases to jump tables, as well as custom asm
directives
---
Diffs of the changes: (+13 -1)
LegalizeDAG.cpp | 11 +++
SelectionDAGISel.cpp |3 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.399
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.400
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.399 Tue Sep 19 22:38:48 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Sep 24 14:44:59 2006
@@ -558,6 +558,17 @@
#endif
assert(0 Do not know how to legalize this operator!);
abort();
+ case ISD::JumpTableRelocBase:
+switch (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0))) {
+case TargetLowering::Custom:
+ Tmp1 = TLI.LowerOperation(Op, DAG);
+ if (Tmp1.Val) Result = Tmp1;
+ break;
+default:
+ Result = LegalizeOp(Node-getOperand(0));
+ break;
+}
+break;
case ISD::GlobalAddress:
case ISD::ExternalSymbol:
case ISD::ConstantPool:
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.278
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.279
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.278Sun Sep 24
00:22:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Sep 24 14:44:59 2006
@@ -868,8 +868,9 @@
SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD,
DAG.getSrcValue(0));
if (isPIC) {
+SDOperand Reloc = DAG.getNode(ISD::JumpTableRelocBase, PTy, TAB);
ADD = DAG.getNode(ISD::ADD, PTy,
-((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD),
TAB);
+((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD),
Reloc);
DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));
} else {
DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.398 - 1.399
---
Log message:
Expand 64-bit shifts more optimally if we know that the high bit of the
shift amount is one or zero. For example, for:
long long foo1(long long X, int C) {
return X (C|32);
}
long long foo2(long long X, int C) {
return X (C~32);
}
we get:
_foo1:
movb $31, %cl
movl 4(%esp), %edx
andb 12(%esp), %cl
shll %cl, %edx
xorl %eax, %eax
ret
_foo2:
movb $223, %cl
movl 4(%esp), %eax
movl 8(%esp), %edx
andb 12(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
ret
instead of:
_foo1:
subl $4, %esp
movl %ebx, (%esp)
movb $32, %bl
movl 8(%esp), %eax
movl 12(%esp), %edx
movb %bl, %cl
orb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
_foo2:
subl $4, %esp
movl %ebx, (%esp)
movb $223, %cl
movl 8(%esp), %eax
movl 12(%esp), %edx
andb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
xorb %bl, %bl
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
---
Diffs of the changes: (+66 -0)
LegalizeDAG.cpp | 66
1 files changed, 66 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.398
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.399
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.398 Mon Sep 18 18:28:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep 19 22:38:48 2006
@@ -3781,6 +3781,72 @@
return true;
}
}
+
+ // Okay, the shift amount isn't constant. However, if we can tell that it is
+ // = 32 or 32, we can still simplify it, without knowing the actual value.
+ uint64_t Mask = NVTBits, KnownZero, KnownOne;
+ TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
+
+ // If we know that the high bit of the shift amount is one, then we can do
+ // this as a couple of simple shifts.
+ if (KnownOne Mask) {
+// Mask out the high bit, which we know is set.
+Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
+ DAG.getConstant(NVTBits-1, Amt.getValueType()));
+
+// Expand the incoming operand to be shifted, so that we have its parts
+SDOperand InL, InH;
+ExpandOp(Op, InL, InH);
+switch(Opc) {
+case ISD::SHL:
+ Lo = DAG.getConstant(0, NVT); // Low part is zero.
+ Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
+ return true;
+case ISD::SRL:
+ Hi = DAG.getConstant(0, NVT); // Hi part is zero.
+ Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
+ return true;
+case ISD::SRA:
+ Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
+ DAG.getConstant(NVTBits-1, Amt.getValueType()));
+ Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
+ return true;
+}
+ }
+
+ // If we know that the high bit of the shift amount is zero, then we can do
+ // this as a couple of simple shifts.
+ if (KnownZero Mask) {
+// Compute 32-amt.
+SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
+ DAG.getConstant(NVTBits, Amt.getValueType()),
+ Amt);
+
+// Expand the incoming operand to be shifted, so that we have its parts
+SDOperand InL, InH;
+ExpandOp(Op, InL, InH);
+switch(Opc) {
+case ISD::SHL:
+ Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
+ Hi = DAG.getNode(ISD::OR, NVT,
+ DAG.getNode(ISD::SHL, NVT, InH, Amt),
+ DAG.getNode(ISD::SRL, NVT, InL, Amt2));
+ return true;
+case ISD::SRL:
+ Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
+ Lo = DAG.getNode(ISD::OR, NVT,
+ DAG.getNode(ISD::SRL, NVT, InL, Amt),
+ DAG.getNode(ISD::SHL, NVT, InH, Amt2));
+ return true;
+case ISD::SRA:
+ Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
+ Lo = DAG.getNode(ISD::OR, NVT,
+ DAG.getNode(ISD::SRL, NVT, InL, Amt),
+ DAG.getNode(ISD::SHL, NVT, InH, Amt2));
+ return true;
+}
+ }
+
return false;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.396 - 1.397
---
Log message:
Allow i32 UDIV, SDIV, UREM, SREM to be expanded into libcalls.
---
Diffs of the changes: (+30 -6)
LegalizeDAG.cpp | 36 ++--
1 files changed, 30 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.396
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.397
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.396 Sat Sep 16 00:08:34 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Sep 18 16:49:04 2006
@@ -2148,6 +2148,19 @@
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Expand: {
+ if (Node-getValueType(0) == MVT::i32) {
+switch (Node-getOpcode()) {
+default: assert(0 Do not know how to expand this integer BinOp!);
+case ISD::UDIV:
+case ISD::SDIV:
+ const char *FnName = Node-getOpcode() == ISD::UDIV
+? __udivsi3 : __divsi3;
+ SDOperand Dummy;
+ Result = ExpandLibCall(FnName, Node, Dummy);
+};
+break;
+ }
+
assert(MVT::isVector(Node-getValueType(0))
Cannot expand this binary operator!);
// Expand the operation into a bunch of nasty scalar code.
@@ -2318,13 +2331,24 @@
}
break;
case TargetLowering::Expand:
+ unsigned DivOpc= (Node-getOpcode() == ISD::UREM) ? ISD::UDIV :
ISD::SREM;
if (MVT::isInteger(Node-getValueType(0))) {
-// X % Y - X-X/Y*Y
-MVT::ValueType VT = Node-getValueType(0);
-unsigned Opc = Node-getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
-Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
-Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
-Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
+if (TLI.getOperationAction(DivOpc, Node-getValueType(0)) ==
+TargetLowering::Legal) {
+ // X % Y - X-X/Y*Y
+ MVT::ValueType VT = Node-getValueType(0);
+ unsigned Opc = Node-getOpcode() == ISD::UREM ? ISD::UDIV :
ISD::SDIV;
+ Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
+ Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
+ Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
+} else {
+ assert(Node-getValueType(0) == MVT::i32
+ Cannot expand this binary operator!);
+ const char *FnName = Node-getOpcode() == ISD::UREM
+? __umodsi3 : __modsi3;
+ SDOperand Dummy;
+ Result = ExpandLibCall(FnName, Node, Dummy);
+}
} else {
// Floating point mod - fmod libcall.
const char *FnName = Node-getValueType(0) == MVT::f32 ?
fmodf:fmod;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.397 - 1.398
---
Log message:
Fix a typo.
---
Diffs of the changes: (+2 -3)
LegalizeDAG.cpp |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.397
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.398
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.397 Mon Sep 18 16:49:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Sep 18 18:28:33 2006
@@ -2331,14 +2331,13 @@
}
break;
case TargetLowering::Expand:
- unsigned DivOpc= (Node-getOpcode() == ISD::UREM) ? ISD::UDIV :
ISD::SREM;
+ unsigned DivOpc= (Node-getOpcode() == ISD::UREM) ? ISD::UDIV :
ISD::SDIV;
if (MVT::isInteger(Node-getValueType(0))) {
if (TLI.getOperationAction(DivOpc, Node-getValueType(0)) ==
TargetLowering::Legal) {
// X % Y - X-X/Y*Y
MVT::ValueType VT = Node-getValueType(0);
- unsigned Opc = Node-getOpcode() == ISD::UREM ? ISD::UDIV :
ISD::SDIV;
- Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
+ Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
} else {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.393 - 1.394
---
Log message:
Allow custom expand of mul
---
Diffs of the changes: (+9 -0)
LegalizeDAG.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.393
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.394
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.393 Tue Sep 12 22:50:39 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Sep 15 19:09:24 2006
@@ -4693,6 +4693,15 @@
break;
}
case ISD::MUL: {
+// If the target wants to custom expand this, let them.
+if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
+ Op = TLI.LowerOperation(Op, DAG);
+ if (Op.Val) {
+ExpandOp(Op, Lo, Hi);
+break;
+ }
+}
+
bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
bool UseLibCall = true;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.394 - 1.395
---
Log message:
simplify control flow, no functionality change
---
Diffs of the changes: (+12 -6)
LegalizeDAG.cpp | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.394
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.395
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.394 Fri Sep 15 19:09:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Sep 15 19:21:44 2006
@@ -4723,22 +4723,28 @@
LH.getOpcode() == ISD::SRA LH.getOperand(0) == LL
LH.getOperand(1).getOpcode() == ISD::Constant
castConstantSDNode(LH.getOperand(1))-getValue() == SH) {
+// FIXME: Move this to the dag combiner.
+
+// Low part:
+Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
+// High part:
Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
-UseLibCall = false;
+break;
} else if (HasMULHU) {
+// Low part:
+Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
+
+// High part:
Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
-UseLibCall = false;
+break;
}
- if (!UseLibCall)
-Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
}
-if (UseLibCall)
- Lo = ExpandLibCall(__muldi3 , Node, Hi);
+Lo = ExpandLibCall(__muldi3 , Node, Hi);
break;
}
case ISD::SDIV: Lo = ExpandLibCall(__divdi3 , Node, Hi); break;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.395 - 1.396
---
Log message:
Oh yeah, this is needed too
---
Diffs of the changes: (+3 -3)
LegalizeDAG.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.395
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.396
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.395 Fri Sep 15 19:21:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Sep 16 00:08:34 2006
@@ -4695,9 +4695,9 @@
case ISD::MUL: {
// If the target wants to custom expand this, let them.
if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
- Op = TLI.LowerOperation(Op, DAG);
- if (Op.Val) {
-ExpandOp(Op, Lo, Hi);
+ SDOperand New = TLI.LowerOperation(Op, DAG);
+ if (New.Val) {
+ExpandOp(New, Lo, Hi);
break;
}
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.391 - 1.392
SelectionDAG.cpp updated: 1.336 - 1.337
SelectionDAGISel.cpp updated: 1.273 - 1.274
---
Log message:
Implement the fpowi now by lowering to a libcall
---
Diffs of the changes: (+16 -1)
LegalizeDAG.cpp |9 -
SelectionDAG.cpp |1 +
SelectionDAGISel.cpp |7 +++
3 files changed, 16 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.391
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.392
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.391 Fri Sep 8 19:20:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Sep 9 01:03:30 2006
@@ -2581,7 +2581,14 @@
break;
}
break;
-
+ case ISD::FPOWI: {
+// We always lower FPOWI into a libcall. No target support it yet.
+const char *FnName = Node-getValueType(0) == MVT::f32
+? __powisf2 : __powidf2;
+SDOperand Dummy;
+Result = ExpandLibCall(FnName, Node, Dummy);
+break;
+ }
case ISD::BIT_CONVERT:
if (!isTypeLegal(Node-getOperand(0).getValueType())) {
Result = ExpandBIT_CONVERT(Node-getValueType(0), Node-getOperand(0));
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.336
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.337
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.336Tue Aug 29
01:42:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Sep 9 01:03:30 2006
@@ -2404,6 +2404,7 @@
case ISD::FSQRT: return fsqrt;
case ISD::FSIN: return fsin;
case ISD::FCOS: return fcos;
+ case ISD::FPOWI: return fpowi;
// Binary operators
case ISD::ADD:return add;
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.273
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.274
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.273Wed Sep 6
20:59:34 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Sep 9 01:03:30 2006
@@ -1620,6 +1620,13 @@
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1;
return 0;
+ case Intrinsic::powi_f32:
+ case Intrinsic::powi_f64:
+setValue(I, DAG.getNode(ISD::FPOWI,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1)),
+ getValue(I.getOperand(2;
+return 0;
case Intrinsic::pcmarker: {
SDOperand Tmp = getValue(I.getOperand(1));
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.390 - 1.391
---
Log message:
Allow targets to custom lower expanded BIT_CONVERT's
---
Diffs of the changes: (+15 -2)
LegalizeDAG.cpp | 17 +++--
1 files changed, 15 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.390
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.391
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.390 Fri Sep 1 13:17:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Sep 8 19:20:27 2006
@@ -4457,8 +4457,21 @@
break;
case ISD::BIT_CONVERT: {
-SDOperand Tmp = ExpandBIT_CONVERT(Node-getValueType(0),
- Node-getOperand(0));
+SDOperand Tmp;
+if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) ==
TargetLowering::Custom){
+ // If the target wants to, allow it to lower this itself.
+ switch (getTypeAction(Node-getOperand(0).getValueType())) {
+ case Expand: assert(0 cannot expand FP!);
+ case Legal: Tmp = LegalizeOp(Node-getOperand(0)); break;
+ case Promote: Tmp = PromoteOp (Node-getOperand(0)); break;
+ }
+ Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
+}
+
+// Turn this into a load/store pair by default.
+if (Tmp.Val == 0)
+ Tmp = ExpandBIT_CONVERT(Node-getValueType(0), Node-getOperand(0));
+
ExpandOp(Tmp, Lo, Hi);
break;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.387 - 1.388
---
Log message:
Fix PR861: http://llvm.org/PR861
---
Diffs of the changes: (+1 -0)
LegalizeDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.387
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.388
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.387 Mon Aug 14 18:53:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Aug 21 15:24:53 2006
@@ -1502,6 +1502,7 @@
SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
+ Result = LegalizeOp(Result);
} else {
SDNode *InVal = Tmp2.Val;
unsigned NumElems =
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.384 - 1.385
SelectionDAG.cpp updated: 1.319 - 1.320
---
Log message:
Eliminate some malloc traffic by allocating vectors on the stack. Change some
method that took std::vectorSDOperand to take a pointer to a first operand
and #operands.
This speeds up isel on kc++ by about 3%.
---
Diffs of the changes: (+67 -82)
LegalizeDAG.cpp | 44 ---
SelectionDAG.cpp | 105 +++
2 files changed, 67 insertions(+), 82 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.384
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.385
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.384 Fri Aug 4 12:45:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Aug 7 20:09:31 2006
@@ -22,6 +22,7 @@
#include llvm/Support/MathExtras.h
#include llvm/Support/CommandLine.h
#include llvm/Support/Visibility.h
+#include llvm/ADT/SmallVector.h
#include iostream
#include map
using namespace llvm;
@@ -541,11 +542,11 @@
if (Node-getOpcode() = ISD::BUILTIN_OP_END) {
// If this is a target node, legalize it by legalizing the operands then
// passing it through.
- std::vectorSDOperand Ops;
+ SmallVectorSDOperand, 8 Ops;
for (unsigned i = 0, e = Node-getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node-getOperand(i)));
- Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops);
+ Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops[0], Ops.size());
for (unsigned i = 0, e = Node-getNumValues(); i != e; ++i)
AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
@@ -621,10 +622,10 @@
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_WO_CHAIN:
case ISD::INTRINSIC_VOID: {
-std::vectorSDOperand Ops;
+SmallVectorSDOperand, 8 Ops;
for (unsigned i = 0, e = Node-getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node-getOperand(i)));
-Result = DAG.UpdateNodeOperands(Result, Ops);
+Result = DAG.UpdateNodeOperands(Result, Ops[0], Ops.size());
// Allow the target to custom lower its intrinsics if it wants to.
if (TLI.getOperationAction(Node-getOpcode(), MVT::Other) ==
@@ -690,7 +691,7 @@
case TargetLowering::Legal:
if (Tmp1 != Node-getOperand(0) ||
getTypeAction(Node-getOperand(1).getValueType()) == Promote) {
-std::vectorSDOperand Ops;
+SmallVectorSDOperand, 8 Ops;
Ops.push_back(Tmp1);
if (getTypeAction(Node-getOperand(1).getValueType()) == Legal) {
Ops.push_back(Node-getOperand(1)); // line # must be legal.
@@ -702,7 +703,7 @@
}
Ops.push_back(Node-getOperand(3)); // filename must be legal.
Ops.push_back(Node-getOperand(4)); // working dir # must be legal.
-Result = DAG.UpdateNodeOperands(Result, Ops);
+Result = DAG.UpdateNodeOperands(Result, Ops[0], Ops.size());
}
break;
}
@@ -815,11 +816,11 @@
Tmp3 = LegalizeOp(Node-getOperand(2));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
} else {
- std::vectorSDOperand Ops;
+ SmallVectorSDOperand, 8 Ops;
// Legalize the operands.
for (unsigned i = 0, e = Node-getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node-getOperand(i)));
- Result = DAG.UpdateNodeOperands(Result, Ops);
+ Result = DAG.UpdateNodeOperands(Result, Ops[0], Ops.size());
}
break;
@@ -1074,9 +1075,9 @@
// Do not try to legalize the target-specific arguments (#1+).
if (Tmp1 != Node-getOperand(0)) {
- std::vectorSDOperand Ops(Node-op_begin(), Node-op_end());
+ SmallVectorSDOperand, 8 Ops(Node-op_begin(), Node-op_end());
Ops[0] = Tmp1;
- Result = DAG.UpdateNodeOperands(Result, Ops);
+ Result = DAG.UpdateNodeOperands(Result, Ops[0], Ops.size());
}
// Remember that the CALLSEQ_START is legalized.
@@ -1117,18 +1118,18 @@
// an optional flag input.
if (Node-getOperand(Node-getNumOperands()-1).getValueType() !=
MVT::Flag){
if (Tmp1 != Node-getOperand(0)) {
-std::vectorSDOperand Ops(Node-op_begin(), Node-op_end());
+SmallVectorSDOperand, 8 Ops(Node-op_begin(), Node-op_end());
Ops[0] = Tmp1;
-Result = DAG.UpdateNodeOperands(Result, Ops);
+Result = DAG.UpdateNodeOperands(Result, Ops[0], Ops.size());
}
} else {
Tmp2 = LegalizeOp(Node-getOperand(Node-getNumOperands()-1));
if (Tmp1 != Node-getOperand(0) ||
Tmp2 != Node-getOperand(Node-getNumOperands()-1)) {
-std::vectorSDOperand Ops(Node-op_begin(), Node-op_end());
+SmallVectorSDOperand, 8 Ops(Node-op_begin(), Node-op_end());
Ops[0] = Tmp1;
Ops.back() = Tmp2;
-Result =
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.383 - 1.384
SelectionDAG.cpp updated: 1.316 - 1.317
---
Log message:
Make SelectionDAG::RemoveDeadNodes iterative instead of recursive, which
also make it simpler.
---
Diffs of the changes: (+33 -51)
LegalizeDAG.cpp |2 -
SelectionDAG.cpp | 82 +--
2 files changed, 33 insertions(+), 51 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.383
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.384
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.383 Wed Jul 26 18:55:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Aug 4 12:45:20 2006
@@ -349,7 +349,7 @@
PackedNodes.clear();
// Remove dead nodes now.
- DAG.RemoveDeadNodes(OldRoot.Val);
+ DAG.RemoveDeadNodes();
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.316
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.317
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.316Wed Aug 2
17:00:34 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Aug 4 12:45:20 2006
@@ -23,6 +23,7 @@
#include llvm/Target/TargetInstrInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/ADT/SetVector.h
+#include llvm/ADT/SmallVector.h
#include llvm/ADT/StringExtras.h
#include iostream
#include set
@@ -263,69 +264,50 @@
//===--===//
/// RemoveDeadNodes - This method deletes all unreachable nodes in the
-/// SelectionDAG, including nodes (like loads) that have uses of their token
-/// chain but no other uses and no side effect. If a node is passed in as an
-/// argument, it is used as the seed for node deletion.
-void SelectionDAG::RemoveDeadNodes(SDNode *N) {
+/// SelectionDAG.
+void SelectionDAG::RemoveDeadNodes() {
// Create a dummy node (which is not added to allnodes), that adds a
reference
// to the root node, preventing it from being deleted.
HandleSDNode Dummy(getRoot());
- bool MadeChange = false;
+ SmallVectorSDNode*, 128 DeadNodes;
- // If we have a hint to start from, use it.
- if (N N-use_empty()) {
-DestroyDeadNode(N);
-MadeChange = true;
- }
-
+ // Add all obviously-dead nodes to the DeadNodes worklist.
for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I)
-if (I-use_empty() I-getOpcode() != 65535) {
- // Node is dead, recursively delete newly dead uses.
- DestroyDeadNode(I);
- MadeChange = true;
-}
-
- // Walk the nodes list, removing the nodes we've marked as dead.
- if (MadeChange) {
-for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; )
{
- SDNode *N = I++;
- if (N-use_empty())
-AllNodes.erase(N);
+if (I-use_empty())
+ DeadNodes.push_back(I);
+
+ // Process the worklist, deleting the nodes and adding their uses to the
+ // worklist.
+ while (!DeadNodes.empty()) {
+SDNode *N = DeadNodes.back();
+DeadNodes.pop_back();
+
+// Take the node out of the appropriate CSE map.
+RemoveNodeFromCSEMaps(N);
+
+// Next, brutally remove the operand list. This is safe to do, as there
are
+// no cycles in the graph.
+for (SDNode::op_iterator I = N-op_begin(), E = N-op_end(); I != E; ++I) {
+ SDNode *Operand = I-Val;
+ Operand-removeUser(N);
+
+ // Now that we removed this operand, see if there are no uses of it left.
+ if (Operand-use_empty())
+DeadNodes.push_back(Operand);
}
+delete[] N-OperandList;
+N-OperandList = 0;
+N-NumOperands = 0;
+
+// Finally, remove N itself.
+AllNodes.erase(N);
}
// If the root changed (e.g. it was a dead load, update the root).
setRoot(Dummy.getValue());
}
-/// DestroyDeadNode - We know that N is dead. Nuke it from the CSE maps for
the
-/// graph. If it is the last user of any of its operands, recursively process
-/// them the same way.
-///
-void SelectionDAG::DestroyDeadNode(SDNode *N) {
- // Okay, we really are going to delete this node. First take this out of the
- // appropriate CSE map.
- RemoveNodeFromCSEMaps(N);
-
- // Next, brutally remove the operand list. This is safe to do, as there are
- // no cycles in the graph.
- for (SDNode::op_iterator I = N-op_begin(), E = N-op_end(); I != E; ++I) {
-SDNode *O = I-Val;
-O-removeUser(N);
-
-// Now that we removed this operand, see if there are no uses of it left.
-if (O-use_empty())
- DestroyDeadNode(O);
- }
- delete[] N-OperandList;
- N-OperandList = 0;
- N-NumOperands = 0;
-
- // Mark the node as dead.
- N-MorphNodeTo(65535);
-}
-
void SelectionDAG::DeleteNode(SDNode *N) {
assert(N-use_empty() Cannot delete a node that is not dead!);
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.382 - 1.383
---
Log message:
Fix a case where LegalizeAllNodesNotLeadingTo could take exponential time.
This manifested itself as really long time to compile
Regression/CodeGen/Generic/2003-05-28-ManyArgs.ll on ppc.
This is PR847: http://llvm.org/PR847 .
---
Diffs of the changes: (+21 -6)
LegalizeDAG.cpp | 27 +--
1 files changed, 21 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.382
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.383
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.382 Tue Jul 11 12:58:07 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jul 26 18:55:56 2006
@@ -177,7 +177,8 @@
/// build_vector Mask. If it's not a legal shuffle, it returns null.
SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
- bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
+ bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
+std::setSDNode* NodesLeadingTo);
void LegalizeSetCCOperands(SDOperand LHS, SDOperand RHS, SDOperand CC);
@@ -406,10 +407,18 @@
/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
/// see if any uses can reach Dest. If no dest operands can get to dest,
/// legalize them, legalize ourself, and return false, otherwise, return true.
-bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
-SDNode *Dest) {
+///
+/// Keep track of the nodes we fine that actually do lead to Dest in
+/// NodesLeadingTo. This avoids retraversing them exponential number of times.
+///
+bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode
*Dest,
+std::setSDNode* NodesLeadingTo)
{
if (N == Dest) return true; // N certainly leads to Dest :)
+ // If we've already processed this node and it does lead to Dest, there is no
+ // need to reprocess it.
+ if (NodesLeadingTo.count(N)) return true;
+
// If the first result of this node has been already legalized, then it
cannot
// reach N.
switch (getTypeAction(N-getValueType(0))) {
@@ -429,9 +438,12 @@
bool OperandsLeadToDest = false;
for (unsigned i = 0, e = N-getNumOperands(); i != e; ++i)
OperandsLeadToDest |= // If an operand leads to Dest, so do we.
- LegalizeAllNodesNotLeadingTo(N-getOperand(i).Val, Dest);
+ LegalizeAllNodesNotLeadingTo(N-getOperand(i).Val, Dest, NodesLeadingTo);
- if (OperandsLeadToDest) return true;
+ if (OperandsLeadToDest) {
+NodesLeadingTo.insert(N);
+return true;
+ }
// Okay, this node looks safe, legalize it and return false.
HandleOp(SDOperand(N, 0));
@@ -1043,8 +1055,11 @@
// Recursively Legalize all of the inputs of the call end that do not lead
// to this call start. This ensures that any libcalls that need be
inserted
// are inserted *before* the CALLSEQ_START.
+{std::setSDNode* NodesLeadingTo;
for (unsigned i = 0, e = CallEnd-getNumOperands(); i != e; ++i)
- LegalizeAllNodesNotLeadingTo(CallEnd-getOperand(i).Val, Node);
+ LegalizeAllNodesNotLeadingTo(CallEnd-getOperand(i).Val, Node,
+ NodesLeadingTo);
+}
// Now that we legalized all of the inputs (which may have inserted
// libcalls) create the new CALLSEQ_START node.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp ScheduleDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.381 - 1.382
ScheduleDAG.cpp updated: 1.96 - 1.97
---
Log message:
Ensure that dump calls that are associated with asserts are removed from
non-debug build.
---
Diffs of the changes: (+14 -2)
LegalizeDAG.cpp | 14 +-
ScheduleDAG.cpp |2 +-
2 files changed, 14 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.381
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.382
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.381 Mon Jul 10 20:40:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jul 11 12:58:07 2006
@@ -540,7 +540,9 @@
return Result.getValue(Op.ResNo);
}
// Otherwise this is an unhandled builtin node. splat.
+#ifndef NDEBUG
std::cerr NODE: ; Node-dump(); std::cerr \n;
+#endif
assert(0 Do not know how to legalize this operator!);
abort();
case ISD::GlobalAddress:
@@ -2865,7 +2867,9 @@
case ISD::CopyFromReg:
assert(0 CopyFromReg must be legal!);
default:
+#ifndef NDEBUG
std::cerr NODE: ; Node-dump(); std::cerr \n;
+#endif
assert(0 Do not know how to promote this operator!);
abort();
case ISD::UNDEF:
@@ -4205,7 +4209,9 @@
case ISD::CopyFromReg:
assert(0 CopyFromReg must be legal!);
default:
+#ifndef NDEBUG
std::cerr NODE: ; Node-dump(); std::cerr \n;
+#endif
assert(0 Do not know how to expand this operator!);
abort();
case ISD::UNDEF:
@@ -4703,7 +4709,11 @@
}
switch (Node-getOpcode()) {
- default: Node-dump(); assert(0 Unhandled operation in SplitVectorOp!);
+ default:
+#ifndef NDEBUG
+Node-dump();
+#endif
+assert(0 Unhandled operation in SplitVectorOp!);
case ISD::VBUILD_VECTOR: {
std::vectorSDOperand LoOps(Node-op_begin(),
Node-op_begin()+NewNumElts);
LoOps.push_back(NewNumEltsNode);
@@ -4820,7 +4830,9 @@
SDOperand Result;
switch (Node-getOpcode()) {
default:
+#ifndef NDEBUG
Node-dump(); std::cerr \n;
+#endif
assert(0 Unknown vector operation in PackVectorOp!);
case ISD::VADD:
case ISD::VSUB:
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.96
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.97
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.96 Thu Jun 15 02:22:16 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Tue Jul 11 12:58:07 2006
@@ -421,7 +421,7 @@
} else {
switch (Node-getOpcode()) {
default:
- Node-dump();
+ DEBUG(Node-dump());
assert(0 This target-independent node should have been selected!);
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
___
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