[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.149 - 1.150
X86ISelLowering.cpp updated: 1.413 - 1.414
X86ISelLowering.h updated: 1.100 - 1.101
---
Log message:
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
---
Diffs of the changes: (+3 -1)
X86ISelDAGToDAG.cpp |2 +-
X86ISelLowering.cpp |1 +
X86ISelLowering.h |1 +
3 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.149
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.150
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.149 Wed Apr 11 17:29:46 2007
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jun 22 09:59:07 2007
@@ -744,7 +744,7 @@
// On x86-64, the resultant disp must fit in 32-bits.
isInt32(AM.Disp + CN-getSignExtended())
// Check to see if the LHS C is zero.
-TLI.MaskedValueIsZero(N.getOperand(0), CN-getValue())) {
+CurDAG-MaskedValueIsZero(N.getOperand(0), CN-getValue())) {
AM.Disp += CN-getValue();
return false;
}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.413
llvm/lib/Target/X86/X86ISelLowering.cpp:1.414
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.413 Mon Jun 18 19:13:10 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Jun 22 09:59:07 2007
@@ -4506,6 +4506,7 @@
uint64_t Mask,
uint64_t KnownZero,
uint64_t KnownOne,
+ const SelectionDAG DAG,
unsigned Depth) const {
unsigned Opc = Op.getOpcode();
assert((Opc = ISD::BUILTIN_OP_END ||
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.100
llvm/lib/Target/X86/X86ISelLowering.h:1.101
--- llvm/lib/Target/X86/X86ISelLowering.h:1.100 Tue Apr 24 16:16:55 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Fri Jun 22 09:59:07 2007
@@ -319,6 +319,7 @@
uint64_t Mask,
uint64_t KnownZero,
uint64_t KnownOne,
+const SelectionDAG DAG,
unsigned Depth = 0) const;
SDOperand getReturnAddressFrameIndex(SelectionDAG DAG);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.148 - 1.149
---
Log message:
Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
---
Diffs of the changes: (+8 -6)
X86ISelDAGToDAG.cpp | 14 --
1 files changed, 8 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.148
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.149
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.148 Wed Mar 28 13:38:33 2007
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Apr 11 17:29:46 2007
@@ -491,13 +491,15 @@
do {
for (MachineBasicBlock::iterator I = MBBI-begin(), E = MBBI-end();
!ContainsFPCode I != E; ++I) {
-for (unsigned op = 0, e = I-getNumOperands(); op != e; ++op) {
- if (I-getOperand(op).isRegister() I-getOperand(op).isDef()
- MRegisterInfo::isVirtualRegister(I-getOperand(op).getReg())
- RegMap-getRegClass(I-getOperand(0).getReg()) ==
+if (I-getNumOperands() != 0 I-getOperand(0).isRegister()) {
+ for (unsigned op = 0, e = I-getNumOperands(); op != e; ++op) {
+if (I-getOperand(op).isRegister() I-getOperand(op).isDef()
+MRegisterInfo::isVirtualRegister(I-getOperand(op).getReg())
+RegMap-getRegClass(I-getOperand(0).getReg()) ==
X86::RFPRegisterClass) {
-ContainsFPCode = true;
-break;
+ ContainsFPCode = true;
+ break;
+}
}
}
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.145 - 1.146
X86InstrInfo.cpp updated: 1.78 - 1.79
---
Log message:
Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2, #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
---
Diffs of the changes: (+39 -13)
X86ISelDAGToDAG.cpp |7 +++
X86InstrInfo.cpp| 45 -
2 files changed, 39 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.145
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.146
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.145 Sun Feb 4 14:18:17 2007
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Mar 20 01:08:29 2007
@@ -886,10 +886,9 @@
else
AM.IndexReg = CurDAG-getRegister(0, VT);
- if (AM.Scale 2)
-Complexity += 2;
- // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg
- else if (AM.Scale 1)
+ // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or
with
+ // a simple shift.
+ if (AM.Scale 1)
Complexity++;
// FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.78
llvm/lib/Target/X86/X86InstrInfo.cpp:1.79
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.78 Thu Mar 8 16:09:11 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Mar 20 01:08:29 2007
@@ -132,29 +132,57 @@
MachineInstr *NewMI = NULL;
// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
- // we have subtarget support, enable the 16-bit LEA generation here.
+ // we have better subtarget support, enable the 16-bit LEA generation here.
bool DisableLEA16 = true;
switch (MI-getOpcode()) {
- default: break;
+ default: return 0;
case X86::SHUFPSrri: {
assert(MI-getNumOperands() == 4 Unknown shufps instruction!);
-const X86Subtarget *Subtarget = TM.getSubtargetX86Subtarget();
+if (!TM.getSubtargetX86Subtarget().hasSSE2()) return 0;
+
unsigned A = MI-getOperand(0).getReg();
unsigned B = MI-getOperand(1).getReg();
unsigned C = MI-getOperand(2).getReg();
-unsigned M = MI-getOperand(3).getImmedValue();
-if (!Subtarget-hasSSE2() || B != C) return 0;
+unsigned M = MI-getOperand(3).getImm();
+if (B != C) return 0;
NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
-goto Done;
+break;
+ }
+ case X86::SHL32ri: {
+assert(MI-getNumOperands() == 3 Unknown shift instruction!);
+// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
+// the flags produced by a shift yet, so this is safe.
+unsigned Dest = MI-getOperand(0).getReg();
+unsigned Src = MI-getOperand(1).getReg();
+unsigned ShAmt = MI-getOperand(2).getImm();
+if (ShAmt == 0 || ShAmt = 4) return 0;
+
+NewMI = BuildMI(get(X86::LEA32r), Dest)
+ .addReg(0).addImm(1 ShAmt).addReg(Src).addImm(0);
+break;
+ }
+ case X86::SHL16ri: {
+assert(MI-getNumOperands() == 3 Unknown shift instruction!);
+if (DisableLEA16) return 0;
+
+// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
+// the flags produced by a shift yet, so this is safe.
+unsigned Dest = MI-getOperand(0).getReg();
+unsigned Src = MI-getOperand(1).getReg();
+unsigned ShAmt = MI-getOperand(2).getImm();
+if (ShAmt == 0 || ShAmt = 4) return 0;
+
+NewMI = BuildMI(get(X86::LEA16r), Dest)
+ .addReg(0).addImm(1 ShAmt).addReg(Src).addImm(0);
+break;
}
}
// FIXME: None of these instructions are promotable to LEAs without
// additional information. In particular, LEA doesn't set the flags that
// add and inc do. :(
- return 0;
-
+ if (0)
switch (MI-getOpcode()) {
case X86::INC32r:
case X86::INC64_32r:
@@ -220,7 +248,6 @@
break;
}
-Done:
if (NewMI) {
NewMI-copyKillDeadInfo(MI);
LV.instructionChanged(MI, NewMI); // Update live variables
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.144 - 1.145
---
Log message:
Fix a miscompilation in the addr mode code trying to implement X | C and
X + C to promote LEA formation. We would incorrectly apply it in some cases
(test) and miss it in others.
This fixes CodeGen/X86/2007-02-04-OrAddrMode.ll
---
Diffs of the changes: (+17 -20)
X86ISelDAGToDAG.cpp | 37 +
1 files changed, 17 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.144
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.145
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.144 Mon Jan 22 15:34:25 2007
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Feb 4 14:18:17 2007
@@ -677,7 +677,7 @@
if (!Available
AM.BaseType == X86ISelAddressMode::RegBase
AM.Base.Reg.Val == 0
-AM.IndexReg.Val == 0)
+AM.IndexReg.Val == 0) {
if (ConstantSDNode *CN = dyn_castConstantSDNode(N.Val-getOperand(1)))
if (CN-getValue() == 3 || CN-getValue() == 5 || CN-getValue() == 9)
{
AM.Scale = unsigned(CN-getValue())-1;
@@ -705,9 +705,10 @@
AM.IndexReg = AM.Base.Reg = Reg;
return false;
}
+}
break;
- case ISD::ADD: {
+ case ISD::ADD:
if (!Available) {
X86ISelAddressMode Backup = AM;
if (!MatchAddress(N.Val-getOperand(0), AM, false)
@@ -720,32 +721,28 @@
AM = Backup;
}
break;
- }
- case ISD::OR: {
+ case ISD::OR:
+// Handle X | C as X + C iff X is known to have C bits clear.
if (!Available) {
- X86ISelAddressMode Backup = AM;
- // Look for (x c1) | c2 where (c2 c1)
- ConstantSDNode *CN = dyn_castConstantSDNode(N.Val-getOperand(0));
- if (CN !MatchAddress(N.Val-getOperand(1), AM, false)) {
-if (AM.GV == NULL AM.Disp == 0 CN-getValue() AM.Scale) {
- AM.Disp = CN-getValue();
+ if (ConstantSDNode *CN = dyn_castConstantSDNode(N.getOperand(1))) {
+X86ISelAddressMode Backup = AM;
+// Start with the LHS as an addr mode.
+if (!MatchAddress(N.getOperand(0), AM, false)
+// Address could not have picked a GV address for the displacement.
+AM.GV == NULL
+// On x86-64, the resultant disp must fit in 32-bits.
+isInt32(AM.Disp + CN-getSignExtended())
+// Check to see if the LHS C is zero.
+TLI.MaskedValueIsZero(N.getOperand(0), CN-getValue())) {
+ AM.Disp += CN-getValue();
return false;
}
+AM = Backup;
}
- AM = Backup;
- CN = dyn_castConstantSDNode(N.Val-getOperand(1));
- if (CN !MatchAddress(N.Val-getOperand(0), AM, false)) {
-if (AM.GV == NULL AM.Disp == 0 CN-getValue() AM.Scale) {
- AM.Disp = CN-getValue();
- return false;
-}
- }
- AM = Backup;
}
break;
}
- }
// Is the base register already occupied?
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86Subtarget.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.143 - 1.144
X86ISelLowering.cpp updated: 1.314 - 1.315
X86Subtarget.cpp updated: 1.49 - 1.50
---
Log message:
Linux GOT indirect reference is only necessary in PIC mode.
---
Diffs of the changes: (+5 -3)
X86ISelDAGToDAG.cpp |3 ++-
X86ISelLowering.cpp |3 ++-
X86Subtarget.cpp|2 +-
3 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.143
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.144
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.143 Fri Jan 12 17:22:14 2007
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jan 22 15:34:25 2007
@@ -947,7 +947,8 @@
// If we're using vanilla 'GOT' PIC style, we should use relative
addressing
// not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
-if (Subtarget-isPICStyleGOT()) {
+if (TM.getRelocationModel() == Reloc::PIC_
+Subtarget-isPICStyleGOT()) {
GlobalBaseReg = RegMap-createVirtualRegister(X86::GR32RegisterClass);
BuildMI(FirstMBB, MBBI, TII-get(X86::ADD32ri), GlobalBaseReg).
addReg(PC).
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.314
llvm/lib/Target/X86/X86ISelLowering.cpp:1.315
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.314 Fri Jan 12 13:20:47 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 22 15:34:25 2007
@@ -664,7 +664,8 @@
InFlag = Chain.getValue(1);
}
- if (Subtarget-isPICStyleGOT()) {
+ if (getTargetMachine().getRelocationModel() == Reloc::PIC_
+ Subtarget-isPICStyleGOT()) {
Chain = DAG.getCopyToReg(Chain, X86::EBX,
DAG.getNode(X86ISD::GlobalBaseReg,
getPointerTy()),
InFlag);
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.49
llvm/lib/Target/X86/X86Subtarget.cpp:1.50
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.49 Wed Jan 17 04:33:08 2007
+++ llvm/lib/Target/X86/X86Subtarget.cppMon Jan 22 15:34:25 2007
@@ -40,7 +40,7 @@
return (!isDirectCall
(GV-hasWeakLinkage() || GV-hasLinkOnceLinkage() ||
(GV-isExternal() !GV-hasNotBeenReadFromBytecode(;
-} else if (isPICStyleGOT()) {
+} else if (TM.getRelocationModel() == Reloc::PIC_ isPICStyleGOT()) {
// Extra load is needed for all non-statics.
return (!isDirectCall
(GV-isExternal() || !GV-hasInternalLinkage()));
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86TargetAsmInfo.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.142 - 1.143 X86TargetAsmInfo.cpp updated: 1.19 - 1.20 --- Log message: Adjust #includes to compensate for lost of DerivedTypes.h in TargetLowering.h --- Diffs of the changes: (+2 -0) X86ISelDAGToDAG.cpp |1 + X86TargetAsmInfo.cpp |1 + 2 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.142 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.143 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.142 Fri Jan 12 13:20:47 2007 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jan 12 17:22:14 2007 @@ -23,6 +23,7 @@ #include llvm/Instructions.h #include llvm/Intrinsics.h #include llvm/Support/CFG.h +#include llvm/Type.h #include llvm/CodeGen/MachineConstantPool.h #include llvm/CodeGen/MachineFunction.h #include llvm/CodeGen/MachineFrameInfo.h Index: llvm/lib/Target/X86/X86TargetAsmInfo.cpp diff -u llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.19 llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.20 --- llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.19 Fri Jan 12 01:05:13 2007 +++ llvm/lib/Target/X86/X86TargetAsmInfo.cppFri Jan 12 17:22:14 2007 @@ -14,6 +14,7 @@ #include X86TargetAsmInfo.h #include X86TargetMachine.h #include X86Subtarget.h +#include llvm/DerivedTypes.h #include llvm/InlineAsm.h #include llvm/Instructions.h #include llvm/Module.h ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86InstrX86-64.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.132 - 1.133
X86ISelLowering.cpp updated: 1.298 - 1.299
X86ISelLowering.h updated: 1.80 - 1.81
X86InstrInfo.td updated: 1.295 - 1.296
X86InstrX86-64.td updated: 1.8 - 1.9
---
Log message:
- Use a different wrapper node for RIP-relative GV, etc.
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
---
Diffs of the changes: (+81 -62)
X86ISelDAGToDAG.cpp | 64
X86ISelLowering.cpp | 43 +-
X86ISelLowering.h |4 +++
X86InstrInfo.td |5 +++-
X86InstrX86-64.td | 27 +
5 files changed, 81 insertions(+), 62 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.132
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.133
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.132 Wed Nov 29 17:46:27 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Nov 30 15:55:46 2006
@@ -590,63 +590,19 @@
break;
}
- case ISD::TargetConstantPool:
-if (AM.BaseType == X86ISelAddressMode::RegBase
-AM.Base.Reg.Val == 0
-AM.CP == 0) {
- ConstantPoolSDNode *CP = castConstantPoolSDNode(N);
- AM.CP = CP-getConstVal();
- AM.Align = CP-getAlignment();
- AM.Disp += CP-getOffset();
- return false;
-}
-break;
-
- case ISD::TargetGlobalAddress:
-if (AM.BaseType == X86ISelAddressMode::RegBase
-AM.Base.Reg.Val == 0
-AM.GV == 0) {
- GlobalAddressSDNode *G = castGlobalAddressSDNode(N);
- AM.GV = G-getGlobal();
- AM.Disp += G-getOffset();
- return false;
-}
-break;
-
- case ISD::TargetExternalSymbol:
-if (isRoot
-AM.BaseType == X86ISelAddressMode::RegBase
-AM.Base.Reg.Val == 0) {
- ExternalSymbolSDNode *S = castExternalSymbolSDNode(N.getOperand(0));
- AM.ES = S-getSymbol();
- return false;
-}
-break;
-
- case ISD::TargetJumpTable:
-if (isRoot
-AM.BaseType == X86ISelAddressMode::RegBase
-AM.Base.Reg.Val == 0) {
- JumpTableSDNode *J = castJumpTableSDNode(N.getOperand(0));
- AM.JT = J-getIndex();
- return false;
-}
-break;
-
case X86ISD::Wrapper:
+ case X86ISD::WrapperRIP: {
+bool isRIP = N.getOpcode() == X86ISD::WrapperRIP;
+// Under X86-64 non-small code model, GV (and friends) are 64-bits.
+if (!isRIP Subtarget-is64Bit() TM.getCodeModel() !=
CodeModel::Small)
+ break;
+
// If value is available in a register both base and index components have
// been picked, we can't fit the result available in the register in the
// addressing mode. Duplicate GlobalAddress or ConstantPool as
displacement.
-
-// Can't fit GV or CP in addressing mode for X86-64 medium or large code
-// model since the displacement field is 32-bit. Ok for small code model.
-
-// For X86-64 PIC code, only allow GV / CP + displacement so we can use RIP
-// relative addressing mode.
-if (Subtarget-is64Bit() TM.getCodeModel() != CodeModel::Small)
- break;
if (!Available || (AM.Base.Reg.Val AM.IndexReg.Val)) {
- bool isRIP = Subtarget-is64Bit();
+ // For X86-64 PIC code, only allow GV / CP + displacement so we can use
+ // RIP relative addressing mode.
if (isRIP
(AM.Base.Reg.Val || AM.Scale 1 || AM.IndexReg.Val ||
AM.BaseType == X86ISelAddressMode::FrameIndexBase))
@@ -683,6 +639,7 @@
}
}
break;
+ }
case ISD::FrameIndex:
if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
@@ -1040,7 +997,8 @@
SDOperand N0 = N.getOperand(0);
SDOperand N1 = N.getOperand(1);
if (N.Val-getValueType(0) == PtrVT
- N0.getOpcode() == X86ISD::Wrapper
+ (N0.getOpcode() == X86ISD::Wrapper
+ || N0.getOpcode() == X86ISD::WrapperRIP)
N1.getOpcode() == ISD::Constant) {
unsigned Offset = (unsigned)castConstantSDNode(N1)-getValue();
SDOperand C(0, 0);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.298
llvm/lib/Target/X86/X86ISelLowering.cpp:1.299
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.298 Wed Nov 29 17:48:14 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Nov 30 15:55:46 2006
@@ -3832,8 +3832,15 @@
SDOperand Result = DAG.getTargetConstantPool(CP-getConstVal(),
getPointerTy(),
CP-getAlignment());
+ // Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
+ TargetMachine tm = getTargetMachine();
+ unsigned WrapperOpcode = (Subtarget-is64Bit()
+(tm.getCodeModel() == CodeModel::Small ||
+ tm.getCodeModel() ==
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.131 - 1.132
---
Log message:
Clean up.
---
Diffs of the changes: (+8 -8)
X86ISelDAGToDAG.cpp | 16
1 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.131
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.132
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.131 Wed Nov 29 17:19:45 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Nov 29 17:46:27 2006
@@ -643,11 +643,13 @@
// For X86-64 PIC code, only allow GV / CP + displacement so we can use RIP
// relative addressing mode.
-if ((!Subtarget-is64Bit() || TM.getCodeModel() == CodeModel::Small)
-(!Available || (AM.Base.Reg.Val AM.IndexReg.Val))) {
+if (Subtarget-is64Bit() TM.getCodeModel() != CodeModel::Small)
+ break;
+if (!Available || (AM.Base.Reg.Val AM.IndexReg.Val)) {
bool isRIP = Subtarget-is64Bit();
- if (isRIP (AM.Base.Reg.Val || AM.Scale 1 || AM.IndexReg.Val ||
-AM.BaseType == X86ISelAddressMode::FrameIndexBase))
+ if (isRIP
+ (AM.Base.Reg.Val || AM.Scale 1 || AM.IndexReg.Val ||
+ AM.BaseType == X86ISelAddressMode::FrameIndexBase))
break;
if (ConstantPoolSDNode *CP =
dyn_castConstantPoolSDNode(N.getOperand(0))) {
@@ -655,8 +657,7 @@
AM.CP = CP-getConstVal();
AM.Align = CP-getAlignment();
AM.Disp += CP-getOffset();
- if (isRIP)
-AM.isRIPRel = true;
+ AM.isRIPRel = isRIP;
return false;
}
} else if (GlobalAddressSDNode *G =
@@ -664,8 +665,7 @@
if (AM.GV == 0) {
AM.GV = G-getGlobal();
AM.Disp += G-getOffset();
- if (isRIP)
-AM.isRIPRel = true;
+ AM.isRIPRel = isRIP;
return false;
}
} else if (isRoot isRIP) {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.128 - 1.129
---
Log message:
For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX while
clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.
---
Diffs of the changes: (+46 -29)
X86ISelDAGToDAG.cpp | 75 +++-
1 files changed, 46 insertions(+), 29 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.128
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.129
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.128 Fri Nov 17 01:52:03 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Nov 17 16:10:14 2006
@@ -1141,7 +1141,7 @@
default: assert(0 Unsupported VT!);
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
-ClrOpcode = X86::MOV8r0;
+ClrOpcode = 0;
SExtOpcode = X86::CBW;
break;
case MVT::i16:
@@ -1163,53 +1163,70 @@
SDOperand N0 = Node-getOperand(0);
SDOperand N1 = Node-getOperand(1);
-
- bool foldedLoad = false;
- SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
- foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
- SDOperand Chain;
- if (foldedLoad) {
-Chain = N1.getOperand(0);
-AddToISelQueue(Chain);
- } else
-Chain = CurDAG-getEntryNode();
-
SDOperand InFlag(0, 0);
- AddToISelQueue(N0);
- Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(LoReg, NVT),
-N0, InFlag);
- InFlag = Chain.getValue(1);
-
- if (isSigned) {
-// Sign extend the low part into the high part.
-InFlag =
- SDOperand(CurDAG-getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
- } else {
-// Zero out the high part, effectively zero extending the input.
-SDOperand ClrNode = SDOperand(CurDAG-getTargetNode(ClrOpcode, NVT),
0);
-Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(HiReg, NVT),
- ClrNode, InFlag);
+ if (NVT == MVT::i8 !isSigned) {
+// Special case for div8, just use a move with zero extension to AX to
+// clear the upper 8 bits (AH).
+SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
+if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
+ SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
+ AddToISelQueue(N0.getOperand(0));
+ AddToISelQueue(Tmp0);
+ AddToISelQueue(Tmp1);
+ AddToISelQueue(Tmp2);
+ AddToISelQueue(Tmp3);
+ Move =
+SDOperand(CurDAG-getTargetNode(X86::MOVZX16rm8, MVT::i16,
MVT::Other,
+Ops, 5), 0);
+ Chain = Move.getValue(1);
+ ReplaceUses(N0.getValue(1), Chain);
+} else {
+ AddToISelQueue(N0);
+ Move =
+SDOperand(CurDAG-getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
+ Chain = CurDAG-getEntryNode();
+}
+Chain = CurDAG-getCopyToReg(Chain, X86::AX, Move, InFlag);
InFlag = Chain.getValue(1);
+ } else {
+AddToISelQueue(N0);
+InFlag =
+ CurDAG-getCopyToReg(CurDAG-getEntryNode(), LoReg, N0,
+ InFlag).getValue(1);
+if (isSigned) {
+ // Sign extend the low part into the high part.
+ InFlag =
+SDOperand(CurDAG-getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
+} else {
+ // Zero out the high part, effectively zero extending the input.
+ SDOperand ClrNode = SDOperand(CurDAG-getTargetNode(ClrOpcode, NVT),
0);
+ InFlag = CurDAG-getCopyToReg(CurDAG-getEntryNode(), HiReg, ClrNode,
+InFlag).getValue(1);
+}
}
+ SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Chain;
+ bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
if (foldedLoad) {
+AddToISelQueue(N1.getOperand(0));
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
-SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
+SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else {
AddToISelQueue(N1);
+Chain = CurDAG-getEntryNode();
InFlag =
SDOperand(CurDAG-getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
- SDOperand Result = CurDAG-getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
-NVT, InFlag);
+ SDOperand Result =
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.122 - 1.123
---
Log message:
Match tblegen changes.
---
Diffs of the changes: (+16 -15)
X86ISelDAGToDAG.cpp | 31 ---
1 files changed, 16 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.122
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.123
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.122 Sun Nov 5 13:31:28 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Nov 8 14:34:28 2006
@@ -143,11 +143,11 @@
SDNode *Select(SDOperand N);
bool MatchAddress(SDOperand N, X86ISelAddressMode AM, bool isRoot = true);
-bool SelectAddr(SDOperand N, SDOperand Base, SDOperand Scale,
-SDOperand Index, SDOperand Disp);
-bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
- SDOperand Index, SDOperand Disp);
-bool SelectScalarSSELoad(SDOperand Root, SDOperand Pred,
+bool SelectAddr(SDOperand Op, SDOperand N, SDOperand Base,
+SDOperand Scale, SDOperand Index, SDOperand Disp);
+bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand Base,
+ SDOperand Scale, SDOperand Index, SDOperand Disp);
+bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp,
SDOperand InChain, SDOperand OutChain);
@@ -773,8 +773,9 @@
/// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can
/// match by reference.
-bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand Base, SDOperand
Scale,
- SDOperand Index, SDOperand Disp) {
+bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand Base,
+ SDOperand Scale, SDOperand Index,
+ SDOperand Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
return false;
@@ -805,7 +806,7 @@
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
-bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Root, SDOperand Pred,
+bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
SDOperand N, SDOperand Base,
SDOperand Scale, SDOperand Index,
SDOperand Disp, SDOperand InChain,
@@ -814,9 +815,9 @@
InChain = N.getOperand(0).getValue(1);
if (ISD::isNON_EXTLoad(InChain.Val)
InChain.getValue(0).hasOneUse()
-CanBeFoldedBy(N.Val, Pred.Val, Root.Val)) {
+CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
LoadSDNode *LD = castLoadSDNode(InChain);
- if (!SelectAddr(LD-getBasePtr(), Base, Scale, Index, Disp))
+ if (!SelectAddr(Op, LD-getBasePtr(), Base, Scale, Index, Disp))
return false;
OutChain = LD-getChain();
return true;
@@ -856,7 +857,7 @@
// Okay, this is a zero extending load. Fold it.
LoadSDNode *LD = castLoadSDNode(N.getOperand(1).getOperand(0));
- if (!SelectAddr(LD-getBasePtr(), Base, Scale, Index, Disp))
+ if (!SelectAddr(Op, LD-getBasePtr(), Base, Scale, Index, Disp))
return false;
OutChain = LD-getChain();
InChain = SDOperand(LD, 1);
@@ -869,8 +870,8 @@
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal
addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
-bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand Base,
-SDOperand Scale,
+bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
+SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
@@ -927,7 +928,7 @@
if (ISD::isNON_EXTLoad(N.Val)
N.hasOneUse()
CanBeFoldedBy(N.Val, P.Val, P.Val))
-return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
+return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
return false;
}
@@ -1288,7 +1289,7 @@
case 'v': // not offsetable??
default: return true;
case 'm': // memory
-if (!SelectAddr(Op, Op0, Op1, Op2, Op3))
+if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
return true;
break;
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86RegisterInfo.h
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.121 - 1.122
X86RegisterInfo.h updated: 1.41 - 1.42
---
Log message:
Unbreak VC++ build.
---
Diffs of the changes: (+4 -2)
X86ISelDAGToDAG.cpp |2 +-
X86RegisterInfo.h |4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.121
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.122
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.121 Thu Nov 2 19:13:15 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Nov 5 13:31:28 2006
@@ -663,7 +663,7 @@
AM.IndexReg = ShVal.Val-getOperand(0);
ConstantSDNode *AddVal =
castConstantSDNode(ShVal.Val-getOperand(1));
-uint64_t Disp = AM.Disp + AddVal-getValue() Val;
+uint64_t Disp = AM.Disp + (AddVal-getValue() Val);
if (isInt32(Disp))
AM.Disp = Disp;
else
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.41
llvm/lib/Target/X86/X86RegisterInfo.h:1.42
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.41 Fri Sep 8 01:48:29 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h Sun Nov 5 13:31:28 2006
@@ -22,9 +22,11 @@
class TargetInstrInfo;
class X86TargetMachine;
-struct X86RegisterInfo : public X86GenRegisterInfo {
+class X86RegisterInfo : public X86GenRegisterInfo {
+public:
X86TargetMachine TM;
const TargetInstrInfo TII;
+
private:
/// Is64Bit - Is the target 64-bits.
bool Is64Bit;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.120 - 1.121
---
Log message:
silence warning
---
Diffs of the changes: (+0 -6)
X86ISelDAGToDAG.cpp |6 --
1 files changed, 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.120
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.121
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.120 Mon Oct 16 01:34:55 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Nov 2 19:13:15 2006
@@ -931,12 +931,6 @@
return false;
}
-static bool isRegister0(SDOperand Op) {
- if (RegisterSDNode *R = dyn_castRegisterSDNode(Op))
-return (R-getReg() == 0);
- return false;
-}
-
/// getGlobalBaseReg - Output the instructions required to put the
/// base address to use for accessing globals into a register.
///
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.119 - 1.120
---
Log message:
SelectScalarSSELoad should call CanBeFoldedBy as well.
---
Diffs of the changes: (+7 -3)
X86ISelDAGToDAG.cpp | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.119
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.120
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.119 Sat Oct 14 03:33:25 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Oct 16 01:34:55 2006
@@ -147,7 +147,8 @@
SDOperand Index, SDOperand Disp);
bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
-bool SelectScalarSSELoad(SDOperand N, SDOperand Base, SDOperand Scale,
+bool SelectScalarSSELoad(SDOperand Root, SDOperand Pred,
+ SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp,
SDOperand InChain, SDOperand OutChain);
bool TryFoldLoad(SDOperand P, SDOperand N,
@@ -804,13 +805,16 @@
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
-bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand N, SDOperand Base,
+bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Root, SDOperand Pred,
+ SDOperand N, SDOperand Base,
SDOperand Scale, SDOperand Index,
SDOperand Disp, SDOperand InChain,
SDOperand OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
InChain = N.getOperand(0).getValue(1);
-if (ISD::isNON_EXTLoad(InChain.Val) InChain.getValue(0).hasOneUse()) {
+if (ISD::isNON_EXTLoad(InChain.Val)
+InChain.getValue(0).hasOneUse()
+CanBeFoldedBy(N.Val, Pred.Val, Root.Val)) {
LoadSDNode *LD = castLoadSDNode(InChain);
if (!SelectAddr(LD-getBasePtr(), Base, Scale, Index, Disp))
return false;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrFPStack.td X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.117 - 1.118
X86ISelLowering.cpp updated: 1.274 - 1.275
X86InstrFPStack.td updated: 1.7 - 1.8
X86InstrInfo.td updated: 1.291 - 1.292
---
Log message:
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
---
Diffs of the changes: (+35 -43)
X86ISelDAGToDAG.cpp |2 -
X86ISelLowering.cpp | 70 +++-
X86InstrFPStack.td |2 -
X86InstrInfo.td |4 +-
4 files changed, 35 insertions(+), 43 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.117
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.118
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.117 Thu Oct 12 14:13:59 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Oct 13 16:14:26 2006
@@ -372,7 +372,7 @@
void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG DAG) {
for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
E = DAG.allnodes_end(); I != E; ++I) {
-if (I-getOpcode() != ISD::STORE)
+if (!ISD::isNON_TRUNCStore(I))
continue;
SDOperand Chain = I-getOperand(0);
if (Chain.Val-getOpcode() != ISD::TokenFactor)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.274
llvm/lib/Target/X86/X86ISelLowering.cpp:1.275
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.274 Thu Oct 12 14:12:56 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Oct 13 16:14:26 2006
@@ -598,8 +598,7 @@
case MVT::f32: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL)));
+ MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 4;
break;
}
@@ -607,8 +606,7 @@
case MVT::f64: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL)));
+ MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 8;
break;
}
@@ -626,8 +624,7 @@
ArgOffset = ((ArgOffset + 15) / 16) * 16;
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
-MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL)));
+MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 16;
}
}
@@ -988,8 +985,7 @@
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
X86::GR64RegisterClass);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
- DAG.getSrcValue(NULL));
+ SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(8, getPointerTy()));
@@ -1002,8 +998,7 @@
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
X86::VR128RegisterClass);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
- DAG.getSrcValue(NULL));
+ SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(16, getPointerTy()));
@@ -1126,8 +1121,7 @@
} else {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
-MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL)));
+MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 8;
}
break;
@@ -1149,8 +1143,7 @@
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
-MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL)));
+MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
ArgOffset += 8;
else
@@ -1631,16 +1624,14 @@
case MVT::f32: {
SDOperand PtrOff =
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.116 - 1.117
---
Log message:
Doh. This wasn't causing problems by luck.
---
Diffs of the changes: (+1 -1)
X86ISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.116
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.117
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.116 Wed Oct 11 22:55:48 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Oct 12 14:13:59 2006
@@ -220,7 +220,7 @@
SDNode *User = *I;
for (unsigned i = 0, e = User-getNumOperands(); i != e; ++i) {
SDOperand Op = User-getOperand(i);
- if (Op.ResNo == FlagResNo)
+ if (Op.Val == N Op.ResNo == FlagResNo)
return User;
}
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.113 - 1.114
---
Log message:
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
---
Diffs of the changes: (+10 -7)
X86ISelDAGToDAG.cpp | 17 ++---
1 files changed, 10 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.113
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.114
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.113 Mon Oct 9 20:46:56 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Oct 11 16:06:01 2006
@@ -148,7 +148,8 @@
bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
bool SelectScalarSSELoad(SDOperand N, SDOperand Base, SDOperand Scale,
- SDOperand Index, SDOperand Disp);
+ SDOperand Index, SDOperand Disp,
+ SDOperand InChain, SDOperand OutChain);
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
@@ -781,20 +782,22 @@
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand N, SDOperand Base,
- SDOperand Scale,
- SDOperand Index, SDOperand Disp) {
-#if 0
+ SDOperand Scale, SDOperand Index,
+ SDOperand Disp, SDOperand InChain,
+ SDOperand OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
-if (N.getOperand(0).getOpcode() == ISD::LOAD) {
- SDOperand LoadAddr = N.getOperand(0).getOperand(0);
+InChain = N.getOperand(0);
+if (ISD::isNON_EXTLoad(InChain.Val)) {
+ LoadSDNode *LD = castLoadSDNode(InChain);
+ SDOperand LoadAddr = LD-getBasePtr();
if (!SelectAddr(LoadAddr, Base, Scale, Index, Disp))
return false;
+ OutChain = LD-getChain();
return true;
}
}
// TODO: Also handle the case where we explicitly require zeros in the top
// elements. This is a vector shuffle from the zero vector.
-#endif
return false;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.114 - 1.115
---
Log message:
Fold zero extending vector loads now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
---
Diffs of the changes: (+52 -5)
X86ISelDAGToDAG.cpp | 57 +++-
1 files changed, 52 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.114
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.115
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.114 Wed Oct 11 16:06:01 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Oct 11 17:09:58 2006
@@ -778,6 +778,16 @@
return true;
}
+/// isZeroNode - Returns true if Elt is a constant zero or a floating point
+/// constant +0.0.
+static inline bool isZeroNode(SDOperand Elt) {
+ return ((isaConstantSDNode(Elt)
+ castConstantSDNode(Elt)-getValue() == 0) ||
+ (isaConstantFPSDNode(Elt)
+ castConstantFPSDNode(Elt)-isExactlyValue(0.0)));
+}
+
+
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
@@ -786,19 +796,56 @@
SDOperand Disp, SDOperand InChain,
SDOperand OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
-InChain = N.getOperand(0);
+InChain = N.getOperand(0).getValue(1);
if (ISD::isNON_EXTLoad(InChain.Val)) {
LoadSDNode *LD = castLoadSDNode(InChain);
- SDOperand LoadAddr = LD-getBasePtr();
- if (!SelectAddr(LoadAddr, Base, Scale, Index, Disp))
+ if (!SelectAddr(LD-getBasePtr(), Base, Scale, Index, Disp))
return false;
OutChain = LD-getChain();
return true;
}
}
- // TODO: Also handle the case where we explicitly require zeros in the top
+
+ // Also handle the case where we explicitly require zeros in the top
// elements. This is a vector shuffle from the zero vector.
-
+ if (N.getOpcode() == ISD::VECTOR_SHUFFLE N.Val-hasOneUse()
+ N.getOperand(0).getOpcode() == ISD::BUILD_VECTOR
+ N.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR
+ N.getOperand(1).Val-hasOneUse()
+ ISD::isNON_EXTLoad(N.getOperand(1).getOperand(0).Val)
+ N.getOperand(1).getOperand(0).hasOneUse()) {
+// Check to see if the BUILD_VECTOR is building a zero vector.
+SDOperand BV = N.getOperand(0);
+for (unsigned i = 0, e = BV.getNumOperands(); i != e; ++i)
+ if (!isZeroNode(BV.getOperand(i))
+ BV.getOperand(i).getOpcode() != ISD::UNDEF)
+return false; // Not a zero/undef vector.
+// Check to see if the shuffle mask is 4/L/L/L or 2/L, where L is something
+// from the LHS.
+unsigned VecWidth = BV.getNumOperands();
+SDOperand ShufMask = N.getOperand(2);
+assert(ShufMask.getOpcode() == ISD::BUILD_VECTOR Invalid shuf mask!);
+if (ConstantSDNode *C = dyn_castConstantSDNode(ShufMask.getOperand(0))) {
+ if (C-getValue() == VecWidth) {
+for (unsigned i = 1; i != VecWidth; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF) {
+// ok.
+ } else {
+ConstantSDNode *C = castConstantSDNode(ShufMask.getOperand(i));
+if (C-getValue() = VecWidth) return false;
+ }
+}
+ }
+
+ // Okay, this is a zero extending load. Fold it.
+ LoadSDNode *LD = castLoadSDNode(N.getOperand(1).getOperand(0));
+ if (!SelectAddr(LD-getBasePtr(), Base, Scale, Index, Disp))
+return false;
+ OutChain = LD-getChain();
+ InChain = SDOperand(LD, 1);
+ return true;
+}
+ }
return false;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.115 - 1.116
---
Log message:
fix compilation failure of smg2000
---
Diffs of the changes: (+1 -1)
X86ISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.115
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.116
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.115 Wed Oct 11 17:09:58 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Oct 11 22:55:48 2006
@@ -797,7 +797,7 @@
SDOperand OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
InChain = N.getOperand(0).getValue(1);
-if (ISD::isNON_EXTLoad(InChain.Val)) {
+if (ISD::isNON_EXTLoad(InChain.Val) InChain.getValue(0).hasOneUse()) {
LoadSDNode *LD = castLoadSDNode(InChain);
if (!SelectAddr(LD-getBasePtr(), Base, Scale, Index, Disp))
return false;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrFPStack.td X86InstrInfo.td X86InstrSSE.td X86InstrX86-64.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.111 - 1.112
X86ISelLowering.cpp updated: 1.271 - 1.272
X86InstrFPStack.td updated: 1.6 - 1.7
X86InstrInfo.td updated: 1.287 - 1.288
X86InstrSSE.td updated: 1.162 - 1.163
X86InstrX86-64.td updated: 1.3 - 1.4
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+72 -83)
X86ISelDAGToDAG.cpp |8 ++---
X86ISelLowering.cpp | 77 ++--
X86InstrFPStack.td |2 -
X86InstrInfo.td | 38 -
X86InstrSSE.td |2 -
X86InstrX86-64.td | 28 +-
6 files changed, 72 insertions(+), 83 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.111
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.112
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.111 Sat Oct 7 16:55:32 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Oct 9 15:57:25 2006
@@ -346,9 +346,9 @@
case ISD::ADDE: {
SDOperand N10 = N1.getOperand(0);
SDOperand N11 = N1.getOperand(1);
-if (N10.Val-getOpcode() == ISD::LOAD)
+if (ISD::isNON_EXTLoad(N10.Val))
RModW = true;
-else if (N11.Val-getOpcode() == ISD::LOAD) {
+else if (ISD::isNON_EXTLoad(N11.Val)) {
RModW = true;
std::swap(N10, N11);
}
@@ -370,7 +370,7 @@
case X86ISD::SHLD:
case X86ISD::SHRD: {
SDOperand N10 = N1.getOperand(0);
-if (N10.Val-getOpcode() == ISD::LOAD)
+if (ISD::isNON_EXTLoad(N10.Val))
RModW = N10.Val-isOperand(Chain.Val) N10.hasOneUse()
(N10.getOperand(1) == N2)
(N10.Val-getValueType(0) == N1.getValueType());
@@ -806,7 +806,7 @@
bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp) {
- if (N.getOpcode() == ISD::LOAD
+ if (ISD::isNON_EXTLoad(N.Val)
N.hasOneUse()
CanBeFoldedBy(N.Val, P.Val))
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.271
llvm/lib/Target/X86/X86ISelLowering.cpp:1.272
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.271 Thu Oct 5 18:01:46 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Oct 9 15:57:25 2006
@@ -490,8 +490,7 @@
// Create the frame index object for this incoming parameter...
int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValue = DAG.getLoad(Op.Val-getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ ArgValue = DAG.getLoad(Op.Val-getValueType(i), Root, FIN, NULL, 0);
ArgValues.push_back(ArgValue);
ArgOffset += ArgIncrement; // Move on to the next argument...
}
@@ -763,8 +762,7 @@
Ops.push_back(DAG.getValueType(RetVT));
Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, Ops[0], Ops.size());
- RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
- DAG.getSrcValue(NULL));
+ RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
Chain = RetVal.getValue(1);
}
@@ -963,8 +961,7 @@
// parameter.
int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValue = DAG.getLoad(Op.Val-getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ ArgValue = DAG.getLoad(Op.Val-getValueType(i), Root, FIN, NULL, 0);
ArgOffset += ArgIncrement; // Move on to the next argument.
}
@@ -1470,11 +1467,10 @@
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
if (ObjectVT == MVT::i64 ObjIntRegs) {
SDOperand ArgValue2 = DAG.getLoad(Op.Val-getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ NULL, 0);
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
} else
-ArgValue = DAG.getLoad(Op.Val-getValueType(i), Root, FIN,
- DAG.getSrcValue(NULL));
+ArgValue = DAG.getLoad(Op.Val-getValueType(i), Root, FIN, NULL, 0);
ArgOffset += ArgIncrement; // Move on to the next argument.
}
@@ -1800,8 +1796,7 @@
Ops.push_back(DAG.getValueType(RetVT));
Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, Ops[0], Ops.size());
- RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
- DAG.getSrcValue(NULL));
+ RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
Chain = RetVal.getValue(1);
}
@@ -1880,8 +1875,7 @@
// Create the frame index
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.112 - 1.113
---
Log message:
More isel time load folding checking for nodes that produce flag values.
See comment in CanBeFoldedBy() for detailed explanation.
---
Diffs of the changes: (+57 -6)
X86ISelDAGToDAG.cpp | 63 +++-
1 files changed, 57 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.112
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.113
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.112 Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Oct 9 20:46:56 2006
@@ -213,7 +213,20 @@
};
}
-static void findNonImmUse(SDNode* Use, SDNode* Def, bool found,
+static SDNode *findFlagUse(SDNode *N) {
+ unsigned FlagResNo = N-getNumValues()-1;
+ for (SDNode::use_iterator I = N-use_begin(), E = N-use_end(); I != E; ++I)
{
+SDNode *User = *I;
+for (unsigned i = 0, e = User-getNumOperands(); i != e; ++i) {
+ SDOperand Op = User-getOperand(i);
+ if (Op.ResNo == FlagResNo)
+return User;
+}
+ }
+ return NULL;
+}
+
+static void findNonImmUse(SDNode* Use, SDNode* Def, SDNode *Ignore, bool
found,
std::setSDNode * Visited) {
if (found ||
Use-getNodeId() Def-getNodeId() ||
@@ -222,8 +235,10 @@
for (unsigned i = 0, e = Use-getNumOperands(); i != e; ++i) {
SDNode *N = Use-getOperand(i).Val;
+if (N == Ignore)
+ continue;
if (N != Def) {
- findNonImmUse(N, Def, found, Visited);
+ findNonImmUse(N, Def, Ignore, found, Visited);
} else {
found = true;
break;
@@ -231,16 +246,27 @@
}
}
-static inline bool isNonImmUse(SDNode* Use, SDNode* Def) {
+static inline bool isNonImmUse(SDNode* Use, SDNode* Def, SDNode *Ignore=NULL) {
std::setSDNode * Visited;
bool found = false;
for (unsigned i = 0, e = Use-getNumOperands(); i != e; ++i) {
SDNode *N = Use-getOperand(i).Val;
-if (N != Def) {
- findNonImmUse(N, Def, found, Visited);
+if (N != Def N != Ignore) {
+ findNonImmUse(N, Def, Ignore, found, Visited);
if (found) break;
}
}
+
+ if (!found Ignore) {
+// We must be checking for reachability between Def and a flag use. Go down
+// recursively if Use also produces a flag.
+MVT::ValueType VT = Use-getValueType(Use-getNumValues()-1);
+if (VT == MVT::Flag !Use-use_empty()) {
+ SDNode *FU = findFlagUse(Use);
+ if (FU)
+return !isNonImmUse(FU, Def, Use);
+}
+ }
return found;
}
@@ -258,7 +284,32 @@
// /[X]
// | ^
// [U]|
- return !FastISel !isNonImmUse(U, N);
+ if (!FastISel !isNonImmUse(U, N)) {
+// If U produces a flag, then it gets (even more) interesting. Since it
+// would have been glued together with its flag use, we need to check if
+// it might reach N:
+//
+// [ N ]
+//^ ^
+//| |
+// [U] \--
+//^ [TF]
+//||
+// \ /
+// [FU]
+//
+// If FU (flag use) indirectly reach N (the load), and U fold N (call it
+// NU), then TF is a predecessor of FU and a successor of NU. But since
+// NU and FU are flagged together, this effectively creates a cycle.
+MVT::ValueType VT = U-getValueType(U-getNumValues()-1);
+if (VT == MVT::Flag !U-use_empty()) {
+ SDNode *FU = findFlagUse(U);
+ if (FU)
+return !isNonImmUse(FU, N, U);
+}
+return true;
+ }
+ return false;
}
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain
operand
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.110 - 1.111
X86InstrSSE.td updated: 1.161 - 1.162
---
Log message:
completely disable folding of loads into scalar sse instructions and provide
a framework for doing it right. This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.
Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.
---
Diffs of the changes: (+61 -14)
X86ISelDAGToDAG.cpp | 25 +
X86InstrSSE.td | 50 --
2 files changed, 61 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.110
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.111
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.110 Fri Sep 29 17:05:10 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Oct 7 16:55:32 2006
@@ -147,6 +147,8 @@
SDOperand Index, SDOperand Disp);
bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
+bool SelectScalarSSELoad(SDOperand N, SDOperand Base, SDOperand Scale,
+ SDOperand Index, SDOperand Disp);
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
@@ -724,6 +726,29 @@
return true;
}
+/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
+/// match a load whose top elements are either undef or zeros. The load flavor
+/// is derived from the type of N, which is either v4f32 or v2f64.
+bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand N, SDOperand Base,
+ SDOperand Scale,
+ SDOperand Index, SDOperand Disp) {
+#if 0
+ if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+if (N.getOperand(0).getOpcode() == ISD::LOAD) {
+ SDOperand LoadAddr = N.getOperand(0).getOperand(0);
+ if (!SelectAddr(LoadAddr, Base, Scale, Index, Disp))
+return false;
+ return true;
+}
+ }
+ // TODO: Also handle the case where we explicitly require zeros in the top
+ // elements. This is a vector shuffle from the zero vector.
+#endif
+
+ return false;
+}
+
+
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal
addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand Base,
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.161
llvm/lib/Target/X86/X86InstrSSE.td:1.162
--- llvm/lib/Target/X86/X86InstrSSE.td:1.161Sat Oct 7 16:17:13 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 16:55:32 2006
@@ -13,6 +13,7 @@
//
//===--===//
+
//===--===//
// SSE specific DAG Nodes.
//===--===//
@@ -32,6 +33,27 @@
def X86pinsrw : SDNodeX86ISD::PINSRW, SDTypeProfile1, 3, [], [];
//===--===//
+// SSE Complex Patterns
+//===--===//
+
+// These are 'extloads' from a scalar to the low element of a vector, zeroing
+// the top elements. These are used for the SSE 'ss' and 'sd' instruction
+// forms.
+def sse_load_f32 : ComplexPatternv4f32, 4, SelectScalarSSELoad, [];
+def sse_load_f64 : ComplexPatternv2f64, 4, SelectScalarSSELoad, [];
+
+def ssmem : Operandv4f32 {
+ let PrintMethod = printf32mem;
+ let NumMIOperands = 4;
+ let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+}
+def sdmem : Operandv2f64 {
+ let PrintMethod = printf64mem;
+ let NumMIOperands = 4;
+ let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+}
+
+//===--===//
// SSE pattern fragments
//===--===//
@@ -185,18 +207,18 @@
def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
!strconcat(OpcodeStr, {$src, $dst|$dst, $src),
[(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
- def m : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+ def m : SSIo, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
!strconcat(OpcodeStr, {$src, $dst|$dst, $src),
- [(set VR128:$dst, (v4f32 (IntId (load addr:$src];
+ [(set VR128:$dst, (v4f32 (IntId sse_load_f32:$src)))];
}
multiclass SD_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
def r : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
!strconcat(OpcodeStr, {$src, $dst|$dst, $src),
[(set
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.109 - 1.110 --- Log message: Not needed. --- Diffs of the changes: (+0 -1) X86ISelDAGToDAG.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.109 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.110 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.109 Sun Sep 17 15:25:45 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Sep 29 17:05:10 2006 @@ -34,7 +34,6 @@ #include llvm/Support/Debug.h #include llvm/Support/MathExtras.h #include llvm/ADT/Statistic.h -#include deque #include iostream #include queue #include set ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.107 - 1.108
---
Log message:
Remove a unnecessary check.
---
Diffs of the changes: (+0 -1)
X86ISelDAGToDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.107
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.108
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.107 Tue Sep 12 23:45:25 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Sep 14 18:55:02 2006
@@ -784,7 +784,6 @@
SDOperand Index, SDOperand Disp) {
if (N.getOpcode() == ISD::LOAD
N.hasOneUse()
- P.Val-isOnlyUse(N.Val)
CanBeFoldedBy(N.Val, P.Val))
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
return false;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.106 - 1.107
---
Log message:
Fix a regression in the 32-bit port from the 64-bit port landing.
We now compile CodeGen/X86/lea-2.ll into:
_test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
leal -5(%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal (,%eax,4), %eax
addl 8(%esp), %eax
addl $4294967291, %eax
ret
---
Diffs of the changes: (+2 -2)
X86ISelDAGToDAG.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.106
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.107
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.106 Tue Sep 12 16:03:39 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 12 23:45:25 2006
@@ -498,7 +498,7 @@
// RIP relative addressing: %rip + 32-bit displacement!
if (AM.isRIPRel) {
if (!AM.ES AM.JT != -1 N.getOpcode() == ISD::Constant) {
- uint64_t Val = castConstantSDNode(N)-getValue();
+ int64_t Val = castConstantSDNode(N)-getSignExtended();
if (isInt32(AM.Disp + Val)) {
AM.Disp += Val;
return false;
@@ -513,7 +513,7 @@
switch (N.getOpcode()) {
default: break;
case ISD::Constant: {
-uint64_t Val = castConstantSDNode(N)-getValue();
+int64_t Val = castConstantSDNode(N)-getSignExtended();
if (isInt32(AM.Disp + Val)) {
AM.Disp += Val;
return false;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.98 - 1.99
---
Log message:
Add an optional pass to preprocess the DAG before x86 isel to allow selecting
more load/mod/store instructions.
---
Diffs of the changes: (+130 -0)
X86ISelDAGToDAG.cpp | 130
1 files changed, 130 insertions(+)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.98
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.99
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.98Sun Aug 27 07:54:01 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Aug 28 15:10:17 2006
@@ -39,6 +39,10 @@
#include set
using namespace llvm;
+#include llvm/Support/CommandLine.h
+static cl::optbool X86ISelPreproc(enable-x86-isel-preprocessing,
cl::Hidden,
+ cl::desc(Enable isel preprocessing on
X86));
+
//===--===//
// Pattern Matcher Implementation
//===--===//
@@ -133,6 +137,7 @@
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
+void InstructionSelectPreprocess(SelectionDAG DAG);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
@@ -232,12 +237,137 @@
return !isNonImmUse(U, N);
}
+/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain
operand
+/// and move load below the TokenFactor. Replace store's chain operand with
+/// load's chain result.
+static void MoveBelowTokenFactor(SelectionDAG DAG, SDOperand Load,
+ SDOperand Store, SDOperand TF) {
+ std::vectorSDOperand Ops;
+ for (unsigned i = 0, e = TF.Val-getNumOperands(); i != e; ++i)
+if (Load.Val == TF.Val-getOperand(i).Val)
+ Ops.push_back(Load.Val-getOperand(0));
+else
+ Ops.push_back(TF.Val-getOperand(i));
+ DAG.UpdateNodeOperands(TF, Ops[0], Ops.size());
+ DAG.UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
+ DAG.UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
+ Store.getOperand(2), Store.getOperand(3));
+}
+
+/// InstructionSelectPreprocess - Preprocess the DAG to allow the instruction
+/// selector to pick more load-modify-store instructions. This is a common
+/// case:
+///
+/// [Load chain]
+/// ^
+/// |
+/// [Load]
+/// ^^
+/// ||
+/// / \-
+/// / |
+/// [TokenFactor] [Op]
+/// ^ ^
+/// | |
+/// \/
+/// \ /
+/// [Store]
+///
+/// The fact the store's chain operand != load's chain will prevent the
+/// (store (op (load))) instruction from being selected. We can transform it
to:
+///
+/// [Load chain]
+/// ^
+/// |
+///[TokenFactor]
+/// ^
+/// |
+/// [Load]
+/// ^^
+/// ||
+/// | \-
+/// | |
+/// | [Op]
+/// | ^
+/// | |
+/// \ /
+///\/
+/// [Store]
+void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG DAG) {
+ for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+ E = DAG.allnodes_end(); I != E; ++I) {
+if (I-getOpcode() != ISD::STORE)
+ continue;
+SDOperand Chain = I-getOperand(0);
+if (Chain.Val-getOpcode() != ISD::TokenFactor)
+ continue;
+
+SDOperand N1 = I-getOperand(1);
+SDOperand N2 = I-getOperand(2);
+if (!N1.hasOneUse())
+ continue;
+
+bool RModW = false;
+SDOperand Load;
+unsigned Opcode = N1.Val-getOpcode();
+switch (Opcode) {
+ case ISD::ADD:
+ case ISD::MUL:
+ case ISD::FADD:
+ case ISD::FMUL:
+ case ISD::AND:
+ case ISD::OR:
+ case ISD::XOR:
+ case ISD::ADDC:
+ case ISD::ADDE: {
+SDOperand N10 = N1.getOperand(0);
+SDOperand N11 = N1.getOperand(1);
+if (N10.Val-getOpcode() == ISD::LOAD)
+ RModW = true;
+else if (N11.Val-getOpcode() == ISD::LOAD) {
+ RModW = true;
+ std::swap(N10, N11);
+}
+RModW = RModW N10.Val-isOperand(Chain.Val) N10.hasOneUse()
+ N10.getOperand(1) == N2;
+if (RModW)
+ Load = N10;
+break;
+ }
+ case ISD::SUB:
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
+ case ISD::ROTL:
+ case ISD::ROTR:
+ case ISD::SUBC:
+ case ISD::SUBE:
+ case X86ISD::SHLD:
+ case X86ISD::SHRD: {
+SDOperand N10 = N1.getOperand(0);
+if (N10.Val-getOpcode() == ISD::LOAD)
+ RModW = N10.Val-isOperand(Chain.Val) N10.hasOneUse()
+N10.getOperand(1)
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.96 - 1.97
---
Log message:
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead.
---
Diffs of the changes: (+4 -4)
X86ISelDAGToDAG.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.96
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.97
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.96Sat Aug 26 03:00:10 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Aug 27 03:14:06 2006
@@ -723,9 +723,9 @@
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
+SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
SDNode *CNode =
- CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
-Tmp2, Tmp3, Chain, InFlag);
+ CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else {
@@ -827,9 +827,9 @@
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
+SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
SDNode *CNode =
- CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
-Tmp2, Tmp3, Chain, InFlag);
+ CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.95 - 1.96 --- Log message: SelectNodeTo now returns a SDNode*. --- Diffs of the changes: (+1 -1) X86ISelDAGToDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.95 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.96 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.95Sat Aug 26 00:34:46 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Aug 26 03:00:10 2006 @@ -658,7 +658,7 @@ } if (C.Val) - return CurDAG-SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val; + return CurDAG-SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C); } // Other cases are handled by auto-generated code. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.93 - 1.94
---
Log message:
Match tblgen changes; clean up.
---
Diffs of the changes: (+34 -79)
X86ISelDAGToDAG.cpp | 113 +++-
1 files changed, 34 insertions(+), 79 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.93
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.94
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.93Wed Aug 16 18:59:00 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Aug 25 20:05:16 2006
@@ -134,13 +134,6 @@
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
-virtual void SelectRootInit() {
- DAGSize = CurDAG-AssignTopologicalOrder(TopOrder);
- unsigned NumBytes = (DAGSize + 7) / 8;
- UnfoldableSet = new unsigned char[NumBytes];
- memset(UnfoldableSet, 0, NumBytes);
-}
-
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand Op,
@@ -185,21 +178,6 @@
/// base register. Return the virtual register that holds this value.
SDOperand getGlobalBaseReg();
-/// UnfoldableSet - An boolean array representing nodes which have been
-/// folded into addressing modes and therefore should not be folded in
-/// another operation.
-unsigned char *UnfoldableSet;
-
-inline void setUnfoldable(SDNode *N) {
- unsigned Id = N-getNodeId();
- UnfoldableSet[Id / 8] |= 1 (Id % 8);
-}
-
-inline bool isUnfoldable(SDNode *N) {
- unsigned Id = N-getNodeId();
- return UnfoldableSet[Id / 8] (1 (Id % 8));
-}
-
#ifndef NDEBUG
unsigned Indent;
#endif
@@ -239,10 +217,6 @@
bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U) {
- // Is it already folded by SelectAddr / SelectLEAAddr?
- if (isUnfoldable(N))
-return false;
-
// If U use can somehow reach N through another path then U can't fold N or
// it will create a cycle. e.g. In the following diagram, U can reach N
// through X. If N is folded into into U, then X is both a predecessor and
@@ -274,7 +248,6 @@
DEBUG(std::cerr = Instruction selection ends:\n);
#endif
- UnfoldableSet = NULL;
DAG.RemoveDeadNodes();
// Emit machine code to BB.
@@ -539,14 +512,6 @@
AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
getAddressOperands(AM, Base, Scale, Index, Disp);
-
- int Id = Base.Val ? Base.Val-getNodeId() : -1;
- if (Id != -1)
-setUnfoldable(Base.Val);
- Id = Index.Val ? Index.Val-getNodeId() : -1;
- if (Id != -1)
-setUnfoldable(Index.Val);
-
return true;
}
@@ -594,14 +559,6 @@
getAddressOperands(AM, Base, Scale, Index, Disp);
return true;
}
-
- int Id = Base.Val ? Base.Val-getNodeId() : -1;
- if (Id != -1)
-setUnfoldable(Base.Val);
- Id = Index.Val ? Index.Val-getNodeId() : -1;
- if (Id != -1)
-setUnfoldable(Index.Val);
-
return false;
}
@@ -702,15 +659,8 @@
CP-getOffset()+Offset);
}
-if (C.Val) {
- if (N.Val-hasOneUse()) {
-return CurDAG-SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val;
- } else {
-SDNode *ResNode = CurDAG-getTargetNode(X86::MOV32ri, MVT::i32, C);
-Result = SDOperand(ResNode, 0);
- return ResNode;
- }
-}
+if (C.Val)
+ return CurDAG-SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val;
}
// Other cases are handled by auto-generated code.
@@ -758,29 +708,30 @@
}
SDOperand Chain;
- if (foldedLoad)
-AddToQueue(Chain, N1.getOperand(0));
- else
+ if (foldedLoad) {
+Chain = N1.getOperand(0);
+AddToISelQueue(Chain);
+ } else
Chain = CurDAG-getEntryNode();
SDOperand InFlag(0, 0);
- AddToQueue(N0, N0);
+ AddToISelQueue(N0);
Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(LoReg, NVT),
N0, InFlag);
InFlag = Chain.getValue(1);
if (foldedLoad) {
-AddToQueue(Tmp0, Tmp0);
-AddToQueue(Tmp1, Tmp1);
-AddToQueue(Tmp2, Tmp2);
-AddToQueue(Tmp3, Tmp3);
+AddToISelQueue(Tmp0);
+AddToISelQueue(Tmp1);
+AddToISelQueue(Tmp2);
+AddToISelQueue(Tmp3);
SDNode *CNode =
CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
Tmp2, Tmp3, Chain, InFlag);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else {
-AddToQueue(N1, N1);
+AddToISelQueue(N1);
InFlag =
SDOperand(CurDAG-getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
@@ -849,13 +800,14 @@
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.91 - 1.92
---
Log message:
SelectNodeTo() may return a SDOperand that is different from the input.
---
Diffs of the changes: (+1 -2)
X86ISelDAGToDAG.cpp |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.91
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.92
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.91Fri Aug 11 04:05:03 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Aug 16 02:30:09 2006
@@ -703,8 +703,7 @@
if (C.Val) {
if (N.Val-hasOneUse()) {
-Result = CurDAG-SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
- return NULL;
+return CurDAG-SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val;
} else {
SDNode *ResNode = CurDAG-getTargetNode(X86::MOV32ri, MVT::i32, C);
Result = SDOperand(ResNode, 0);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.92 - 1.93
---
Log message:
Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match
tablegen.
---
Diffs of the changes: (+2 -1)
X86ISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.92
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.93
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.92Wed Aug 16 02:30:09 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Aug 16 18:59:00 2006
@@ -610,7 +610,8 @@
SDOperand Index, SDOperand Disp) {
if (N.getOpcode() == ISD::LOAD
N.hasOneUse()
- !CanBeFoldedBy(N.Val, P.Val))
+ P.Val-isOnlyUse(N.Val)
+ CanBeFoldedBy(N.Val, P.Val))
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
return false;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.90 - 1.91
X86ISelLowering.cpp updated: 1.243 - 1.244
---
Log message:
Match tablegen changes.
---
Diffs of the changes: (+38 -20)
X86ISelDAGToDAG.cpp | 26 ++
X86ISelLowering.cpp | 32
2 files changed, 38 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.90
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.91
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.90Mon Aug 7 19:31:00 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Aug 11 04:05:03 2006
@@ -123,7 +123,7 @@
#include X86GenDAGISel.inc
private:
-void Select(SDOperand Result, SDOperand N);
+SDNode *Select(SDOperand Result, SDOperand N);
bool MatchAddress(SDOperand N, X86ISelAddressMode AM, bool isRoot = true);
bool SelectAddr(SDOperand N, SDOperand Base, SDOperand Scale,
@@ -646,7 +646,7 @@
return FindCallStartFromCall(Node-getOperand(0).Val);
}
-void X86DAGToDAGISel::Select(SDOperand Result, SDOperand N) {
+SDNode *X86DAGToDAGISel::Select(SDOperand Result, SDOperand N) {
SDNode *Node = N.Val;
MVT::ValueType NVT = Node-getValueType(0);
unsigned Opc, MOpc;
@@ -669,15 +669,14 @@
DEBUG(std::cerr \n);
Indent -= 2;
#endif
-return; // Already selected.
+return NULL; // Already selected.
}
switch (Opcode) {
default: break;
case X86ISD::GlobalBaseReg:
Result = getGlobalBaseReg();
- ReplaceUses(N, Result);
- return;
+ return Result.Val;
case ISD::ADD: {
// Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
@@ -705,12 +704,12 @@
if (C.Val) {
if (N.Val-hasOneUse()) {
Result = CurDAG-SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
+ return NULL;
} else {
SDNode *ResNode = CurDAG-getTargetNode(X86::MOV32ri, MVT::i32, C);
Result = SDOperand(ResNode, 0);
-ReplaceUses(N, Result);
+ return ResNode;
}
- return;
}
}
@@ -798,7 +797,7 @@
DEBUG(std::cerr \n);
Indent -= 2;
#endif
- return;
+ return NULL;
}
case ISD::SDIV:
@@ -902,7 +901,8 @@
DEBUG(std::cerr \n);
Indent -= 2;
#endif
- return;
+
+ return NULL;
}
case ISD::TRUNCATE: {
@@ -927,7 +927,6 @@
AddToQueue(Tmp0, Node-getOperand(0));
Tmp1 = SDOperand(CurDAG-getTargetNode(Opc, VT, Tmp0), 0);
Result = SDOperand(CurDAG-getTargetNode(Opc2, NVT, Tmp1), 0);
-ReplaceUses(N, Result);
#ifndef NDEBUG
DEBUG(std::cerr std::string(Indent-2, ' '));
@@ -936,14 +935,15 @@
DEBUG(std::cerr \n);
Indent -= 2;
#endif
-return;
+return Result.Val;
}
break;
}
}
- SelectCode(Result, N);
+ SDNode *ResNode = SelectCode(Result, N);
+
#ifndef NDEBUG
DEBUG(std::cerr std::string(Indent-2, ' '));
DEBUG(std::cerr = );
@@ -951,6 +951,8 @@
DEBUG(std::cerr \n);
Indent -= 2;
#endif
+
+ return ResNode;
}
bool X86DAGToDAGISel::
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.243
llvm/lib/Target/X86/X86ISelLowering.cpp:1.244
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.243 Fri Aug 11 02:35:45 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Aug 11 04:05:03 2006
@@ -2992,9 +2992,14 @@
}
Constant *CS = ConstantStruct::get(CV);
SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
- SDOperand Mask
-= DAG.getNode(X86ISD::LOAD_PACK,
- VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+ std::vectorMVT::ValueType Tys;
+ Tys.push_back(VT);
+ Tys.push_back(MVT::Other);
+ SmallVectorSDOperand, 3 Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(CPIdx);
+ Ops.push_back(DAG.getSrcValue(NULL));
+ SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, Ops[0], Ops.size());
return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
}
@@ -3013,8 +3018,14 @@
}
Constant *CS = ConstantStruct::get(CV);
SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
- SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK,
- VT, DAG.getEntryNode(), CPIdx,
DAG.getSrcValue(NULL));
+ std::vectorMVT::ValueType Tys;
+ Tys.push_back(VT);
+ Tys.push_back(MVT::Other);
+ SmallVectorSDOperand, 3 Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(CPIdx);
+ Ops.push_back(DAG.getSrcValue(NULL));
+ SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, Ops[0], Ops.size());
return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
}
@@ -4121,10 +4132,15 @@
Base-getOperand(2));
else {
// Just use movups, it's shorter.
+std::vectorMVT::ValueType Tys;
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.88 - 1.89
---
Log message:
Match tablegen isel changes.
---
Diffs of the changes: (+54 -101)
X86ISelDAGToDAG.cpp | 155 ++--
1 files changed, 54 insertions(+), 101 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.88
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.89
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.88Wed Aug 2 17:01:32 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Aug 7 17:28:20 2006
@@ -12,7 +12,7 @@
//
//===--===//
-#define DEBUG_TYPE isel
+#define DEBUG_TYPE x86-isel
#include X86.h
#include X86InstrBuilder.h
#include X86ISelLowering.h
@@ -35,6 +35,7 @@
#include llvm/ADT/Statistic.h
#include deque
#include iostream
+#include queue
#include set
using namespace llvm;
@@ -99,7 +100,7 @@
: SelectionDAGISel(X86Lowering),
X86Lowering(*TM.getTargetLowering()),
Subtarget(TM.getSubtargetX86Subtarget()),
-DAGSize(0), ReachabilityMatrix(NULL), ReachMatrixRange(NULL) {}
+ReachabilityMatrix(NULL) {}
virtual bool runOnFunction(Function Fn) {
// Make sure we re-emit a set of the global base reg if necessary
@@ -123,7 +124,7 @@
#include X86GenDAGISel.inc
private:
-void DetermineReachability(SDNode *f, SDNode *t);
+void DetermineReachability();
void Select(SDOperand Result, SDOperand N);
@@ -135,6 +136,18 @@
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
+
+virtual void SelectRootInit() {
+ DAGSize = CurDAG-AssignTopologicalOrder(TopOrder);
+ unsigned NumBytes = (DAGSize + 7) / 8;
+ UnfoldableSet = new unsigned char[NumBytes];
+ memset(UnfoldableSet, 0, NumBytes);
+ unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
+ ReachabilityMatrix = new unsigned char[RMSize];
+ memset(ReachabilityMatrix, 0, RMSize);
+ DetermineReachability();
+}
+
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand Op,
@@ -179,22 +192,10 @@
/// base register. Return the virtual register that holds this value.
SDOperand getGlobalBaseReg();
-/// DAGSize - Number of nodes in the DAG.
-///
-unsigned DAGSize;
-
-/// TopOrder - Topological ordering of all nodes in the DAG.
-///
-std::vectorSDNode* TopOrder;
-
/// ReachabilityMatrix - A N x N matrix representing all pairs reachability
/// information. One bit per potential edge.
unsigned char *ReachabilityMatrix;
-/// ReachMatrixRange - The range of reachability information available for
-/// the particular source node.
-unsigned *ReachMatrixRange;
-
inline void setReachable(SDNode *f, SDNode *t) {
unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
ReachabilityMatrix[Idx / 8] |= 1 (Idx % 8);
@@ -243,7 +244,6 @@
// /[X]
// | ^
// [U]|
- DetermineReachability(U, N);
assert(isReachable(U, N) Attempting to fold a non-operand node?);
for (SDNode::op_iterator I = U-op_begin(), E = U-op_end(); I != E; ++I) {
SDNode *P = I-Val;
@@ -255,23 +255,15 @@
/// DetermineReachability - Determine reachability between all pairs of nodes
/// between f and t in topological order.
-void X86DAGToDAGISel::DetermineReachability(SDNode *f, SDNode *t) {
- unsigned Orderf = f-getNodeId();
- unsigned Ordert = t-getNodeId();
- unsigned Range = ReachMatrixRange[Orderf];
- if (Range = Ordert)
-return;
- if (Range Orderf)
-Range = Orderf;
-
- for (unsigned i = Range; i Ordert; ++i) {
+void X86DAGToDAGISel::DetermineReachability() {
+ for (unsigned i = 0; i DAGSize; ++i) {
SDNode *N = TopOrder[i];
setReachable(N, N);
// If N is a leaf node, there is nothing more to do.
if (N-getNumOperands() == 0)
continue;
-for (unsigned i2 = Range; ; ++i2) {
+for (unsigned i2 = 0; ; ++i2) {
SDNode *M = TopOrder[i2];
if (isReachable(M, N)) {
// Update reachability from M to N's operands.
@@ -284,8 +276,6 @@
if (M == N) break;
}
}
-
- ReachMatrixRange[Orderf] = Ordert;
}
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
@@ -294,16 +284,6 @@
DEBUG(BB-dump());
MachineFunction::iterator FirstMBB = BB;
- DAGSize = DAG.AssignTopologicalOrder(TopOrder);
- unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
- ReachabilityMatrix = new unsigned char[RMSize];
- memset(ReachabilityMatrix, 0, RMSize);
- ReachMatrixRange = new unsigned[DAGSize];
- memset(ReachMatrixRange, 0, DAGSize * sizeof(unsigned));
- unsigned NumBytes =
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.89 - 1.90
---
Log message:
Eliminate reachability matrix. It has to be calculated before any instruction
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.
---
Diffs of the changes: (+34 -57)
X86ISelDAGToDAG.cpp | 91 +++-
1 files changed, 34 insertions(+), 57 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.89
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.90
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.89Mon Aug 7 17:28:20 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Aug 7 19:31:00 2006
@@ -99,8 +99,7 @@
X86DAGToDAGISel(X86TargetMachine TM)
: SelectionDAGISel(X86Lowering),
X86Lowering(*TM.getTargetLowering()),
-Subtarget(TM.getSubtargetX86Subtarget()),
-ReachabilityMatrix(NULL) {}
+Subtarget(TM.getSubtargetX86Subtarget()) {}
virtual bool runOnFunction(Function Fn) {
// Make sure we re-emit a set of the global base reg if necessary
@@ -124,8 +123,6 @@
#include X86GenDAGISel.inc
private:
-void DetermineReachability();
-
void Select(SDOperand Result, SDOperand N);
bool MatchAddress(SDOperand N, X86ISelAddressMode AM, bool isRoot = true);
@@ -142,10 +139,6 @@
unsigned NumBytes = (DAGSize + 7) / 8;
UnfoldableSet = new unsigned char[NumBytes];
memset(UnfoldableSet, 0, NumBytes);
- unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
- ReachabilityMatrix = new unsigned char[RMSize];
- memset(ReachabilityMatrix, 0, RMSize);
- DetermineReachability();
}
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
@@ -192,20 +185,6 @@
/// base register. Return the virtual register that holds this value.
SDOperand getGlobalBaseReg();
-/// ReachabilityMatrix - A N x N matrix representing all pairs reachability
-/// information. One bit per potential edge.
-unsigned char *ReachabilityMatrix;
-
-inline void setReachable(SDNode *f, SDNode *t) {
- unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- ReachabilityMatrix[Idx / 8] |= 1 (Idx % 8);
-}
-
-inline bool isReachable(SDNode *f, SDNode *t) {
- unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- return ReachabilityMatrix[Idx / 8] (1 (Idx % 8));
-}
-
/// UnfoldableSet - An boolean array representing nodes which have been
/// folded into addressing modes and therefore should not be folded in
/// another operation.
@@ -227,6 +206,38 @@
};
}
+static void findNonImmUse(SDNode* Use, SDNode* Def, bool found,
+ std::setSDNode * Visited) {
+ if (found ||
+ Use-getNodeId() Def-getNodeId() ||
+ !Visited.insert(Use).second)
+return;
+
+ for (unsigned i = 0, e = Use-getNumOperands(); i != e; ++i) {
+SDNode *N = Use-getOperand(i).Val;
+if (N != Def) {
+ findNonImmUse(N, Def, found, Visited);
+} else {
+ found = true;
+ break;
+}
+ }
+}
+
+static inline bool isNonImmUse(SDNode* Use, SDNode* Def) {
+ std::setSDNode * Visited;
+ bool found = false;
+ for (unsigned i = 0, e = Use-getNumOperands(); i != e; ++i) {
+SDNode *N = Use-getOperand(i).Val;
+if (N != Def) {
+ findNonImmUse(N, Def, found, Visited);
+ if (found) break;
+}
+ }
+ return found;
+}
+
+
bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U) {
// Is it already folded by SelectAddr / SelectLEAAddr?
if (isUnfoldable(N))
@@ -244,38 +255,7 @@
// /[X]
// | ^
// [U]|
- assert(isReachable(U, N) Attempting to fold a non-operand node?);
- for (SDNode::op_iterator I = U-op_begin(), E = U-op_end(); I != E; ++I) {
-SDNode *P = I-Val;
-if (P != N isReachable(P, N))
- return false;
- }
- return true;
-}
-
-/// DetermineReachability - Determine reachability between all pairs of nodes
-/// between f and t in topological order.
-void X86DAGToDAGISel::DetermineReachability() {
- for (unsigned i = 0; i DAGSize; ++i) {
-SDNode *N = TopOrder[i];
-setReachable(N, N);
-// If N is a leaf node, there is nothing more to do.
-if (N-getNumOperands() == 0)
- continue;
-
-for (unsigned i2 = 0; ; ++i2) {
- SDNode *M = TopOrder[i2];
- if (isReachable(M, N)) {
-// Update reachability from M to N's operands.
-for (SDNode::op_iterator I = N-op_begin(),E = N-op_end(); I !=
E;++I){
- SDNode *P = I-Val;
- if (P-getNodeId() = 0)
-setReachable(M, P);
-}
- }
- if (M == N) break;
-}
- }
+ return !isNonImmUse(U, N);
}
/// InstructionSelectBasicBlock - This callback is invoked by
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.86 - 1.87
---
Log message:
Use of vectorbool causes some horrendous compile time regression (2x)!
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.
---
Diffs of the changes: (+26 -13)
X86ISelDAGToDAG.cpp | 39 ++-
1 files changed, 26 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.86
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.87
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.86Tue Aug 1 03:17:22 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Aug 2 04:18:33 2006
@@ -99,7 +99,7 @@
: SelectionDAGISel(X86Lowering),
X86Lowering(*TM.getTargetLowering()),
Subtarget(TM.getSubtargetX86Subtarget()),
-DAGSize(0) {}
+DAGSize(0), ReachabilityMatrix(NULL), ReachMatrixRange(NULL) {}
virtual bool runOnFunction(Function Fn) {
// Make sure we re-emit a set of the global base reg if necessary
@@ -189,33 +189,35 @@
/// ReachabilityMatrix - A N x N matrix representing all pairs reachability
/// information. One bit per potential edge.
-std::vectorbool ReachabilityMatrix;
+unsigned char *ReachabilityMatrix;
-/// RMRange - The range of reachability information available for the
-/// particular source node.
-std::vectorunsigned ReachMatrixRange;
+/// ReachMatrixRange - The range of reachability information available for
+/// the particular source node.
+unsigned *ReachMatrixRange;
inline void setReachable(SDNode *f, SDNode *t) {
unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- ReachabilityMatrix[Idx] = true;
+ ReachabilityMatrix[Idx / 8] |= 1 (Idx % 8);
}
inline bool isReachable(SDNode *f, SDNode *t) {
unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- return ReachabilityMatrix[Idx];
+ return ReachabilityMatrix[Idx / 8] (1 (Idx % 8));
}
/// UnfoldableSet - An boolean array representing nodes which have been
/// folded into addressing modes and therefore should not be folded in
/// another operation.
-std::vectorbool UnfoldableSet;
+unsigned char *UnfoldableSet;
inline void setUnfoldable(SDNode *N) {
- UnfoldableSet[N-getNodeId()] = true;
+ unsigned Id = N-getNodeId();
+ UnfoldableSet[Id / 8] |= 1 (Id % 8);
}
inline bool isUnfoldable(SDNode *N) {
- return UnfoldableSet[N-getNodeId()];
+ unsigned Id = N-getNodeId();
+ return UnfoldableSet[Id / 8] (1 (Id % 8));
}
#ifndef NDEBUG
@@ -291,9 +293,14 @@
TopOrder = DAG.AssignTopologicalOrder();
DAGSize = TopOrder.size();
- ReachabilityMatrix.assign(DAGSize*DAGSize, false);
- ReachMatrixRange.assign(DAGSize, 0);
- UnfoldableSet.assign(DAGSize, false);
+ unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
+ ReachabilityMatrix = new unsigned char[RMSize];
+ memset(ReachabilityMatrix, 0, RMSize);
+ ReachMatrixRange = new unsigned[DAGSize];
+ memset(ReachMatrixRange, 0, DAGSize * sizeof(unsigned));
+ unsigned NumBytes = (DAGSize + 7) / 8;
+ UnfoldableSet = new unsigned char[NumBytes];
+ memset(UnfoldableSet, 0, NumBytes);
// Codegen the basic block.
#ifndef NDEBUG
@@ -305,6 +312,12 @@
DEBUG(std::cerr = Instruction selection ends:\n);
#endif
+ delete[] ReachabilityMatrix;
+ delete[] ReachMatrixRange;
+ delete[] UnfoldableSet;
+ ReachabilityMatrix = NULL;
+ ReachMatrixRange = NULL;
+ UnfoldableSet = NULL;
CodeGenMap.clear();
HandleMap.clear();
ReplaceMap.clear();
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.87 - 1.88
---
Log message:
Reflect change to AssignTopologicalOrder().
---
Diffs of the changes: (+8 -5)
X86ISelDAGToDAG.cpp | 13 -
1 files changed, 8 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.87
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.88
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.87Wed Aug 2 04:18:33 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Aug 2 17:01:32 2006
@@ -271,12 +271,15 @@
if (N-getNumOperands() == 0)
continue;
-for (unsigned i2 = Orderf; ; ++i2) {
+for (unsigned i2 = Range; ; ++i2) {
SDNode *M = TopOrder[i2];
if (isReachable(M, N)) {
// Update reachability from M to N's operands.
-for (SDNode::op_iterator I = N-op_begin(), E = N-op_end(); I !=
E;++I)
- setReachable(M, I-Val);
+for (SDNode::op_iterator I = N-op_begin(),E = N-op_end(); I !=
E;++I){
+ SDNode *P = I-Val;
+ if (P-getNodeId() = 0)
+setReachable(M, P);
+}
}
if (M == N) break;
}
@@ -291,8 +294,7 @@
DEBUG(BB-dump());
MachineFunction::iterator FirstMBB = BB;
- TopOrder = DAG.AssignTopologicalOrder();
- DAGSize = TopOrder.size();
+ DAGSize = DAG.AssignTopologicalOrder(TopOrder);
unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
ReachabilityMatrix = new unsigned char[RMSize];
memset(ReachabilityMatrix, 0, RMSize);
@@ -318,6 +320,7 @@
ReachabilityMatrix = NULL;
ReachMatrixRange = NULL;
UnfoldableSet = NULL;
+ TopOrder.clear();
CodeGenMap.clear();
HandleMap.clear();
ReplaceMap.clear();
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.85 - 1.86
---
Log message:
Factor topological order code to SelectionDAG. Clean up.
---
Diffs of the changes: (+23 -87)
X86ISelDAGToDAG.cpp | 110 ++--
1 files changed, 23 insertions(+), 87 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.85
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.86
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.85Fri Jul 28 01:33:41 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Aug 1 03:17:22 2006
@@ -99,8 +99,7 @@
: SelectionDAGISel(X86Lowering),
X86Lowering(*TM.getTargetLowering()),
Subtarget(TM.getSubtargetX86Subtarget()),
-DAGSize(0), TopOrder(NULL), IdToOrder(NULL),
-RMRange(NULL), ReachabilityMatrix(NULL) {}
+DAGSize(0) {}
virtual bool runOnFunction(Function Fn) {
// Make sure we re-emit a set of the global base reg if necessary
@@ -124,7 +123,6 @@
#include X86GenDAGISel.inc
private:
-void DetermineTopologicalOrdering();
void DetermineReachability(SDNode *f, SDNode *t);
void Select(SDOperand Result, SDOperand N);
@@ -187,43 +185,37 @@
/// TopOrder - Topological ordering of all nodes in the DAG.
///
-SDNode* *TopOrder;
+std::vectorSDNode* TopOrder;
-/// IdToOrder - Node id to topological order map.
-///
-unsigned *IdToOrder;
+/// ReachabilityMatrix - A N x N matrix representing all pairs reachability
+/// information. One bit per potential edge.
+std::vectorbool ReachabilityMatrix;
-/// RMRange - The range of reachibility information available for the
+/// RMRange - The range of reachability information available for the
/// particular source node.
-unsigned *RMRange;
-
-/// ReachabilityMatrix - A N x N matrix representing all pairs reachibility
-/// information. One bit per potential edge.
-unsigned char *ReachabilityMatrix;
+std::vectorunsigned ReachMatrixRange;
inline void setReachable(SDNode *f, SDNode *t) {
unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- ReachabilityMatrix[Idx / 8] |= 1 (Idx % 8);
+ ReachabilityMatrix[Idx] = true;
}
inline bool isReachable(SDNode *f, SDNode *t) {
unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- return ReachabilityMatrix[Idx / 8] (1 (Idx % 8));
+ return ReachabilityMatrix[Idx];
}
/// UnfoldableSet - An boolean array representing nodes which have been
/// folded into addressing modes and therefore should not be folded in
/// another operation.
-unsigned char *UnfoldableSet;
+std::vectorbool UnfoldableSet;
inline void setUnfoldable(SDNode *N) {
- unsigned Id = N-getNodeId();
- UnfoldableSet[Id / 8] |= 1 (Id % 8);
+ UnfoldableSet[N-getNodeId()] = true;
}
inline bool isUnfoldable(SDNode *N) {
- unsigned Id = N-getNodeId();
- return UnfoldableSet[Id / 8] (1 (Id % 8));
+ return UnfoldableSet[N-getNodeId()];
}
#ifndef NDEBUG
@@ -259,58 +251,12 @@
return true;
}
-/// DetermineTopologicalOrdering - Determine topological ordering of the nodes
-/// in the DAG.
-void X86DAGToDAGISel::DetermineTopologicalOrdering() {
- TopOrder = new SDNode*[DAGSize];
- IdToOrder = new unsigned[DAGSize];
- memset(IdToOrder, 0, DAGSize * sizeof(unsigned));
- RMRange = new unsigned[DAGSize];
- memset(RMRange, 0, DAGSize * sizeof(unsigned));
-
- std::vectorunsigned InDegree(DAGSize);
- std::dequeSDNode* Sources;
- for (SelectionDAG::allnodes_iterator I = CurDAG-allnodes_begin(),
- E = CurDAG-allnodes_end(); I != E; ++I) {
-SDNode *N = I;
-unsigned Degree = N-use_size();
-InDegree[N-getNodeId()] = Degree;
-if (Degree == 0)
- Sources.push_back(I);
- }
-
- unsigned Order = 0;
- while (!Sources.empty()) {
-SDNode *N = Sources.front();
-Sources.pop_front();
-TopOrder[Order] = N;
-IdToOrder[N-getNodeId()] = Order;
-Order++;
-for (SDNode::op_iterator I = N-op_begin(), E = N-op_end(); I != E; ++I) {
- SDNode *P = I-Val;
- int PId = P-getNodeId();
- unsigned Degree = InDegree[PId] - 1;
- if (Degree == 0)
-Sources.push_back(P);
- InDegree[PId] = Degree;
-}
- }
-}
-
-/// DetermineReachability - Determine reachibility between all pairs of nodes
+/// DetermineReachability - Determine reachability between all pairs of nodes
/// between f and t in topological order.
void X86DAGToDAGISel::DetermineReachability(SDNode *f, SDNode *t) {
- if (!ReachabilityMatrix) {
-unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
-ReachabilityMatrix = new unsigned char[RMSize];
-memset(ReachabilityMatrix, 0, RMSize);
- }
-
- int Idf = f-getNodeId();
- int Idt = t-getNodeId();
- unsigned Orderf = IdToOrder[Idf];
- unsigned Ordert = IdToOrder[Idt];
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.83 - 1.84
---
Log message:
Some clean up.
---
Diffs of the changes: (+8 -6)
X86ISelDAGToDAG.cpp | 14 --
1 files changed, 8 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.83
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.84
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.83Thu Jul 27 20:03:48 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jul 28 01:05:06 2006
@@ -33,8 +33,8 @@
#include llvm/Support/Debug.h
#include llvm/Support/Visibility.h
#include llvm/ADT/Statistic.h
+#include deque
#include iostream
-#include list
#include set
using namespace llvm;
@@ -125,7 +125,7 @@
private:
void DetermineTopologicalOrdering();
-void DeterminReachibility(SDNode *f, SDNode *t);
+void DetermineReachibility(SDNode *f, SDNode *t);
void Select(SDOperand Result, SDOperand N);
@@ -239,7 +239,7 @@
// If U use can somehow reach N through another path then U can't fold N or
// it will create a cycle. e.g. In the following diagram, U can reach N
- // through X. If N is foled into into U, then X is both a predecessor and
+ // through X. If N is foledd into into U, then X is both a predecessor and
// a successor of U.
//
// [ N ]
@@ -249,7 +249,7 @@
// /[X]
// | ^
// [U]|
- DeterminReachibility(U, N);
+ DetermineReachibility(U, N);
assert(isReachable(U, N) Attempting to fold a non-operand node?);
for (SDNode::op_iterator I = U-op_begin(), E = U-op_end(); I != E; ++I) {
SDNode *P = I-Val;
@@ -269,7 +269,7 @@
memset(RMRange, 0, DAGSize * sizeof(unsigned));
std::vectorunsigned InDegree(DAGSize);
- std::listSDNode* Sources;
+ std::dequeSDNode* Sources;
for (SelectionDAG::allnodes_iterator I = CurDAG-allnodes_begin(),
E = CurDAG-allnodes_end(); I != E; ++I) {
SDNode *N = I;
@@ -297,7 +297,9 @@
}
}
-void X86DAGToDAGISel::DeterminReachibility(SDNode *f, SDNode *t) {
+/// DetermineReachibility - Determine reachibility between all pairs of nodes
+/// between f and t in topological order.
+void X86DAGToDAGISel::DetermineReachibility(SDNode *f, SDNode *t) {
if (!ReachibilityMatrix) {
unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
ReachibilityMatrix = new unsigned char[RMSize];
___
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
On Fri, 2006-07-28 at 01:05 -0500, Evan Cheng wrote: +void DetermineReachibility(SDNode *f, SDNode *t); Hate to be pedantic about this, but its Reachability (a between h and b) Reid. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.84 - 1.85
---
Log message:
Can't spell.
---
Diffs of the changes: (+15 -15)
X86ISelDAGToDAG.cpp | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.84
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.85
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.84Fri Jul 28 01:05:06 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jul 28 01:33:41 2006
@@ -100,7 +100,7 @@
X86Lowering(*TM.getTargetLowering()),
Subtarget(TM.getSubtargetX86Subtarget()),
DAGSize(0), TopOrder(NULL), IdToOrder(NULL),
-RMRange(NULL), ReachibilityMatrix(NULL) {}
+RMRange(NULL), ReachabilityMatrix(NULL) {}
virtual bool runOnFunction(Function Fn) {
// Make sure we re-emit a set of the global base reg if necessary
@@ -125,7 +125,7 @@
private:
void DetermineTopologicalOrdering();
-void DetermineReachibility(SDNode *f, SDNode *t);
+void DetermineReachability(SDNode *f, SDNode *t);
void Select(SDOperand Result, SDOperand N);
@@ -197,18 +197,18 @@
/// particular source node.
unsigned *RMRange;
-/// ReachibilityMatrix - A N x N matrix representing all pairs reachibility
+/// ReachabilityMatrix - A N x N matrix representing all pairs reachibility
/// information. One bit per potential edge.
-unsigned char *ReachibilityMatrix;
+unsigned char *ReachabilityMatrix;
inline void setReachable(SDNode *f, SDNode *t) {
unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- ReachibilityMatrix[Idx / 8] |= 1 (Idx % 8);
+ ReachabilityMatrix[Idx / 8] |= 1 (Idx % 8);
}
inline bool isReachable(SDNode *f, SDNode *t) {
unsigned Idx = f-getNodeId() * DAGSize + t-getNodeId();
- return ReachibilityMatrix[Idx / 8] (1 (Idx % 8));
+ return ReachabilityMatrix[Idx / 8] (1 (Idx % 8));
}
/// UnfoldableSet - An boolean array representing nodes which have been
@@ -239,7 +239,7 @@
// If U use can somehow reach N through another path then U can't fold N or
// it will create a cycle. e.g. In the following diagram, U can reach N
- // through X. If N is foledd into into U, then X is both a predecessor and
+ // through X. If N is folded into into U, then X is both a predecessor and
// a successor of U.
//
// [ N ]
@@ -249,7 +249,7 @@
// /[X]
// | ^
// [U]|
- DetermineReachibility(U, N);
+ DetermineReachability(U, N);
assert(isReachable(U, N) Attempting to fold a non-operand node?);
for (SDNode::op_iterator I = U-op_begin(), E = U-op_end(); I != E; ++I) {
SDNode *P = I-Val;
@@ -297,13 +297,13 @@
}
}
-/// DetermineReachibility - Determine reachibility between all pairs of nodes
+/// DetermineReachability - Determine reachibility between all pairs of nodes
/// between f and t in topological order.
-void X86DAGToDAGISel::DetermineReachibility(SDNode *f, SDNode *t) {
- if (!ReachibilityMatrix) {
+void X86DAGToDAGISel::DetermineReachability(SDNode *f, SDNode *t) {
+ if (!ReachabilityMatrix) {
unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
-ReachibilityMatrix = new unsigned char[RMSize];
-memset(ReachibilityMatrix, 0, RMSize);
+ReachabilityMatrix = new unsigned char[RMSize];
+memset(ReachabilityMatrix, 0, RMSize);
}
int Idf = f-getNodeId();
@@ -360,12 +360,12 @@
DEBUG(std::cerr = Instruction selection ends:\n);
#endif
- delete[] ReachibilityMatrix;
+ delete[] ReachabilityMatrix;
delete[] TopOrder;
delete[] IdToOrder;
delete[] RMRange;
delete[] UnfoldableSet;
- ReachibilityMatrix = NULL;
+ ReachabilityMatrix = NULL;
TopOrder = NULL;
IdToOrder = RMRange = NULL;
UnfoldableSet = NULL;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.76 - 1.77 --- Log message: isNonImmUse is replaced by IsFoldableBy --- Diffs of the changes: (+1 -1) X86ISelDAGToDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.76 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.77 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.76Thu Jul 27 11:44:36 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 27 16:19:10 2006 @@ -640,7 +640,7 @@ if (N.getOpcode() == ISD::LOAD N.hasOneUse() !CodeGenMap.count(N.getValue(0)) - (P.getNumOperands() == 1 || !isNonImmUse(P.Val, N.Val))) + !IsFoldableBy(N.Val, P.Val)) return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp); return false; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.77 - 1.78
---
Log message:
Calculate the portion of reachbility matrix on demand.
---
Diffs of the changes: (+42 -11)
X86ISelDAGToDAG.cpp | 53 +---
1 files changed, 42 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.77
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.78
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.77Thu Jul 27 16:19:10 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 27 17:10:00 2006
@@ -124,7 +124,7 @@
private:
void DetermineTopologicalOrdering();
-void DeterminReachibility();
+void DeterminReachibility(SDNode *f, SDNode *t);
void Select(SDOperand Result, SDOperand N);
@@ -186,7 +186,15 @@
/// TopOrder - Topological ordering of all nodes in the DAG.
///
-std::vectorSDNode* TopOrder;
+SDNode* *TopOrder;
+
+/// IdToOrder - Node id to topological order map.
+///
+unsigned *IdToOrder;
+
+/// RMRange - The range of reachibility information available for the
+/// particular source node.
+unsigned *RMRange;
/// ReachibilityMatrix - A N x N matrix representing all pairs reachibility
/// information. One bit per potential edge.
@@ -221,8 +229,7 @@
// /[X]
// | ^
// [U]|
- if (!ReachibilityMatrix)
-DeterminReachibility();
+ DeterminReachibility(U, N);
assert(isReachable(U, N) Attempting to fold a non-operand node?);
for (SDNode::op_iterator I = U-op_begin(), E = U-op_end(); I != E; ++I) {
SDNode *P = I-Val;
@@ -236,7 +243,11 @@
/// in the DAG.
void X86DAGToDAGISel::DetermineTopologicalOrdering() {
DAGSize = CurDAG-AssignNodeIds();
- TopOrder.reserve(DAGSize);
+ TopOrder = new SDNode*[DAGSize];
+ IdToOrder = new unsigned[DAGSize];
+ memset(IdToOrder, 0, DAGSize * sizeof(unsigned));
+ RMRange = new unsigned[DAGSize];
+ memset(RMRange, 0, DAGSize * sizeof(unsigned));
std::vectorunsigned InDegree(DAGSize);
std::listSDNode* Sources;
@@ -254,6 +265,7 @@
SDNode *N = Sources.front();
Sources.pop_front();
TopOrder[Order] = N;
+IdToOrder[N-getNodeId()] = Order;
Order++;
for (SDNode::op_iterator I = N-op_begin(), E = N-op_end(); I != E; ++I) {
SDNode *P = I-Val;
@@ -266,19 +278,31 @@
}
}
-void X86DAGToDAGISel::DeterminReachibility() {
- DetermineTopologicalOrdering();
- ReachibilityMatrix = new unsigned char[DAGSize * DAGSize];
- memset(ReachibilityMatrix, 0, DAGSize * DAGSize * sizeof(unsigned char));
+void X86DAGToDAGISel::DeterminReachibility(SDNode *f, SDNode *t) {
+ if (!ReachibilityMatrix) {
+DetermineTopologicalOrdering();
+ReachibilityMatrix = new unsigned char[DAGSize * DAGSize];
+memset(ReachibilityMatrix, 0, DAGSize * DAGSize * sizeof(unsigned char));
+ }
- for (unsigned i = 0; i DAGSize; ++i) {
+ int Idf = f-getNodeId();
+ int Idt = t-getNodeId();
+ unsigned Orderf = IdToOrder[Idf];
+ unsigned Ordert = IdToOrder[Idt];
+ unsigned Range = RMRange[Idf];
+ if (Range = Ordert)
+return;
+ if (Range Orderf)
+Range = Orderf;
+
+ for (unsigned i = Range; i Ordert; ++i) {
SDNode *N = TopOrder[i];
setReachable(N, N);
// If N is a leaf node, there is nothing more to do.
if (N-getNumOperands() == 0)
continue;
-for (unsigned i2 = 0; ; ++i2) {
+for (unsigned i2 = Orderf; ; ++i2) {
SDNode *M = TopOrder[i2];
if (isReachable(M, N)) {
// Update reachibility from M to N's operands.
@@ -288,6 +312,8 @@
if (M == N) break;
}
}
+
+ RMRange[Idf] = Ordert;
}
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
@@ -308,7 +334,12 @@
#endif
if (ReachibilityMatrix) {
delete[] ReachibilityMatrix;
+delete[] TopOrder;
+delete[] IdToOrder;
+delete[] RMRange;
ReachibilityMatrix = NULL;
+TopOrder = NULL;
+IdToOrder = RMRange = NULL;
}
CodeGenMap.clear();
HandleMap.clear();
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.78 - 1.79
---
Log message:
Allocating too large an array for ReachibilityMatrix.
---
Diffs of the changes: (+5 -2)
X86ISelDAGToDAG.cpp |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.78
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.79
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.78Thu Jul 27 17:10:00 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 27 17:35:40 2006
@@ -281,8 +281,11 @@
void X86DAGToDAGISel::DeterminReachibility(SDNode *f, SDNode *t) {
if (!ReachibilityMatrix) {
DetermineTopologicalOrdering();
-ReachibilityMatrix = new unsigned char[DAGSize * DAGSize];
-memset(ReachibilityMatrix, 0, DAGSize * DAGSize * sizeof(unsigned char));
+unsigned RMSize = DAGSize * DAGSize / 8;
+if ((DAGSize * DAGSize) % 8)
+ RMSize++;
+ReachibilityMatrix = new unsigned char[RMSize];
+memset(ReachibilityMatrix, 0, RMSize);
}
int Idf = f-getNodeId();
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.79 - 1.80
---
Log message:
Brain cramp..
---
Diffs of the changes: (+1 -3)
X86ISelDAGToDAG.cpp |4 +---
1 files changed, 1 insertion(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.79
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.80
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.79Thu Jul 27 17:35:40 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 27 18:35:40 2006
@@ -281,9 +281,7 @@
void X86DAGToDAGISel::DeterminReachibility(SDNode *f, SDNode *t) {
if (!ReachibilityMatrix) {
DetermineTopologicalOrdering();
-unsigned RMSize = DAGSize * DAGSize / 8;
-if ((DAGSize * DAGSize) % 8)
- RMSize++;
+unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
ReachibilityMatrix = new unsigned char[RMSize];
memset(ReachibilityMatrix, 0, RMSize);
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.80 - 1.81
---
Log message:
Another duh. Determine topological order before any target node is added.
---
Diffs of the changes: (+13 -13)
X86ISelDAGToDAG.cpp | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.80
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.81
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.80Thu Jul 27 18:35:40 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 27 19:10:59 2006
@@ -99,7 +99,8 @@
: SelectionDAGISel(X86Lowering),
X86Lowering(*TM.getTargetLowering()),
Subtarget(TM.getSubtargetX86Subtarget()),
-DAGSize(0), ReachibilityMatrix(NULL) {}
+DAGSize(0), TopOrder(NULL), IdToOrder(NULL),
+RMRange(NULL), ReachibilityMatrix(NULL) {}
virtual bool runOnFunction(Function Fn) {
// Make sure we re-emit a set of the global base reg if necessary
@@ -242,7 +243,6 @@
/// DetermineTopologicalOrdering - Determine topological ordering of the nodes
/// in the DAG.
void X86DAGToDAGISel::DetermineTopologicalOrdering() {
- DAGSize = CurDAG-AssignNodeIds();
TopOrder = new SDNode*[DAGSize];
IdToOrder = new unsigned[DAGSize];
memset(IdToOrder, 0, DAGSize * sizeof(unsigned));
@@ -280,7 +280,6 @@
void X86DAGToDAGISel::DeterminReachibility(SDNode *f, SDNode *t) {
if (!ReachibilityMatrix) {
-DetermineTopologicalOrdering();
unsigned RMSize = (DAGSize * DAGSize + 7) / 8;
ReachibilityMatrix = new unsigned char[RMSize];
memset(ReachibilityMatrix, 0, RMSize);
@@ -323,25 +322,26 @@
DEBUG(BB-dump());
MachineFunction::iterator FirstMBB = BB;
+ DAGSize = DAG.AssignNodeIds();
+ DetermineTopologicalOrdering();
+
// Codegen the basic block.
#ifndef NDEBUG
DEBUG(std::cerr = Instruction selection begins:\n);
Indent = 0;
#endif
DAG.setRoot(SelectRoot(DAG.getRoot()));
- assert(InFlightSet.empty() ISel InFlightSet has not been emptied!);
#ifndef NDEBUG
DEBUG(std::cerr = Instruction selection ends:\n);
#endif
- if (ReachibilityMatrix) {
-delete[] ReachibilityMatrix;
-delete[] TopOrder;
-delete[] IdToOrder;
-delete[] RMRange;
-ReachibilityMatrix = NULL;
-TopOrder = NULL;
-IdToOrder = RMRange = NULL;
- }
+
+ delete[] ReachibilityMatrix;
+ delete[] TopOrder;
+ delete[] IdToOrder;
+ delete[] RMRange;
+ ReachibilityMatrix = NULL;
+ TopOrder = NULL;
+ IdToOrder = RMRange = NULL;
CodeGenMap.clear();
HandleMap.clear();
ReplaceMap.clear();
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.81 - 1.82
---
Log message:
Node selected into address mode cannot be folded.
---
Diffs of the changes: (+39 -0)
X86ISelDAGToDAG.cpp | 39 +++
1 files changed, 39 insertions(+)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.81
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.82
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.81Thu Jul 27 19:10:59 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 27 19:49:31 2006
@@ -211,6 +211,21 @@
return ReachibilityMatrix[Idx / 8] (1 (Idx % 8));
}
+/// UnfoldableSet - An boolean array representing nodes which have been
+/// folded into addressing modes and therefore should not be folded in
+/// another operation.
+unsigned char *UnfoldableSet;
+
+inline void setUnfoldable(SDNode *N) {
+ unsigned Id = N-getNodeId();
+ UnfoldableSet[Id / 8] |= 1 (Id % 8);
+}
+
+inline bool isUnfoldable(SDNode *N) {
+ unsigned Id = N-getNodeId();
+ return UnfoldableSet[Id / 8] (1 (Id % 8));
+}
+
#ifndef NDEBUG
unsigned Indent;
#endif
@@ -218,6 +233,10 @@
}
bool X86DAGToDAGISel::IsFoldableBy(SDNode *N, SDNode *U) {
+ // Is it already folded by SelectAddr / SelectLEAAddr?
+ if (isUnfoldable(N))
+return false;
+
// If U use can somehow reach N through another path then U can't fold N or
// it will create a cycle. e.g. In the following diagram, U can reach N
// through X. If N is foled into into U, then X is both a predecessor and
@@ -323,6 +342,10 @@
MachineFunction::iterator FirstMBB = BB;
DAGSize = DAG.AssignNodeIds();
+ unsigned NumBytes = (DAGSize+7) / 8;
+ UnfoldableSet = new unsigned char[NumBytes];
+ memset(UnfoldableSet, 0, NumBytes);
+
DetermineTopologicalOrdering();
// Codegen the basic block.
@@ -339,9 +362,11 @@
delete[] TopOrder;
delete[] IdToOrder;
delete[] RMRange;
+ delete[] UnfoldableSet;
ReachibilityMatrix = NULL;
TopOrder = NULL;
IdToOrder = RMRange = NULL;
+ UnfoldableSet = NULL;
CodeGenMap.clear();
HandleMap.clear();
ReplaceMap.clear();
@@ -615,6 +640,13 @@
getAddressOperands(AM, Base, Scale, Index, Disp);
+ int Id = Base.Val ? Base.Val-getNodeId() : -1;
+ if (Id != -1)
+setUnfoldable(Base.Val);
+ Id = Index.Val ? Index.Val-getNodeId() : -1;
+ if (Id != -1)
+setUnfoldable(Index.Val);
+
return true;
}
@@ -663,6 +695,13 @@
return true;
}
+ int Id = Base.Val ? Base.Val-getNodeId() : -1;
+ if (Id != -1)
+setUnfoldable(Base.Val);
+ Id = Index.Val ? Index.Val-getNodeId() : -1;
+ if (Id != -1)
+setUnfoldable(Index.Val);
+
return false;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.82 - 1.83
---
Log message:
Rename IsFoldableBy to CanBeFoldedleBy
---
Diffs of the changes: (+3 -3)
X86ISelDAGToDAG.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.82
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.83
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.82Thu Jul 27 19:49:31 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 27 20:03:48 2006
@@ -118,7 +118,7 @@
virtual void EmitFunctionEntryCode(Function Fn, MachineFunction MF);
-virtual bool IsFoldableBy(SDNode *N, SDNode *U);
+virtual bool CanBeFoldedBy(SDNode *N, SDNode *U);
// Include the pieces autogenerated from the target description.
#include X86GenDAGISel.inc
@@ -232,7 +232,7 @@
};
}
-bool X86DAGToDAGISel::IsFoldableBy(SDNode *N, SDNode *U) {
+bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U) {
// Is it already folded by SelectAddr / SelectLEAAddr?
if (isUnfoldable(N))
return false;
@@ -711,7 +711,7 @@
if (N.getOpcode() == ISD::LOAD
N.hasOneUse()
!CodeGenMap.count(N.getValue(0))
- !IsFoldableBy(N.Val, P.Val))
+ !CanBeFoldedBy(N.Val, P.Val))
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
return false;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.73 - 1.74
---
Log message:
Add support for m inline asm constraints.
---
Diffs of the changes: (+29 -1)
X86ISelDAGToDAG.cpp | 30 +-
1 files changed, 29 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.73
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.74
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.73Fri Jun 2 17:38:37 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jun 8 13:03:49 2006
@@ -128,7 +128,13 @@
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
-
+/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+/// inline asm expressions.
+virtual bool SelectInlineAsmMemoryOperand(const SDOperand Op,
+ char ConstraintCode,
+ std::vectorSDOperand OutOps,
+ SelectionDAG DAG);
+
void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
inline void getAddressOperands(X86ISelAddressMode AM, SDOperand Base,
@@ -876,6 +882,28 @@
#endif
}
+bool X86DAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDOperand Op, char ConstraintCode,
+ std::vectorSDOperand OutOps, SelectionDAG
DAG){
+ SDOperand Op0, Op1, Op2, Op3;
+ switch (ConstraintCode) {
+ case 'o': // offsetable??
+ case 'v': // not offsetable??
+ default: return true;
+ case 'm': // memory
+if (!SelectAddr(Op, Op0, Op1, Op2, Op3))
+ return true;
+break;
+ }
+
+ OutOps.resize(4);
+ Select(OutOps[0], Op0);
+ Select(OutOps[1], Op1);
+ Select(OutOps[2], Op2);
+ Select(OutOps[3], Op3);
+ return false;
+}
+
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.71 - 1.72
---
Log message:
Use xor to clear a register.
---
Diffs of the changes: (+4 -6)
X86ISelDAGToDAG.cpp | 10 --
1 files changed, 4 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.71
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.72
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.71Tue May 30 15:24:48 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jun 2 16:20:34 2006
@@ -744,17 +744,17 @@
default: assert(0 Unsupported VT!);
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
-ClrOpcode = X86::MOV8ri;
+ClrOpcode = X86::MOV8r0;
SExtOpcode = X86::CBW;
break;
case MVT::i16:
LoReg = X86::AX; HiReg = X86::DX;
-ClrOpcode = X86::MOV16ri;
+ClrOpcode = X86::MOV16r0;
SExtOpcode = X86::CWD;
break;
case MVT::i32:
LoReg = X86::EAX; HiReg = X86::EDX;
-ClrOpcode = X86::MOV32ri;
+ClrOpcode = X86::MOV32r0;
SExtOpcode = X86::CDQ;
break;
}
@@ -783,9 +783,7 @@
SDOperand(CurDAG-getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
} else {
// Zero out the high part, effectively zero extending the input.
-SDOperand ClrNode =
- SDOperand(CurDAG-getTargetNode(ClrOpcode, NVT,
- CurDAG-getTargetConstant(0, NVT)),
0);
+SDOperand ClrNode = SDOperand(CurDAG-getTargetNode(ClrOpcode, NVT),
0);
Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(HiReg, NVT),
ClrNode, InFlag);
InFlag = Chain.getValue(1);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.72 - 1.73
X86RegisterInfo.cpp updated: 1.155 - 1.156
---
Log message:
Cygwin support. Patch by Anton Korobeynikov!
---
Diffs of the changes: (+28 -4)
X86ISelDAGToDAG.cpp |9 +++--
X86RegisterInfo.cpp | 23 +--
2 files changed, 28 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.72
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.73
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.72Fri Jun 2 16:20:34 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jun 2 17:38:37 2006
@@ -129,6 +129,8 @@
SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
+void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
+
inline void getAddressOperands(X86ISelAddressMode AM, SDOperand Base,
SDOperand Scale, SDOperand Index,
SDOperand Disp) {
@@ -250,8 +252,11 @@
/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
/// the main function.
-static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
- MachineFrameInfo *MFI) {
+void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
+ MachineFrameInfo *MFI) {
+ if (Subtarget-TargetType == X86Subtarget::isCygwin)
+BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol(__main);
+
// Switch the FPU to 64-bit precision mode for better compatibility and
speed.
int CWFrameIdx = MFI-CreateStackObject(2, 2);
addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.155
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.156
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.155 Wed May 31 14:00:07 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Jun 2 17:38:37 2006
@@ -14,9 +14,12 @@
#include X86.h
#include X86RegisterInfo.h
+#include X86Subtarget.h
+#include X86TargetMachine.h
#include X86InstrBuilder.h
#include llvm/Constants.h
#include llvm/Type.h
+#include llvm/Function.h
#include llvm/CodeGen/ValueTypes.h
#include llvm/CodeGen/MachineInstrBuilder.h
#include llvm/CodeGen/MachineFunction.h
@@ -635,7 +638,14 @@
// if frame pointer elimination is disabled.
//
static bool hasFP(MachineFunction MF) {
- return NoFramePointerElim || MF.getFrameInfo()-hasVarSizedObjects();
+ const Function* Fn = MF.getFunction();
+ const X86Subtarget* Subtarget =
MF.getTarget().getSubtargetX86Subtarget();
+
+ return (NoFramePointerElim ||
+ MF.getFrameInfo()-hasVarSizedObjects() ||
+ (Fn-hasExternalLinkage()
+ Fn-getName() == main
+ Subtarget-TargetType == X86Subtarget::isCygwin));
}
void X86RegisterInfo::
@@ -730,6 +740,9 @@
MachineBasicBlock MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned Align = MF.getTarget().getFrameInfo()-getStackAlignment();
+ const Function* Fn = MF.getFunction();
+ const X86Subtarget* Subtarget = MF.getTarget().getSubtargetX86Subtarget();
MachineInstr *MI;
// Get the number of bytes to allocate from the FrameInfo
@@ -744,7 +757,6 @@
// Round the size to a multiple of the alignment (don't forget the 4 byte
// offset though).
-unsigned Align = MF.getTarget().getFrameInfo()-getStackAlignment();
NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
}
@@ -775,6 +787,13 @@
MBB.insert(MBBI, MI);
}
+
+ // If it's main() on Cygwin\Mingw32 we should align stack as well
+ if (Fn-hasExternalLinkage() Fn-getName() == main
+ Subtarget-TargetType == X86Subtarget::isCygwin) {
+MI = BuildMI(X86::AND32ri, 2, X86::ESP).addImm(-Align);
+MBB.insert(MBBI, MI);
+ }
}
void X86RegisterInfo::emitEpilogue(MachineFunction MF,
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.69 - 1.70
X86InstrInfo.td updated: 1.271 - 1.272
---
Log message:
A addressing mode folding enhancement:
Fold c2 in (x c1) | c2 where (c2 c1)
e.g.
int test(int x) {
return (x 3) + 7;
}
This can be codegen'd as:
leal 7(,%eax,8), %eax
---
Diffs of the changes: (+25 -1)
X86ISelDAGToDAG.cpp | 24
X86InstrInfo.td |2 +-
2 files changed, 25 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.69
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.70
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.69Wed May 24 19:24:27 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue May 30 01:59:36 2006
@@ -392,6 +392,30 @@
}
break;
}
+
+ case ISD::OR: {
+if (!Available) {
+ X86ISelAddressMode Backup = AM;
+ // Look for (x c1) | c2 where (c2 c1)
+ ConstantSDNode *CN = dyn_castConstantSDNode(N.Val-getOperand(0));
+ if (CN !MatchAddress(N.Val-getOperand(1), AM, false)) {
+if (AM.GV == NULL AM.Disp == 0 CN-getValue() AM.Scale) {
+ AM.Disp = CN-getValue();
+ return false;
+}
+ }
+ AM = Backup;
+ CN = dyn_castConstantSDNode(N.Val-getOperand(1));
+ if (CN !MatchAddress(N.Val-getOperand(0), AM, false)) {
+if (AM.GV == NULL AM.Disp == 0 CN-getValue() AM.Scale) {
+ AM.Disp = CN-getValue();
+ return false;
+}
+ }
+ AM = Backup;
+}
+break;
+ }
}
// Is the base register already occupied?
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.271
llvm/lib/Target/X86/X86InstrInfo.td:1.272
--- llvm/lib/Target/X86/X86InstrInfo.td:1.271 Fri May 19 20:40:16 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue May 30 01:59:36 2006
@@ -133,7 +133,7 @@
// Define X86 specific addressing mode.
def addr: ComplexPatterniPTR, 4, SelectAddr, [];
def leaaddr : ComplexPatterniPTR, 4, SelectLEAAddr,
- [add, mul, shl, frameindex];
+ [add, mul, shl, or, frameindex];
//===--===//
// X86 Instruction Format Definitions.
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.70 - 1.71
---
Log message:
Remove bogus comment.
---
Diffs of the changes: (+0 -1)
X86ISelDAGToDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.70
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.71
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.70Tue May 30 01:59:36 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue May 30 15:24:48 2006
@@ -461,7 +461,6 @@
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal
addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
-/// For X86, it always is unless it's just a (Reg + const).
bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand Base,
SDOperand Scale,
SDOperand Index, SDOperand Disp) {
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.h X86InstrBuilder.h X86InstrInfo.h X86JITInfo.cpp X86Relocations.h
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.66 - 1.67
X86ISelLowering.h updated: 1.64 - 1.65
X86InstrBuilder.h updated: 1.20 - 1.21
X86InstrInfo.h updated: 1.51 - 1.52
X86JITInfo.cpp updated: 1.18 - 1.19
X86Relocations.h updated: 1.2 - 1.3
---
Log message:
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786:
http://llvm.cs.uiuc.edu/PR786 .
---
Diffs of the changes: (+6 -6)
X86ISelDAGToDAG.cpp |2 +-
X86ISelLowering.h |2 +-
X86InstrBuilder.h |2 +-
X86InstrInfo.h |2 +-
X86JITInfo.cpp |2 +-
X86Relocations.h|2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.66
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.67
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.66Sun May 21 01:28:50 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed May 24 12:04:04 2006
@@ -47,7 +47,7 @@
struct X86ISelAddressMode {
enum {
RegBase,
- FrameIndexBase,
+ FrameIndexBase
} BaseType;
struct {// This is really a union, discriminated by BaseType!
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.64
llvm/lib/Target/X86/X86ISelLowering.h:1.65
--- llvm/lib/Target/X86/X86ISelLowering.h:1.64 Tue May 23 16:06:34 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Wed May 24 12:04:04 2006
@@ -156,7 +156,7 @@
/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
/// corresponds to X86::PINSRW.
- PINSRW,
+ PINSRW
};
// X86 specific condition code. These correspond to X86_*_COND in
Index: llvm/lib/Target/X86/X86InstrBuilder.h
diff -u llvm/lib/Target/X86/X86InstrBuilder.h:1.20
llvm/lib/Target/X86/X86InstrBuilder.h:1.21
--- llvm/lib/Target/X86/X86InstrBuilder.h:1.20 Thu May 4 13:16:01 2006
+++ llvm/lib/Target/X86/X86InstrBuilder.h Wed May 24 12:04:04 2006
@@ -35,7 +35,7 @@
struct X86AddressMode {
enum {
RegBase,
-FrameIndexBase,
+FrameIndexBase
} BaseType;
union {
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.51
llvm/lib/Target/X86/X86InstrInfo.h:1.52
--- llvm/lib/Target/X86/X86InstrInfo.h:1.51 Thu May 18 01:27:15 2006
+++ llvm/lib/Target/X86/X86InstrInfo.h Wed May 24 12:04:04 2006
@@ -162,7 +162,7 @@
SpecialFP = 7 FPTypeShift,
OpcodeShift = 16,
-OpcodeMask= 0xFF OpcodeShift,
+OpcodeMask= 0xFF OpcodeShift
// Bits 25 - 31 are unused
};
}
Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.18
llvm/lib/Target/X86/X86JITInfo.cpp:1.19
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.18 Tue May 2 14:14:47 2006
+++ llvm/lib/Target/X86/X86JITInfo.cpp Wed May 24 12:04:04 2006
@@ -167,7 +167,7 @@
}
void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter MCE) {
- if (Fn != X86CompilationCallback) {
+ if (Fn != (void*)X86CompilationCallback) {
MCE.startFunctionStub(5);
MCE.emitByte(0xE9);
MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4);
Index: llvm/lib/Target/X86/X86Relocations.h
diff -u llvm/lib/Target/X86/X86Relocations.h:1.2
llvm/lib/Target/X86/X86Relocations.h:1.3
--- llvm/lib/Target/X86/X86Relocations.h:1.2Thu Apr 21 18:38:14 2005
+++ llvm/lib/Target/X86/X86Relocations.hWed May 24 12:04:04 2006
@@ -25,7 +25,7 @@
// reloc_absolute_word - Absolute relocation, just add the relocated
value
// to the value already in memory.
- reloc_absolute_word = 1,
+ reloc_absolute_word = 1
};
}
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.67 - 1.68 --- Log message: Clear HandleMap and ReplaceMap after instruction selection. Or it may cause non-deterministic behavior. --- Diffs of the changes: (+2 -0) X86ISelDAGToDAG.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.67 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.68 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.67Wed May 24 12:04:04 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed May 24 15:46:25 2006 @@ -186,6 +186,8 @@ DEBUG(std::cerr = Instruction selection ends:\n); #endif CodeGenMap.clear(); + HandleMap.clear(); + ReplaceMap.clear(); DAG.RemoveDeadNodes(); // Emit machine code to BB. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.65 - 1.66
---
Log message:
Back out indirect branch load folding hack. It broke some tests.
---
Diffs of the changes: (+0 -63)
X86ISelDAGToDAG.cpp | 63
1 files changed, 63 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.65
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.66
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.65Sat May 20 04:21:39 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sun May 21 01:28:50 2006
@@ -835,69 +835,6 @@
break;
}
-
-case X86ISD::CALL:
-case X86ISD::TAILCALL: {
- // Handle indirect call which folds a load here. This never matches by
- // the TableGen generated code since the load's chain result is read by
- // the callseq_start node or by a TokenFactor which feeds into the
- // callseq_start.
- SDOperand N1 = Node-getOperand(1);
- if (N1.getOpcode() == ISD::LOAD N1.hasOneUse()
- !CodeGenMap.count(N1.getValue(0))) {
-SDOperand Chain = Node-getOperand(0);
-SDNode *CallStart = FindCallStartFromCall(Chain.Val);
-if (!CallStart) break;
-SDNode *CSOp0 = CallStart-getOperand(0).Val;
-if (! (CSOp0 == N1.Val ||
- (CSOp0-getOpcode() == ISD::TokenFactor
-N1.Val-isOperand(CSOp0
- break;
-SDOperand Base, Scale, Index, Disp;
-if (SelectAddr(N1.getOperand(1), Base, Scale, Index, Disp)) {
- Select(Base, Base);
- Select(Scale, Scale);
- Select(Index, Index);
- Select(Disp, Disp);
- Select(Chain, Chain);
- bool HasOptInFlag = false;
- SDOperand InFlag;
- if (N.getNumOperands() == 3) {
-Select(InFlag, N.getOperand(2));
-HasOptInFlag = true;
- }
- SDNode *ResNode;
- if (HasOptInFlag)
-ResNode = CurDAG-getTargetNode(X86::CALL32m, MVT::Other,
MVT::Flag,
-Base, Scale, Index, Disp, Chain,
-InFlag);
- else
-ResNode = CurDAG-getTargetNode(X86::CALL32m, MVT::Other,
MVT::Flag,
-Base, Scale, Index, Disp, Chain);
-
- SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val,
- Chain.ResNo);
- SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, ResNode, 1);
- // CALLSEQ_START needs a chain! It can't be ResNode, that would cause
- // a cycle. It should be the chain of the load.
- Select(Chain, N1.getOperand(0));
- SelectionDAG::InsertISelMapEntry(CodeGenMap, N1.Val, 1, Chain.Val,
- Chain.ResNo);
- AddHandleReplacement(N1.Val, 1, Chain.Val, Chain.ResNo);
- Result = SDOperand(ResNode, 0);
-
-#ifndef NDEBUG
- DEBUG(std::cerr std::string(Indent-2, ' '));
- DEBUG(std::cerr == );
- DEBUG(Result.Val-dump(CurDAG));
- DEBUG(std::cerr \n);
- Indent -= 2;
-#endif
- return;
-}
- }
- break;
-}
}
SelectCode(Result, N);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.63 - 1.64 --- Log message: Missing break statements. --- Diffs of the changes: (+3 -0) X86ISelDAGToDAG.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.63 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.64 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.63Fri May 19 20:40:16 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat May 20 02:44:28 2006 @@ -832,6 +832,8 @@ #endif return; } + + break; } case X86ISD::CALL: @@ -884,6 +886,7 @@ return; } } + break; } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.61 - 1.62
---
Log message:
Handle indirect call which folds a load manually. This never matches by
the TableGen generated code since the load's chain result is read by
the callseq_start node.
---
Diffs of the changes: (+58 -0)
X86ISelDAGToDAG.cpp | 58
1 files changed, 58 insertions(+)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.61
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.62
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.61Tue May 16 02:21:53 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri May 19 20:36:52 2006
@@ -516,6 +516,13 @@
return CurDAG-getRegister(GlobalBaseReg, MVT::i32);
}
+static SDNode *FindCallStartFromCall(SDNode *Node) {
+ if (Node-getOpcode() == ISD::CALLSEQ_START) return Node;
+assert(Node-getOperand(0).getValueType() == MVT::Other
+ Node doesn't have a token chain argument!);
+ return FindCallStartFromCall(Node-getOperand(0).Val);
+}
+
void X86DAGToDAGISel::Select(SDOperand Result, SDOperand N) {
SDNode *Node = N.Val;
MVT::ValueType NVT = Node-getValueType(0);
@@ -826,6 +833,57 @@
return;
}
}
+
+case X86ISD::CALL: {
+ // Handle indirect call which folds a load here. This never matches by
+ // the TableGen generated code since the load's chain result is read by
+ // the callseq_start node.
+ SDOperand N1 = Node-getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD N1.hasOneUse()
+ !CodeGenMap.count(N1.getValue(0))) {
+SDOperand Chain = Node-getOperand(0);
+SDNode *CallStart = FindCallStartFromCall(Chain.Val);
+if (!CallStart || CallStart-getOperand(0).Val != N1.Val)
+ break;
+SDOperand Base, Scale, Index, Disp;
+if (SelectAddr(N1.getOperand(1), Base, Scale, Index, Disp)) {
+ Select(Base, Base);
+ Select(Scale, Scale);
+ Select(Index, Index);
+ Select(Disp, Disp);
+ Select(Chain, Chain);
+ bool HasOptInFlag = false;
+ SDOperand InFlag;
+ if (N.getNumOperands() == 3) {
+Select(InFlag, N.getOperand(2));
+HasOptInFlag = true;
+ }
+ SDNode *ResNode;
+ if (HasOptInFlag)
+ResNode = CurDAG-getTargetNode(X86::CALL32m, MVT::Other,
MVT::Flag,
+Base, Scale, Index, Disp, Chain,
+InFlag);
+ else
+ResNode = CurDAG-getTargetNode(X86::CALL32m, MVT::Other,
MVT::Flag,
+Base, Scale, Index, Disp, Chain);
+
+ SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val,
+ Chain.ResNo);
+ SelectionDAG::InsertISelMapEntry(CodeGenMap, N1.Val, 1, ResNode, 0);
+ SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, ResNode, 1);
+ Result = SDOperand(ResNode, 0);
+
+#ifndef NDEBUG
+ DEBUG(std::cerr std::string(Indent-2, ' '));
+ DEBUG(std::cerr == );
+ DEBUG(Result.Val-dump(CurDAG));
+ DEBUG(std::cerr \n);
+ Indent -= 2;
+#endif
+ return;
+}
+ }
+}
}
SelectCode(Result, N);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.62 - 1.63
X86InstrInfo.td updated: 1.270 - 1.271
---
Log message:
Remove unused patterns.
---
Diffs of the changes: (+4 -7)
X86ISelDAGToDAG.cpp |3 ++-
X86InstrInfo.td |8 ++--
2 files changed, 4 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.62
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.63
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.62Fri May 19 20:36:52 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri May 19 20:40:16 2006
@@ -834,7 +834,8 @@
}
}
-case X86ISD::CALL: {
+case X86ISD::CALL:
+case X86ISD::TAILCALL: {
// Handle indirect call which folds a load here. This never matches by
// the TableGen generated code since the load's chain result is read by
// the callseq_start node.
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.270
llvm/lib/Target/X86/X86InstrInfo.td:1.271
--- llvm/lib/Target/X86/X86InstrInfo.td:1.270 Fri May 19 13:40:54 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri May 19 20:40:16 2006
@@ -75,7 +75,7 @@
def X86call: SDNodeX86ISD::CALL, SDT_X86Call,
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag];
-def X86tailcall: SDNodeX86ISD::TAILCALL, SDT_X86Call,
+def X86tailcall: SDNodeX86ISD::TAILCALL, SDT_X86Call,
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag];
def X86rep_stos: SDNodeX86ISD::REP_STOS, SDTX86RepStr,
@@ -442,8 +442,7 @@
[];
def CALL32r : I0xFF, MRM2r, (ops GR32:$dst), call {*}$dst,
[(X86call GR32:$dst)];
-def CALL32m : I0xFF, MRM2m, (ops i32mem:$dst), call {*}$dst,
- [(X86call (loadiPTR addr:$dst))];
+def CALL32m : I0xFF, MRM2m, (ops i32mem:$dst), call {*}$dst, [];
}
// Tail call stuff.
@@ -2370,9 +2369,6 @@
def : Pat(X86tailcall GR32:$dst),
(CALL32r GR32:$dst);
-def : Pat(X86tailcall (loadiPTR addr:$dst)),
- (CALL32m addr:$dst);
-
def : Pat(X86tailcall tglobaladdr:$dst),
(CALLpcrel32 tglobaladdr:$dst);
def : Pat(X86tailcall texternalsym:$dst),
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.56 - 1.57 --- Log message: #include Intrinsics.h into all dag isels --- Diffs of the changes: (+1 -0) X86ISelDAGToDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.56 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.57 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.56Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Mar 25 00:47:10 2006 @@ -21,6 +21,7 @@ #include X86TargetMachine.h #include llvm/GlobalValue.h #include llvm/Instructions.h +#include llvm/Intrinsics.h #include llvm/Support/CFG.h #include llvm/CodeGen/MachineConstantPool.h #include llvm/CodeGen/MachineFunction.h ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.54 - 1.55 --- Log message: Don't match x 1 to LEAL. It's better to emit x + x. --- Diffs of the changes: (+4 -1) X86ISelDAGToDAG.cpp |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.54 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.55 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.54Sat Feb 25 04:09:08 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Feb 28 15:13:57 2006 @@ -453,8 +453,11 @@ else AM.IndexReg = CurDAG-getRegister(0, MVT::i32); - if (AM.Scale 1) + if (AM.Scale 2) Complexity += 2; + // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg + else if (AM.Scale 1) +Complexity++; // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA // to a LEA. This is determined with some expermentation but is by no means ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.53 - 1.54
---
Log message:
* Cleaned up addressing mode matching code.
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
---
Diffs of the changes: (+127 -156)
X86ISelDAGToDAG.cpp | 283 +++-
1 files changed, 127 insertions(+), 156 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.53
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.54
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.53Thu Feb 23 14:41:18 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Feb 25 04:09:08 2006
@@ -46,7 +46,6 @@
enum {
RegBase,
FrameIndexBase,
- ConstantPoolBase
} BaseType;
struct {// This is really a union, discriminated by BaseType!
@@ -58,9 +57,12 @@
SDOperand IndexReg;
unsigned Disp;
GlobalValue *GV;
+Constant *CP;
+unsigned Align;// CP alignment.
X86ISelAddressMode()
- : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0) {
+ : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0),
+CP(0), Align(0) {
}
};
}
@@ -132,7 +134,9 @@
Scale = getI8Imm(AM.Scale);
Index = AM.IndexReg;
Disp = AM.GV ? CurDAG-getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
-: getI32Imm(AM.Disp);
+: (AM.CP ?
+ CurDAG-getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp)
+ : getI32Imm(AM.Disp));
}
/// getI8Imm - Return a target constant with the specified value, of type
@@ -266,76 +270,54 @@
/// addressing mode
bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode AM,
bool isRoot) {
- bool StopHere = false;
- // If N has already been selected, we may or may not want to fold its
- // operands into the addressing mode. It will result in code duplication!
- // FIXME: Right now we do. That is, as long as the selected target node
- // does not produce a chain. This may require a more sophisticated
heuristics.
+ bool Available = false;
+ // If N has already been selected, reuse the result unless in some very
+ // specific cases.
std::mapSDOperand, SDOperand::iterator CGMI=
CodeGenMap.find(N.getValue(0));
if (CGMI != CodeGenMap.end()) {
-if (isRoot)
- // Stop here if it is a root. It's probably not profitable to go deeper.
- StopHere = true;
-else {
- for (unsigned i = 0, e = CGMI-second.Val-getNumValues(); i != e; ++i) {
-if (CGMI-second.Val-getValueType(i) == MVT::Other)
- StopHere = true;
- }
-}
+Available = true;
}
switch (N.getOpcode()) {
default: break;
- case ISD::FrameIndex:
-if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
- AM.BaseType = X86ISelAddressMode::FrameIndexBase;
- AM.Base.FrameIndex = castFrameIndexSDNode(N)-getIndex();
- return false;
-}
-break;
+ case ISD::Constant:
+AM.Disp += castConstantSDNode(N)-getValue();
+return false;
- case ISD::ConstantPool:
-if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
- if (ConstantPoolSDNode *CP = dyn_castConstantPoolSDNode(N)) {
-AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
-AM.Base.Reg = CurDAG-getTargetConstantPool(CP-get(), MVT::i32,
-CP-getAlignment());
-return false;
+ case X86ISD::Wrapper:
+// If both base and index components have been picked, we can't fit
+// the result available in the register in the addressing mode. Duplicate
+// GlobalAddress or ConstantPool as displacement.
+if (!Available || (AM.Base.Reg.Val AM.IndexReg.Val)) {
+ if (ConstantPoolSDNode *CP =
+ dyn_castConstantPoolSDNode(N.getOperand(0))) {
+if (AM.CP == 0) {
+ AM.CP = CP-get();
+ AM.Align = CP-getAlignment();
+ AM.Disp += CP-getOffset();
+ return false;
+}
+ } else if (GlobalAddressSDNode *G =
+ dyn_castGlobalAddressSDNode(N.getOperand(0))) {
+if (AM.GV == 0) {
+ AM.GV = G-getGlobal();
+ AM.Disp += G-getOffset();
+ return false;
+}
}
}
break;
- case ISD::GlobalAddress:
-if (AM.GV == 0) {
- AM.GV = castGlobalAddressSDNode(N)-getGlobal();
+ case ISD::FrameIndex:
+if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
+ AM.BaseType = X86ISelAddressMode::FrameIndexBase;
+ AM.Base.FrameIndex = castFrameIndexSDNode(N)-getIndex();
return false;
}
break;
- case X86ISD::Wrapper:
-if (ConstantPoolSDNode *CP =
-dyn_castConstantPoolSDNode(N.getOperand(0))) {
- if (AM.BaseType ==
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.52 - 1.53
X86ISelLowering.cpp updated: 1.95 - 1.96
X86ISelLowering.h updated: 1.31 - 1.32
X86InstrInfo.td updated: 1.248 - 1.249
---
Log message:
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
---
Diffs of the changes: (+81 -37)
X86ISelDAGToDAG.cpp | 71 +++-
X86ISelLowering.cpp | 31 --
X86ISelLowering.h |6 ++--
X86InstrInfo.td | 10 +--
4 files changed, 81 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.52
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.53
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.52Wed Feb 22 20:43:52 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Feb 23 14:41:18 2006
@@ -295,7 +295,6 @@
break;
case ISD::ConstantPool:
- case ISD::TargetConstantPool:
if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
if (ConstantPoolSDNode *CP = dyn_castConstantPoolSDNode(N)) {
AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
@@ -307,17 +306,27 @@
break;
case ISD::GlobalAddress:
- case ISD::TargetGlobalAddress:
if (AM.GV == 0) {
AM.GV = castGlobalAddressSDNode(N)-getGlobal();
return false;
}
break;
- case X86ISD::TGAWrapper:
-if (AM.GV == 0) {
- AM.GV = castGlobalAddressSDNode(N.getOperand(0))-getGlobal();
- return false;
+ case X86ISD::Wrapper:
+if (ConstantPoolSDNode *CP =
+dyn_castConstantPoolSDNode(N.getOperand(0))) {
+ if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
+AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
+AM.Base.Reg = CurDAG-getTargetConstantPool(CP-get(), MVT::i32,
+CP-getAlignment());
+return false;
+ }
+} else if (GlobalAddressSDNode *G =
+ dyn_castGlobalAddressSDNode(N.getOperand(0))) {
+ if (AM.GV == 0) {
+AM.GV = castGlobalAddressSDNode(N.getOperand(0))-getGlobal();
+return false;
+ }
}
break;
@@ -484,9 +493,11 @@
Complexity++;
if (SelectIndex)
Complexity++;
- if (AM.GV)
+ if (AM.GV) {
Complexity++;
- else if (AM.Disp 1)
+if (AM.Disp)
+ Complexity++;
+ } else if (AM.Disp 1)
Complexity++;
// Suppose base == %eax and it has multiple uses, then instead of
// movl %eax, %ecx
@@ -574,13 +585,43 @@
switch (Opcode) {
default: break;
-case X86ISD::TGAWrapper: {
- GlobalValue *GV =
castGlobalAddressSDNode(N.getOperand(0))-getGlobal();
- SDOperand TGA = CurDAG-getTargetGlobalAddress(GV, MVT::i32);
- Result = CodeGenMap[N] =
-SDOperand(CurDAG-getTargetNode(X86::MOV32ri, MVT::i32, TGA), 0);
+case X86ISD::GlobalBaseReg:
+ Result = getGlobalBaseReg();
+ return;
+
+case X86ISD::Wrapper: {
+ // It's beneficial to manully select the wrapper nodes here rather
+ // then using tablgen'd code to match this. We do not want to mutate the
+ // node to MOV32ri and we do not want to record this in CodeGenMap.
+ // We want to allow the wrapped leaf nodes be duplicated so they can
+ // be used in addressing modes.
+ // e.g.
+ // 0xa59e4a0: i32 = TargetGlobalAddress xxx 0
+ // 0xa59e740: i32 = X86ISD::Wrapper 0xa59e4a0
+ // ...
+ // 0xa59e880: i32 = add 0xa59e740, 0xa59e800
+ // ...
+ // 0xa59e880: multiple use
+ // 0xa59e970: i32 = add 0xa59e880, 0xa59e910
+ // ...
+ // 0xa59ea60: i32,ch = load 0xa589780, 0xa59e970, 0xa59ea00
+ // ...
+ // 0xa59e880: multiple use
+ //0xa59eb60: ch = CopyToReg 0xa59ea60:1, 0xa59eaf0, 0xa59e880
+ // By allowing the TargetGlobalAddress to be duplicated, it can appear
+ // in the load address as well as an operand of the add.
+ Result = SDOperand(CurDAG-getTargetNode(X86::MOV32ri, MVT::i32,
+ N.getOperand(0)), 0);
+#ifndef NDEBUG
+ DEBUG(std::cerr std::string(Indent-2, ' '));
+ DEBUG(std::cerr == );
+ DEBUG(Result.Val-dump(CurDAG));
+ DEBUG(std::cerr \n);
+ Indent -= 2;
+#endif
return;
}
+
case ISD::MULHU:
case ISD::MULHS: {
if (Opcode == ISD::MULHU)
@@ -666,10 +707,6 @@
return;
}
-case X86ISD::GlobalBaseReg:
- Result = getGlobalBaseReg();
- return;
-
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.50 - 1.51
---
Log message:
X86 codegen tweak to use lea in another case:
Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
---
Diffs of the changes: (+12 -9)
X86ISelDAGToDAG.cpp | 21 -
1 files changed, 12 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.50
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.51
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.50Fri Feb 17 18:15:05 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Feb 22 18:13:58 2006
@@ -457,23 +457,19 @@
SDOperand Index, SDOperand Disp) {
X86ISelAddressMode AM;
if (!MatchAddress(N, AM)) {
-bool SelectBase = false;
bool SelectIndex = false;
bool Check = false;
if (AM.BaseType == X86ISelAddressMode::RegBase) {
- if (AM.Base.Reg.Val) {
-Check = true;
-SelectBase = true;
- } else {
+ if (AM.Base.Reg.Val)
+Check = true;
+ else
AM.Base.Reg = CurDAG-getRegister(0, MVT::i32);
- }
}
-if (AM.IndexReg.Val) {
+if (AM.IndexReg.Val)
SelectIndex = true;
-} else {
+else
AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
-}
if (Check) {
unsigned Complexity = 0;
@@ -485,6 +481,13 @@
Complexity++;
else if (AM.Disp 1)
Complexity++;
+ // Suppose base == %eax and it has multiple uses, then instead of
+ // movl %eax, %ecx
+ // addl $8, %ecx
+ // use
+ // leal 8(%eax), %ecx.
+ if (AM.Base.Reg.Val-use_size() 1)
+Complexity++;
if (Complexity = 1)
return false;
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.48 - 1.49
---
Log message:
Prevent certain nodes that have already been selected from being folded into
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.
---
Diffs of the changes: (+40 -19)
X86ISelDAGToDAG.cpp | 59 +++-
1 files changed, 40 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.48
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.49
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.48Fri Feb 10 16:46:26 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Feb 10 20:05:36 2006
@@ -107,7 +107,7 @@
private:
void Select(SDOperand Result, SDOperand N);
-bool MatchAddress(SDOperand N, X86ISelAddressMode AM);
+bool MatchAddress(SDOperand N, X86ISelAddressMode AM, bool isRoot = true);
bool SelectAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
@@ -252,7 +252,26 @@
/// MatchAddress - Add the specified node to the specified addressing mode,
/// returning true if it cannot be done. This just pattern matches for the
/// addressing mode
-bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode AM) {
+bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode AM,
+ bool isRoot) {
+ bool StopHere = false;
+ // If N has already been selected, we may or may not want to fold its
+ // operands into the addressing mode. It will result in code duplication!
+ // FIXME: Right now we do. That is, as long as the selected target node
+ // does not produce a chain. This may require a more sophisticated
heuristics.
+ std::mapSDOperand, SDOperand::iterator CGMI=
CodeGenMap.find(N.getValue(0));
+ if (CGMI != CodeGenMap.end()) {
+if (isRoot)
+ // Stop here if it is a root. It's probably not profitable to go deeper.
+ StopHere = true;
+else {
+ for (unsigned i = 0, e = CGMI-second.Val-getNumValues(); i != e; ++i) {
+if (CGMI-second.Val-getValueType(i) == MVT::Other)
+ StopHere = true;
+ }
+}
+ }
+
switch (N.getOpcode()) {
default: break;
case ISD::FrameIndex:
@@ -287,7 +306,7 @@
return false;
case ISD::SHL:
-if (AM.IndexReg.Val == 0 AM.Scale == 1)
+if (!StopHere AM.IndexReg.Val == 0 AM.Scale == 1)
if (ConstantSDNode *CN = dyn_castConstantSDNode(N.Val-getOperand(1)))
{
unsigned Val = CN-getValue();
if (Val == 1 || Val == 2 || Val == 3) {
@@ -313,7 +332,7 @@
case ISD::MUL:
// X*[3,5,9] - X+X*[2,4,8]
-if (AM.IndexReg.Val == 0 AM.BaseType == X86ISelAddressMode::RegBase
+if (!StopHere AM.IndexReg.Val == 0 AM.BaseType ==
X86ISelAddressMode::RegBase
AM.Base.Reg.Val == 0)
if (ConstantSDNode *CN = dyn_castConstantSDNode(N.Val-getOperand(1)))
if (CN-getValue() == 3 || CN-getValue() == 5 || CN-getValue() == 9)
{
@@ -341,15 +360,17 @@
break;
case ISD::ADD: {
-X86ISelAddressMode Backup = AM;
-if (!MatchAddress(N.Val-getOperand(0), AM)
-!MatchAddress(N.Val-getOperand(1), AM))
- return false;
-AM = Backup;
-if (!MatchAddress(N.Val-getOperand(1), AM)
-!MatchAddress(N.Val-getOperand(0), AM))
- return false;
-AM = Backup;
+if (!StopHere) {
+ X86ISelAddressMode Backup = AM;
+ if (!MatchAddress(N.Val-getOperand(0), AM, false)
+ !MatchAddress(N.Val-getOperand(1), AM, false))
+return false;
+ AM = Backup;
+ if (!MatchAddress(N.Val-getOperand(1), AM, false)
+ !MatchAddress(N.Val-getOperand(0), AM, false))
+return false;
+ AM = Backup;
+}
break;
}
}
@@ -474,7 +495,7 @@
if (Opcode = ISD::BUILTIN_OP_END Opcode X86ISD::FIRST_NUMBER) {
Result = N;
#ifndef NDEBUG
-DEBUG(std::cerr std::string(Indent, ' '));
+DEBUG(std::cerr std::string(Indent-2, ' '));
DEBUG(std::cerr == );
DEBUG(Node-dump(CurDAG));
DEBUG(std::cerr \n);
@@ -487,7 +508,7 @@
if (CGMI != CodeGenMap.end()) {
Result = CGMI-second;
#ifndef NDEBUG
-DEBUG(std::cerr std::string(Indent, ' '));
+DEBUG(std::cerr std::string(Indent-2, ' '));
DEBUG(std::cerr == );
DEBUG(Result.Val-dump(CurDAG));
DEBUG(std::cerr \n);
@@ -574,7 +595,7 @@
}
#ifndef NDEBUG
- DEBUG(std::cerr std::string(Indent, ' '));
+ DEBUG(std::cerr std::string(Indent-2, ' '));
DEBUG(std::cerr == );
DEBUG(Result.Val-dump(CurDAG));
DEBUG(std::cerr \n);
@@ -682,7 +703,7 @@
}
#ifndef NDEBUG
- DEBUG(std::cerr std::string(Indent, ' '));
+ DEBUG(std::cerr std::string(Indent-2,
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.45 - 1.46
---
Log message:
Match tblgen change.
---
Diffs of the changes: (+2 -2)
X86ISelDAGToDAG.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.45
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.46
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.45Thu Feb 9 01:17:49 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Feb 9 16:12:53 2006
@@ -536,7 +536,7 @@
CodeGenMap[N.getValue(0)] = Result;
if (foldedLoad) {
CodeGenMap[N1.getValue(1)] = Result.getValue(1);
-AddHandleReplacement(N1.getValue(1), Result.getValue(1));
+AddHandleReplacement(N1.Val, 1, Result.Val, 1);
}
return;
@@ -637,7 +637,7 @@
CodeGenMap[N.getValue(0)] = Result;
if (foldedLoad) {
CodeGenMap[N1.getValue(1)] = Result.getValue(1);
-AddHandleReplacement(N1.getValue(1), Result.getValue(1));
+AddHandleReplacement(N1.Val, 1, Result.Val, 1);
}
return;
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.43 - 1.44
---
Log message:
Change Select() from
SDOperand Select(SDOperand N);
to
void Select(SDOperand Result, SDOperand N);
---
Diffs of the changes: (+53 -38)
X86ISelDAGToDAG.cpp | 91 ++--
1 files changed, 53 insertions(+), 38 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.43
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.44
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.43Mon Feb 6 00:02:33 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Feb 8 18:37:58 2006
@@ -104,7 +104,7 @@
#include X86GenDAGISel.inc
private:
-SDOperand Select(SDOperand N);
+void Select(SDOperand Result, SDOperand N);
bool MatchAddress(SDOperand N, X86ISelAddressMode AM);
bool SelectAddr(SDOperand N, SDOperand Base, SDOperand Scale,
@@ -445,17 +445,22 @@
return false;
}
-SDOperand X86DAGToDAGISel::Select(SDOperand N) {
+void X86DAGToDAGISel::Select(SDOperand Result, SDOperand N) {
SDNode *Node = N.Val;
MVT::ValueType NVT = Node-getValueType(0);
unsigned Opc, MOpc;
unsigned Opcode = Node-getOpcode();
- if (Opcode = ISD::BUILTIN_OP_END Opcode X86ISD::FIRST_NUMBER)
-return N; // Already selected.
+ if (Opcode = ISD::BUILTIN_OP_END Opcode X86ISD::FIRST_NUMBER) {
+Result = N;
+return; // Already selected.
+ }
std::mapSDOperand, SDOperand::iterator CGMI = CodeGenMap.find(N);
- if (CGMI != CodeGenMap.end()) return CGMI-second;
+ if (CGMI != CodeGenMap.end()) {
+Result = CGMI-second;
+return;
+ }
switch (Opcode) {
default: break;
@@ -499,33 +504,39 @@
}
}
- SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
- : CurDAG-getEntryNode();
+ SDOperand Chain;
+ if (foldedLoad)
+Select(Chain, N1.getOperand(0));
+ else
+Chain = CurDAG-getEntryNode();
- SDOperand InFlag;
+ SDOperand InFlag(0, 0);
+ Select(N0, N0);
Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(LoReg, NVT),
-Select(N0), InFlag);
+N0, InFlag);
InFlag = Chain.getValue(1);
if (foldedLoad) {
-Tmp0 = Select(Tmp0);
-Tmp1 = Select(Tmp1);
-Tmp2 = Select(Tmp2);
-Tmp3 = Select(Tmp3);
+Select(Tmp0, Tmp0);
+Select(Tmp1, Tmp1);
+Select(Tmp2, Tmp2);
+Select(Tmp3, Tmp3);
Chain = CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
Tmp2, Tmp3, Chain, InFlag);
InFlag = Chain.getValue(1);
} else {
-InFlag = CurDAG-getTargetNode(Opc, MVT::Flag, Select(N1), InFlag);
+Select(N1, N1);
+InFlag = CurDAG-getTargetNode(Opc, MVT::Flag, N1, InFlag);
}
- SDOperand Result = CurDAG-getCopyFromReg(Chain, HiReg, NVT, InFlag);
+ Result = CurDAG-getCopyFromReg(Chain, HiReg, NVT, InFlag);
CodeGenMap[N.getValue(0)] = Result;
if (foldedLoad) {
CodeGenMap[N1.getValue(1)] = Result.getValue(1);
AddHandleReplacement(N1.getValue(1), Result.getValue(1));
}
- return Result;
+
+ return;
}
case ISD::SDIV:
@@ -576,12 +587,16 @@
bool foldedLoad = false;
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
- SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
- : CurDAG-getEntryNode();
+ SDOperand Chain;
+ if (foldedLoad)
+Select(Chain, N1.getOperand(0));
+ else
+Chain = CurDAG-getEntryNode();
- SDOperand InFlag;
+ SDOperand InFlag(0, 0);
+ Select(N0, N0);
Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(LoReg, NVT),
-Select(N0), InFlag);
+N0, InFlag);
InFlag = Chain.getValue(1);
if (isSigned) {
@@ -598,25 +613,26 @@
}
if (foldedLoad) {
-Tmp0 = Select(Tmp0);
-Tmp1 = Select(Tmp1);
-Tmp2 = Select(Tmp2);
-Tmp3 = Select(Tmp3);
+Select(Tmp0, Tmp0);
+Select(Tmp1, Tmp1);
+Select(Tmp2, Tmp2);
+Select(Tmp3, Tmp3);
Chain = CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
Tmp2, Tmp3, Chain, InFlag);
InFlag = Chain.getValue(1);
} else {
-InFlag = CurDAG-getTargetNode(Opc, MVT::Flag, Select(N1), InFlag);
+Select(N1, N1);
+InFlag = CurDAG-getTargetNode(Opc, MVT::Flag, N1, InFlag);
}
- SDOperand Result = CurDAG-getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
-NVT, InFlag);
+ Result =
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.42 - 1.43
---
Log message:
- Update load folding checks to match those auto-generated by tblgen.
- Manually select SDOperand's returned by TryFoldLoad which make up the
load address.
---
Diffs of the changes: (+26 -11)
X86ISelDAGToDAG.cpp | 37 ++---
1 files changed, 26 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.42
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.43
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.42Sun Feb 5 00:46:41 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Feb 6 00:02:33 2006
@@ -111,7 +111,8 @@
SDOperand Index, SDOperand Disp);
bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
-bool TryFoldLoad(SDOperand N, SDOperand Base, SDOperand Scale,
+bool TryFoldLoad(SDOperand P, SDOperand N,
+ SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
inline void getAddressOperands(X86ISelAddressMode AM, SDOperand Base,
@@ -381,11 +382,13 @@
return true;
}
-bool X86DAGToDAGISel::TryFoldLoad(SDOperand N, SDOperand Base,
- SDOperand Scale, SDOperand Index,
- SDOperand Disp) {
- if (N.getOpcode() == ISD::LOAD N.hasOneUse()
- CodeGenMap.count(N.getValue(1)) == 0)
+bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
+ SDOperand Base, SDOperand Scale,
+ SDOperand Index, SDOperand Disp) {
+ if (N.getOpcode() == ISD::LOAD
+ N.hasOneUse()
+ !CodeGenMap.count(N.getValue(0))
+ (P.getNumOperands() == 1 || !isNonImmUse(P.Val, N.Val)))
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
return false;
}
@@ -486,10 +489,10 @@
bool foldedLoad = false;
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
- foldedLoad = TryFoldLoad(N1, Tmp0, Tmp1, Tmp2, Tmp3);
+ foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
// MULHU and MULHS are commmutative
if (!foldedLoad) {
-foldedLoad = TryFoldLoad(N0, Tmp0, Tmp1, Tmp2, Tmp3);
+foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
if (foldedLoad) {
N0 = Node-getOperand(1);
N1 = Node-getOperand(0);
@@ -505,6 +508,10 @@
InFlag = Chain.getValue(1);
if (foldedLoad) {
+Tmp0 = Select(Tmp0);
+Tmp1 = Select(Tmp1);
+Tmp2 = Select(Tmp2);
+Tmp3 = Select(Tmp3);
Chain = CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
Tmp2, Tmp3, Chain, InFlag);
InFlag = Chain.getValue(1);
@@ -514,8 +521,10 @@
SDOperand Result = CurDAG-getCopyFromReg(Chain, HiReg, NVT, InFlag);
CodeGenMap[N.getValue(0)] = Result;
- if (foldedLoad)
+ if (foldedLoad) {
CodeGenMap[N1.getValue(1)] = Result.getValue(1);
+AddHandleReplacement(N1.getValue(1), Result.getValue(1));
+ }
return Result;
}
@@ -566,7 +575,7 @@
bool foldedLoad = false;
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
- foldedLoad = TryFoldLoad(N1, Tmp0, Tmp1, Tmp2, Tmp3);
+ foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
: CurDAG-getEntryNode();
@@ -589,6 +598,10 @@
}
if (foldedLoad) {
+Tmp0 = Select(Tmp0);
+Tmp1 = Select(Tmp1);
+Tmp2 = Select(Tmp2);
+Tmp3 = Select(Tmp3);
Chain = CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
Tmp2, Tmp3, Chain, InFlag);
InFlag = Chain.getValue(1);
@@ -599,8 +612,10 @@
SDOperand Result = CurDAG-getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
NVT, InFlag);
CodeGenMap[N.getValue(0)] = Result;
- if (foldedLoad)
+ if (foldedLoad) {
CodeGenMap[N1.getValue(1)] = Result.getValue(1);
+AddHandleReplacement(N1.getValue(1), Result.getValue(1));
+ }
return Result;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.38 - 1.39
---
Log message:
Complex pattern's custom matcher should not call Select() on any operands.
Select them afterwards if it returns true.
---
Diffs of the changes: (+7 -13)
X86ISelDAGToDAG.cpp | 20 +++-
1 files changed, 7 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.38
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.39
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.38Tue Jan 31 16:28:30 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Feb 4 02:50:49 2006
@@ -369,17 +369,11 @@
return false;
if (AM.BaseType == X86ISelAddressMode::RegBase) {
-if (AM.Base.Reg.Val) {
- if (AM.Base.Reg.getOpcode() != ISD::Register)
-AM.Base.Reg = Select(AM.Base.Reg);
-} else {
+if (!AM.Base.Reg.Val)
AM.Base.Reg = CurDAG-getRegister(0, MVT::i32);
-}
}
- if (AM.IndexReg.Val)
-AM.IndexReg = Select(AM.IndexReg);
- else
+ if (!AM.IndexReg.Val)
AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
getAddressOperands(AM, Base, Scale, Index, Disp);
@@ -441,11 +435,6 @@
return false;
}
-if (SelectBase)
- AM.Base.Reg = Select(AM.Base.Reg);
-if (SelectIndex)
- AM.IndexReg = Select(AM.IndexReg);
-
getAddressOperands(AM, Base, Scale, Index, Disp);
return true;
}
@@ -461,6 +450,11 @@
if (Opcode = ISD::BUILTIN_OP_END Opcode X86ISD::FIRST_NUMBER)
return N; // Already selected.
+ // These are probably emitted by SelectAddr().
+ if (Opcode == ISD::TargetConstant || Opcode == ISD::TargetConstantPool ||
+ Opcode == ISD::TargetFrameIndex || Opcode == ISD::TargetGlobalAddress)
+return N;
+
std::mapSDOperand, SDOperand::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI-second;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.41 - 1.42 --- Log message: Use SelectRoot() as entry of any tblgen based isel. --- Diffs of the changes: (+2 -1) X86ISelDAGToDAG.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.41 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.42 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.41Sat Feb 4 23:25:07 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Feb 5 00:46:41 2006 @@ -30,6 +30,7 @@ #include llvm/Support/Debug.h #include llvm/ADT/Statistic.h #include iostream +#include set using namespace llvm; //===--===// @@ -151,7 +152,7 @@ MachineFunction::iterator FirstMBB = BB; // Codegen the basic block. - DAG.setRoot(Select(DAG.getRoot())); + DAG.setRoot(SelectRoot(DAG.getRoot())); CodeGenMap.clear(); DAG.RemoveDeadNodes(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.33 - 1.34
X86ISelLowering.cpp updated: 1.49 - 1.50
---
Log message:
A obvious typo
---
Diffs of the changes: (+3 -1)
X86ISelDAGToDAG.cpp |2 ++
X86ISelLowering.cpp |2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.33
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.34
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.33Mon Jan 16 15:21:29 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jan 18 19:46:14 2006
@@ -215,6 +215,7 @@
/// the main function.
static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
+#if 0
// Switch the FPU to 64-bit precision mode for better compatibility and
speed.
int CWFrameIdx = MFI-CreateStackObject(2, 2);
addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
@@ -225,6 +226,7 @@
// Reload the modified control word now.
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+#endif
}
void X86DAGToDAGISel::EmitFunctionEntryCode(Function Fn, MachineFunction MF)
{
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.49
llvm/lib/Target/X86/X86ISelLowering.cpp:1.50
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.49Wed Jan 18 03:26:46 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Jan 18 19:46:14 2006
@@ -1457,7 +1457,7 @@
Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
} else {
Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
- Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt);
+ Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
}
SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.34 - 1.35
---
Log message:
Didn't mean to check that in.
---
Diffs of the changes: (+0 -2)
X86ISelDAGToDAG.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.34
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.35
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.34Wed Jan 18 19:46:14 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jan 18 19:52:56 2006
@@ -215,7 +215,6 @@
/// the main function.
static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
-#if 0
// Switch the FPU to 64-bit precision mode for better compatibility and
speed.
int CWFrameIdx = MFI-CreateStackObject(2, 2);
addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
@@ -226,7 +225,6 @@
// Reload the modified control word now.
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
-#endif
}
void X86DAGToDAGISel::EmitFunctionEntryCode(Function Fn, MachineFunction MF)
{
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.32 - 1.33
X86ISelLowering.cpp updated: 1.42 - 1.43
X86InstrInfo.td updated: 1.206 - 1.207
---
Log message:
Fix FP_TO_INT**_IN_MEM lowering.
---
Diffs of the changes: (+132 -103)
X86ISelDAGToDAG.cpp | 58
X86ISelLowering.cpp | 150 +---
X86InstrInfo.td | 27 -
3 files changed, 132 insertions(+), 103 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.32
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.33
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.32Sun Jan 15 03:00:21 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jan 16 15:21:29 2006
@@ -642,64 +642,6 @@
return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
-
-case X86ISD::FP_TO_INT16_IN_MEM:
-case X86ISD::FP_TO_INT32_IN_MEM:
-case X86ISD::FP_TO_INT64_IN_MEM: {
- assert(N.getOperand(1).getValueType() == MVT::f64);
-
- // Change the floating point control register to use round towards zero
- // mode when truncating to an integer value.
- MachineFunction MF = CurDAG-getMachineFunction();
- int CWFI = MF.getFrameInfo()-CreateStackObject(2, 2);
- SDOperand CWSlot = CurDAG-getFrameIndex(CWFI, MVT::i32);
- SDOperand Base, Scale, Index, Disp;
- (void)SelectAddr(CWSlot, Base, Scale, Index, Disp);
- SDOperand Chain = N.getOperand(0);
-
- // Save the control word.
- Chain = CurDAG-getTargetNode(X86::FNSTCW16m, MVT::Other,
-Base, Scale, Index, Disp, Chain);
-
- // Load the old value of the high byte of the control word.
- SDOperand OldCW =
-CurDAG-getTargetNode(X86::MOV16rm, MVT::i16, MVT::Other,
- Base, Scale, Index, Disp, Chain);
- Chain = OldCW.getValue(1);
-
- // Set the high part to be round to zero...
- Chain = CurDAG-getTargetNode(X86::MOV16mi, MVT::Other,
-Base, Scale, Index, Disp,
-CurDAG-getConstant(0xC7F, MVT::i16),
-Chain);
-
- // Reload the modified control word now...
- Chain = CurDAG-getTargetNode(X86::FLDCW16m, MVT::Other,
-Base, Scale, Index, Disp, Chain);
-
- // Restore the memory image of control word to original value
- Chain = CurDAG-getTargetNode(X86::MOV16mr, MVT::Other,
-Base, Scale, Index, Disp, OldCW, Chain);
-
- switch (Opcode) {
- default: assert(0 Unknown FP_TO_INT*_IN_MEM);
- case X86ISD::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
- case X86ISD::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
- case X86ISD::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
- }
-
- SDOperand N1 = Select(N.getOperand(1));
- SDOperand Base2, Scale2, Index2, Disp2;
- (void)SelectAddr(N.getOperand(2), Base2, Scale2, Index2, Disp2);
- Chain = CurDAG-getTargetNode(Opc, MVT::Other,
-Base2, Scale2, Index2, Disp2, N1, Chain);
-
- // Reload the modified control word now...
- CodeGenMap[N] =
-Chain = CurDAG-getTargetNode(X86::FLDCW16m, MVT::Other,
- Base, Scale, Index, Disp, Chain);
- return Chain;
-}
}
return SelectCode(N);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.42
llvm/lib/Target/X86/X86ISelLowering.cpp:1.43
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.42Sun Jan 15 03:00:21 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 16 15:21:29 2006
@@ -13,6 +13,7 @@
//===--===//
#include X86.h
+#include X86InstrBuilder.h
#include X86ISelLowering.h
#include X86TargetMachine.h
#include llvm/CallingConv.h
@@ -1261,54 +1262,117 @@
MachineBasicBlock *
X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
- assert((MI-getOpcode() == X86::CMOV_FR32 ||
- MI-getOpcode() == X86::CMOV_FR64)
- Unexpected instr type to insert);
-
- // To insert a SELECT_CC instruction, we actually have to insert the
diamond
- // control-flow pattern. The incoming instruction knows the destination vreg
- // to set, the condition code register to branch on, the true/false values to
- // select between, and a branch opcode to use.
- const BasicBlock *LLVM_BB = BB-getBasicBlock();
- ilistMachineBasicBlock::iterator It = BB;
- ++It;
+ switch (MI-getOpcode()) {
+ default: assert(false Unexpected instr type to insert);
+ case X86::CMOV_FR32:
+ case X86::CMOV_FR64: {
+// To insert a SELECT_CC instruction, we actually have to insert the
diamond
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelPattern.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.31 - 1.32
X86ISelLowering.cpp updated: 1.41 - 1.42
X86ISelPattern.cpp updated: 1.197 - 1.198
---
Log message:
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
---
Diffs of the changes: (+4 -84)
X86ISelDAGToDAG.cpp | 40
X86ISelLowering.cpp |7 ---
X86ISelPattern.cpp | 41 -
3 files changed, 4 insertions(+), 84 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.31
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.32
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.31Sat Jan 14 14:11:13 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Jan 15 03:00:21 2006
@@ -700,46 +700,6 @@
Base, Scale, Index, Disp, Chain);
return Chain;
}
-
-case ISD::DYNAMIC_STACKALLOC: {
- SDOperand Chain = N.getOperand(0);
- SDOperand Size = N.getOperand(1);
- SDOperand Align = N.getOperand(2);
-
- // FIXME: We are currently ignoring the requested alignment for handling
- // greater than the stack alignment. This will need to be revisited at
- // some point.
- if (!isaConstantSDNode(Align) ||
- castConstantSDNode(Align)-getValue() != 0) {
-std::cerr Cannot allocate stack object with greater alignment than
-the stack alignment yet!;
-abort();
- }
-
- // FIXME: This produces crappy code. Lots of unnecessary MOV32rr to and
- // from ESP.
- SDOperand InFlag;
- SDOperand SPVal = CurDAG-getCopyFromReg(Chain, X86::ESP, MVT::i32,
InFlag);
- Chain = SPVal.getValue(1);
- InFlag = SPVal.getValue(2);
-
- SDOperand Result = Select(CurDAG-getNode(X86ISD::SUB_FLAG, MVT::i32,
-SPVal, Size, InFlag));
- InFlag = Result.getValue(1);
-
- // Force the result back into ESP.
- Chain = CurDAG-getCopyToReg(Chain,
-CurDAG-getRegister(X86::ESP, MVT::i32),
-Result, InFlag);
- InFlag = Chain.getValue(1);
-
- // Copy the result back from ESP.
- Result = CurDAG-getCopyFromReg(Chain, X86::ESP, MVT::i32, InFlag);
-
- CodeGenMap[N.getValue(0)] = Result;
- CodeGenMap[N.getValue(1)] = Result.getValue(1);
- return Result.getValue(N.ResNo);
-}
}
return SelectCode(N);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.41
llvm/lib/Target/X86/X86ISelLowering.cpp:1.42
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.41Fri Jan 13 21:14:10 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Jan 15 03:00:21 2006
@@ -162,9 +162,10 @@
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
- // Not implemented yet.
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ // Expand to the default code.
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
if (X86ScalarSSE) {
// Set up the FP register classes.
Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.197
llvm/lib/Target/X86/X86ISelPattern.cpp:1.198
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.197Fri Jan 13 14:19:44 2006
+++ llvm/lib/Target/X86/X86ISelPattern.cpp Sun Jan 15 03:00:21 2006
@@ -2386,46 +2386,6 @@
return Result;
}
- case ISD::DYNAMIC_STACKALLOC:
-// Generate both result values.
-if (Result != 1)
- ExprMap[N.getValue(1)] = 1; // Generate the token
-else
- Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
-// FIXME: We are currently ignoring the requested alignment for handling
-// greater than the stack alignment. This will need to be revisited at
some
-// point. Align = N.getOperand(2);
-
-if (!isaConstantSDNode(N.getOperand(2)) ||
-castConstantSDNode(N.getOperand(2))-getValue() != 0) {
- std::cerr Cannot allocate stack object with greater alignment than
- the stack alignment yet!;
- abort();
-}
-
-if (ConstantSDNode *CN = dyn_castConstantSDNode(N.getOperand(1))) {
- Select(N.getOperand(0));
- BuildMI(BB, X86::SUB32ri, 2, X86::ESP).addReg(X86::ESP)
-.addImm(CN-getValue());
-} else {
- if (getRegPressure(N.getOperand(0)) getRegPressure(N.getOperand(1))) {
-Select(N.getOperand(0));
-Tmp1 = SelectExpr(N.getOperand(1));
- } else {
-Tmp1 = SelectExpr(N.getOperand(1));
-Select(N.getOperand(0));
- }
-
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.30 - 1.31
---
Log message:
silence a warning
---
Diffs of the changes: (+1 -0)
X86ISelDAGToDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.30
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.31
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.30Wed Jan 11 16:15:18 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Jan 14 14:11:13 2006
@@ -682,6 +682,7 @@
Base, Scale, Index, Disp, OldCW, Chain);
switch (Opcode) {
+ default: assert(0 Unknown FP_TO_INT*_IN_MEM);
case X86ISD::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
case X86ISD::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
case X86ISD::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.25 - 1.26
X86ISelLowering.cpp updated: 1.25 - 1.26
X86InstrInfo.td updated: 1.192 - 1.193
---
Log message:
FP_TO_INT*_IN_MEM and x87 FP Select support.
---
Diffs of the changes: (+131 -21)
X86ISelDAGToDAG.cpp | 58
X86ISelLowering.cpp | 53 +--
X86InstrInfo.td | 41 +++-
3 files changed, 131 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.25
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.26
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.25Mon Jan 9 17:10:28 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Jan 10 14:26:56 2006
@@ -18,6 +18,7 @@
#include llvm/GlobalValue.h
#include llvm/CodeGen/MachineConstantPool.h
#include llvm/CodeGen/MachineFunction.h
+#include llvm/CodeGen/MachineFrameInfo.h
#include llvm/CodeGen/SelectionDAGISel.h
#include llvm/Target/TargetMachine.h
#include llvm/Support/Debug.h
@@ -550,6 +551,63 @@
return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
+
+case X86ISD::FP_TO_INT16_IN_MEM:
+case X86ISD::FP_TO_INT32_IN_MEM:
+case X86ISD::FP_TO_INT64_IN_MEM: {
+ assert(N.getOperand(1).getValueType() == MVT::f64);
+
+ // Change the floating point control register to use round towards zero
+ // mode when truncating to an integer value.
+ MachineFunction MF = CurDAG-getMachineFunction();
+ int CWFI = MF.getFrameInfo()-CreateStackObject(2, 2);
+ SDOperand CWSlot = CurDAG-getFrameIndex(CWFI, MVT::i32);
+ SDOperand Base, Scale, Index, Disp;
+ (void)SelectAddr(CWSlot, Base, Scale, Index, Disp);
+ SDOperand Chain = N.getOperand(0);
+
+ // Save the control word.
+ Chain = CurDAG-getTargetNode(X86::FNSTCW16m, MVT::Other,
+Base, Scale, Index, Disp, Chain);
+
+ // Load the old value of the high byte of the control word.
+ SDOperand OldCW =
+CurDAG-getTargetNode(X86::MOV16rm, MVT::i16, MVT::Other,
+ Base, Scale, Index, Disp, Chain);
+ Chain = OldCW.getValue(1);
+
+ // Set the high part to be round to zero...
+ Chain = CurDAG-getTargetNode(X86::MOV16mi, MVT::Other,
+Base, Scale, Index, Disp,
+CurDAG-getConstant(0xC7F, MVT::i16),
+Chain);
+
+ // Reload the modified control word now...
+ Chain = CurDAG-getTargetNode(X86::FLDCW16m, MVT::Other,
+Base, Scale, Index, Disp, Chain);
+
+ // Restore the memory image of control word to original value
+ Chain = CurDAG-getTargetNode(X86::MOV16mr, MVT::Other,
+Base, Scale, Index, Disp, OldCW, Chain);
+
+ switch (Opcode) {
+ case X86ISD::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
+ case X86ISD::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
+ case X86ISD::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
+ }
+
+ SDOperand N1 = Select(N.getOperand(1));
+ SDOperand Base2, Scale2, Index2, Disp2;
+ (void)SelectAddr(N.getOperand(2), Base2, Scale2, Index2, Disp2);
+ Chain = CurDAG-getTargetNode(Opc, MVT::Other,
+Base2, Scale2, Index2, Disp2, N1, Chain);
+
+ // Reload the modified control word now...
+ CodeGenMap[N] =
+Chain = CurDAG-getTargetNode(X86::FLDCW16m, MVT::Other,
+ Base, Scale, Index, Disp, Chain);
+ return Chain;
+}
}
return SelectCode(N);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.25
llvm/lib/Target/X86/X86ISelLowering.cpp:1.26
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.25Mon Jan 9 16:29:54 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Jan 10 14:26:56 2006
@@ -1192,6 +1192,26 @@
return X86CC;
}
+/// SupportedByFPCMOV - is there a floating point cmov for the specific
+/// X86 condition code.
+/// Current x86 isa includes the following FP cmov instructions:
+/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
+static bool SupportedByFPCMOV(unsigned X86CC) {
+ switch (X86CC) {
+ default:
+return false;
+ case X86ISD::COND_B:
+ case X86ISD::COND_BE:
+ case X86ISD::COND_E:
+ case X86ISD::COND_P:
+ case X86ISD::COND_A:
+ case X86ISD::COND_AE:
+ case X86ISD::COND_NE:
+ case X86ISD::COND_NP:
+return true;
+ }
+}
+
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
@@ -1444,21 +1464,32 @@
}
}
case ISD::SELECT: {
-SDOperand Cond = Op.getOperand(0);
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.26 - 1.27
---
Log message:
Fit into 80 cols
---
Diffs of the changes: (+2 -1)
X86ISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.26
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.27
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.26Tue Jan 10 14:26:56 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Jan 10 18:46:55 2006
@@ -315,7 +315,8 @@
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal
addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
/// For X86, it always is unless it's just a (Reg + const).
-bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand
Scale,
+bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand Base,
+SDOperand Scale,
SDOperand Index, SDOperand Disp) {
X86ISelAddressMode AM;
if (!MatchAddress(N, AM)) {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelPattern.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.27 - 1.28
X86ISelPattern.cpp updated: 1.191 - 1.192
---
Log message:
implement FP_REG_KILL insertion for the dag-dag instruction selector
---
Diffs of the changes: (+59 -1)
X86ISelDAGToDAG.cpp | 59
X86ISelPattern.cpp |1
2 files changed, 59 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.27
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.28
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.27Tue Jan 10 18:46:55 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Jan 10 19:15:34 2006
@@ -13,12 +13,17 @@
//===--===//
#include X86.h
+#include X86RegisterInfo.h
#include X86Subtarget.h
#include X86ISelLowering.h
#include llvm/GlobalValue.h
+#include llvm/Instructions.h
+#include llvm/Support/CFG.h
#include llvm/CodeGen/MachineConstantPool.h
#include llvm/CodeGen/MachineFunction.h
#include llvm/CodeGen/MachineFrameInfo.h
+#include llvm/CodeGen/MachineInstrBuilder.h
+#include llvm/CodeGen/SSARegMap.h
#include llvm/CodeGen/SelectionDAGISel.h
#include llvm/Target/TargetMachine.h
#include llvm/Support/Debug.h
@@ -139,6 +144,7 @@
/// when it has created a SelectionDAG for us to codegen.
void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG DAG) {
DEBUG(BB-dump());
+ MachineFunction::iterator FirstMBB = BB;
// Codegen the basic block.
DAG.setRoot(Select(DAG.getRoot()));
@@ -147,6 +153,59 @@
// Emit machine code to BB.
ScheduleAndEmitDAG(DAG);
+
+ // If we are emitting FP stack code, scan the basic block to determine if
this
+ // block defines any FP values. If so, put an FP_REG_KILL instruction before
+ // the terminator of the block.
+ if (X86Vector SSE2) {
+// Note that FP stack instructions *are* used in SSE code when returning
+// values, but these are not live out of the basic block, so we don't need
+// an FP_REG_KILL in this case either.
+bool ContainsFPCode = false;
+
+// Scan all of the machine instructions in these MBBs, checking for FP
+// stores.
+MachineFunction::iterator MBBI = FirstMBB;
+do {
+ for (MachineBasicBlock::iterator I = MBBI-begin(), E = MBBI-end();
+ !ContainsFPCode I != E; ++I) {
+for (unsigned op = 0, e = I-getNumOperands(); op != e; ++op) {
+ if (I-getOperand(op).isRegister() I-getOperand(op).isDef()
+ MRegisterInfo::isVirtualRegister(I-getOperand(op).getReg())
+ RegMap-getRegClass(I-getOperand(0).getReg()) ==
+X86::RFPRegisterClass) {
+ContainsFPCode = true;
+break;
+ }
+}
+ }
+} while (!ContainsFPCode *(MBBI++) != BB);
+
+// Check PHI nodes in successor blocks. These PHI's will be lowered to
have
+// a copy of the input value in this block.
+if (!ContainsFPCode) {
+ // Final check, check LLVM BB's that are successors to the LLVM BB
+ // corresponding to BB for FP PHI nodes.
+ const BasicBlock *LLVMBB = BB-getBasicBlock();
+ const PHINode *PN;
+ for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
+ !ContainsFPCode SI != E; ++SI) {
+for (BasicBlock::const_iterator II = SI-begin();
+ (PN = dyn_castPHINode(II)); ++II) {
+ if (PN-getType()-isFloatingPoint()) {
+ContainsFPCode = true;
+break;
+ }
+}
+ }
+}
+
+// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
+if (ContainsFPCode) {
+ BuildMI(*BB, BB-getFirstTerminator(), X86::FP_REG_KILL, 0);
+ ++NumFPKill;
+}
+ }
}
/// FIXME: copied from X86ISelPattern.cpp
Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.191
llvm/lib/Target/X86/X86ISelPattern.cpp:1.192
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.191Fri Jan 6 11:55:49 2006
+++ llvm/lib/Target/X86/X86ISelPattern.cpp Tue Jan 10 19:15:34 2006
@@ -226,7 +226,6 @@
break;
}
-
// Insert FP_REG_KILL instructions into basic blocks that need them. This
// only occurs due to the floating point stackifier not being aggressive
// enough to handle arbitrary global stackification.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.24 - 1.25
X86InstrInfo.td updated: 1.191 - 1.192
---
Log message:
* Added undef patterns.
* Some reorg.
---
Diffs of the changes: (+83 -68)
X86ISelDAGToDAG.cpp |9 ---
X86InstrInfo.td | 142 ++--
2 files changed, 83 insertions(+), 68 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.24
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.25
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.24Fri Jan 6 17:19:29 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jan 9 17:10:28 2006
@@ -550,15 +550,6 @@
return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
-
-case ISD::UNDEF: {
- Opc = (NVT == MVT::f64) ? (X86Vector = SSE2 ? X86::FLD0SD : X86::FpLD0)
- : X86::IMPLICIT_DEF;
- if (N.Val-hasOneUse())
-return CurDAG-SelectNodeTo(N.Val, Opc, NVT);
- else
-return CodeGenMap[N] = CurDAG-getTargetNode(Opc, NVT);
-}
}
return SelectCode(N);
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.191
llvm/lib/Target/X86/X86InstrInfo.td:1.192
--- llvm/lib/Target/X86/X86InstrInfo.td:1.191 Mon Jan 9 12:33:28 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Jan 9 17:10:28 2006
@@ -368,6 +368,16 @@
[(X86callseq_end imm:$amt1, imm:$amt2)];
def IMPLICIT_USE : I0, Pseudo, (ops variable_ops), #IMPLICIT_USE, [];
def IMPLICIT_DEF : I0, Pseudo, (ops variable_ops), #IMPLICIT_DEF, [];
+def IMPLICIT_DEF_R8 : I0, Pseudo, (ops R8:$dst),
+ #IMPLICIT_DEF $dst,
+ [(set R8:$dst, (undef))];
+def IMPLICIT_DEF_R16 : I0, Pseudo, (ops R16:$dst),
+ #IMPLICIT_DEF $dst,
+ [(set R16:$dst, (undef))];
+def IMPLICIT_DEF_R32 : I0, Pseudo, (ops R32:$dst),
+ #IMPLICIT_DEF $dst,
+ [(set R32:$dst, (undef))];
+
let isTerminator = 1 in
let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
def FP_REG_KILL : I0, Pseudo, (ops), #FP_REG_KILL, [];
@@ -438,11 +448,6 @@
[(X86call (loadi32 addr:$dst))];
}
-def : Pat(X86call tglobaladdr:$dst),
- (CALLpcrel32 tglobaladdr:$dst);
-def : Pat(X86call externalsym:$dst),
- (CALLpcrel32 externalsym:$dst);
-
// Tail call stuff.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
def TAILJMPd : IBr0xE9, (ops calltarget:$dst), jmp $dst # TAIL CALL, [];
@@ -1890,25 +1895,6 @@
} // end Two Address instructions
-// X86 specific add which produces a flag.
-def : Pat(X86addflag R32:$src1, R32:$src2),
- (ADD32rr R32:$src1, R32:$src2);
-def : Pat(X86addflag R32:$src1, (load addr:$src2)),
- (ADD32rm R32:$src1, addr:$src2);
-def : Pat(X86addflag R32:$src1, imm:$src2),
- (ADD32ri R32:$src1, imm:$src2);
-def : Pat(X86addflag R32:$src1, i32immSExt8:$src2),
- (ADD32ri8 R32:$src1, i32immSExt8:$src2);
-
-def : Pat(X86subflag R32:$src1, R32:$src2),
- (SUB32rr R32:$src1, R32:$src2);
-def : Pat(X86subflag R32:$src1, (load addr:$src2)),
- (SUB32rm R32:$src1, addr:$src2);
-def : Pat(X86subflag R32:$src1, imm:$src2),
- (SUB32ri R32:$src1, imm:$src2);
-def : Pat(X86subflag R32:$src1, i32immSExt8:$src2),
- (SUB32ri8 R32:$src1, i32immSExt8:$src2);
-
// Suprisingly enough, these are not two address instructions!
def IMUL16rri : Ii160x69, MRMSrcReg, // R16 = R16*I16
(ops R16:$dst, R16:$src1, i16imm:$src2),
@@ -2284,20 +2270,6 @@
movz{wl|x} {$src, $dst|$dst, $src},
[(set R32:$dst, (zextloadi32i16 addr:$src))], TB;
-// Handling 1 bit zextload and sextload
-def : Pat(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src);
-def : Pat(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src);
-def : Pat(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src);
-def : Pat(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src);
-
-// Handling 1 bit extload
-def : Pat(extloadi8i1 addr:$src), (MOV8rm addr:$src);
-
-// Modeling anyext as zext
-def : Pat(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src);
-def : Pat(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src);
-def : Pat(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src);
-
//===--===//
// XMM Floating point support (requires SSE / SSE2)
//===--===//
@@ -2555,25 +2527,25 @@
// FPI - Floating Point Instruction template.
class FPIbits8 o, Format F, dag ops, string asm : Io, F, ops, asm, [] {}
-// FpI - Floating Point Psuedo Instruction template.
-class FpIdag ops, FPFormat fp, listdag pattern
- : X86Inst0, Pseudo, NoImm,
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.22 - 1.23
---
Log message:
ISEL code for MULHU, MULHS, and UNDEF.
---
Diffs of the changes: (+82 -7)
X86ISelDAGToDAG.cpp | 89 +++-
1 files changed, 82 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.22
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.23
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.22Thu Jan 5 19:06:31 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jan 6 14:36:21 2006
@@ -100,6 +100,8 @@
SDOperand Index, SDOperand Disp);
bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
+bool TryFoldLoad(SDOperand N, SDOperand Base, SDOperand Scale,
+ SDOperand Index, SDOperand Disp);
inline void getAddressOperands(X86ISelAddressMode AM, SDOperand Base,
SDOperand Scale, SDOperand Index,
@@ -294,8 +296,16 @@
return false;
}
-static bool isRegister0(SDOperand Op)
-{
+bool X86DAGToDAGISel::TryFoldLoad(SDOperand N, SDOperand Base,
+ SDOperand Scale, SDOperand Index,
+ SDOperand Disp) {
+ if (N.getOpcode() == ISD::LOAD N.hasOneUse()
+ CodeGenMap.count(N.getValue(1)))
+return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
+ return false;
+}
+
+static bool isRegister0(SDOperand Op) {
if (RegisterSDNode *R = dyn_castRegisterSDNode(Op))
return (R-getReg() == 0);
return false;
@@ -354,14 +364,67 @@
SDOperand X86DAGToDAGISel::Select(SDOperand N) {
SDNode *Node = N.Val;
MVT::ValueType NVT = Node-getValueType(0);
- unsigned Opc;
+ unsigned Opc, MOpc;
+ unsigned Opcode = Node-getOpcode();
- if (Node-getOpcode() = ISD::BUILTIN_OP_END
- Node-getOpcode() X86ISD::FIRST_NUMBER)
+ if (Opcode = ISD::BUILTIN_OP_END Opcode X86ISD::FIRST_NUMBER)
return N; // Already selected.
- switch (Node-getOpcode()) {
+ switch (Opcode) {
default: break;
+case ISD::MULHU:
+case ISD::MULHS: {
+ if (Opcode == ISD::MULHU)
+switch (NVT) {
+default: assert(0 Unsupported VT!);
+case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
+case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
+case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
+}
+ else
+switch (NVT) {
+default: assert(0 Unsupported VT!);
+case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
+case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
+case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
+}
+
+ unsigned LoReg, HiReg;
+ switch (NVT) {
+ default: assert(0 Unsupported VT!);
+ case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
+ case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
+ case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
+ }
+
+ SDOperand N0 = Node-getOperand(0);
+ SDOperand N1 = Node-getOperand(1);
+
+ bool foldedLoad = false;
+ SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
+ foldedLoad = TryFoldLoad(N1, Tmp0, Tmp1, Tmp2, Tmp3);
+ SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
+ : CurDAG-getEntryNode();
+
+ SDOperand InFlag;
+ Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(LoReg, NVT),
+Select(N0), InFlag);
+ InFlag = Chain.getValue(1);
+
+ if (foldedLoad) {
+Chain = CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
+ Tmp2, Tmp3, Chain, InFlag);
+InFlag = Chain.getValue(1);
+ } else {
+InFlag = CurDAG-getTargetNode(Opc, MVT::Flag, Select(N1), InFlag);
+ }
+
+ SDOperand Result = CurDAG-getCopyFromReg(Chain, HiReg, NVT, InFlag);
+ CodeGenMap[N.getValue(0)] = Result;
+ CodeGenMap[N.getValue(1)] = Result.getValue(1);
+ CodeGenMap[N.getValue(2)] = Result.getValue(2);
+ return Result.getValue(N.ResNo);
+}
case ISD::TRUNCATE: {
unsigned Reg;
@@ -387,9 +450,21 @@
Result = CurDAG-getCopyFromReg(Chain,
Reg, VT, InFlag);
- return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
+ if (N.Val-hasOneUse())
+return CurDAG-SelectNodeTo(N.Val, Opc, VT, Result);
+ else
+return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
+
+case ISD::UNDEF: {
+ Opc = (NVT == MVT::f64) ? (X86Vector = SSE2 ? X86::FLD0SD : X86::FpLD0)
+ : X86::IMPLICIT_DEF;
+ if (N.Val-hasOneUse())
+return CurDAG-SelectNodeTo(N.Val, Opc, NVT);
+ else
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.23 - 1.24
---
Log message:
* Added integer div / rem.
* Fixed a load folding bug.
---
Diffs of the changes: (+98 -4)
X86ISelDAGToDAG.cpp | 102 +---
1 files changed, 98 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.23
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.24
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.23Fri Jan 6 14:36:21 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jan 6 17:19:29 2006
@@ -300,7 +300,7 @@
SDOperand Scale, SDOperand Index,
SDOperand Disp) {
if (N.getOpcode() == ISD::LOAD N.hasOneUse()
- CodeGenMap.count(N.getValue(1)))
+ CodeGenMap.count(N.getValue(1)) == 0)
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
return false;
}
@@ -403,6 +403,15 @@
bool foldedLoad = false;
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
foldedLoad = TryFoldLoad(N1, Tmp0, Tmp1, Tmp2, Tmp3);
+ // MULHU and MULHS are commmutative
+ if (!foldedLoad) {
+foldedLoad = TryFoldLoad(N0, Tmp0, Tmp1, Tmp2, Tmp3);
+if (foldedLoad) {
+ N0 = Node-getOperand(1);
+ N1 = Node-getOperand(0);
+}
+ }
+
SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
: CurDAG-getEntryNode();
@@ -421,9 +430,94 @@
SDOperand Result = CurDAG-getCopyFromReg(Chain, HiReg, NVT, InFlag);
CodeGenMap[N.getValue(0)] = Result;
- CodeGenMap[N.getValue(1)] = Result.getValue(1);
- CodeGenMap[N.getValue(2)] = Result.getValue(2);
- return Result.getValue(N.ResNo);
+ if (foldedLoad)
+CodeGenMap[N1.getValue(1)] = Result.getValue(1);
+ return Result;
+}
+
+case ISD::SDIV:
+case ISD::UDIV:
+case ISD::SREM:
+case ISD::UREM: {
+ bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
+ bool isDiv= Opcode == ISD::SDIV || Opcode == ISD::UDIV;
+ if (!isSigned)
+switch (NVT) {
+default: assert(0 Unsupported VT!);
+case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
+case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
+case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
+}
+ else
+switch (NVT) {
+default: assert(0 Unsupported VT!);
+case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
+case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
+case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
+}
+
+ unsigned LoReg, HiReg;
+ unsigned ClrOpcode, SExtOpcode;
+ switch (NVT) {
+ default: assert(0 Unsupported VT!);
+ case MVT::i8:
+LoReg = X86::AL; HiReg = X86::AH;
+ClrOpcode = X86::MOV8ri;
+SExtOpcode = X86::CBW;
+break;
+ case MVT::i16:
+LoReg = X86::AX; HiReg = X86::DX;
+ClrOpcode = X86::MOV16ri;
+SExtOpcode = X86::CWD;
+break;
+ case MVT::i32:
+LoReg = X86::EAX; HiReg = X86::EDX;
+ClrOpcode = X86::MOV32ri;
+SExtOpcode = X86::CDQ;
+break;
+ }
+
+ SDOperand N0 = Node-getOperand(0);
+ SDOperand N1 = Node-getOperand(1);
+
+ bool foldedLoad = false;
+ SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
+ foldedLoad = TryFoldLoad(N1, Tmp0, Tmp1, Tmp2, Tmp3);
+ SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
+ : CurDAG-getEntryNode();
+
+ SDOperand InFlag;
+ Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(LoReg, NVT),
+Select(N0), InFlag);
+ InFlag = Chain.getValue(1);
+
+ if (isSigned) {
+// Sign extend the low part into the high part.
+InFlag = CurDAG-getTargetNode(SExtOpcode, MVT::Flag, InFlag);
+ } else {
+// Zero out the high part, effectively zero extending the input.
+SDOperand ClrNode =
+ CurDAG-getTargetNode(ClrOpcode, NVT,
+CurDAG-getTargetConstant(0, NVT));
+Chain = CurDAG-getCopyToReg(Chain, CurDAG-getRegister(HiReg, NVT),
+ ClrNode, InFlag);
+InFlag = Chain.getValue(1);
+ }
+
+ if (foldedLoad) {
+Chain = CurDAG-getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
+ Tmp2, Tmp3, Chain, InFlag);
+InFlag = Chain.getValue(1);
+ } else {
+InFlag = CurDAG-getTargetNode(Opc, MVT::Flag, Select(N1), InFlag);
+ }
+
+ SDOperand Result = CurDAG-getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
+NVT, InFlag);
+ CodeGenMap[N.getValue(0)] = Result;
+ if
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.21 - 1.22
---
Log message:
fold (shl x, 1) - (add x, x)
---
Diffs of the changes: (+0 -20)
X86ISelDAGToDAG.cpp | 20
1 files changed, 20 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.21
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.22
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.21Wed Jan 4 20:08:37 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jan 5 19:06:31 2006
@@ -363,26 +363,6 @@
switch (Node-getOpcode()) {
default: break;
-case ISD::SHL:
- if (ConstantSDNode *CN = dyn_castConstantSDNode(Node-getOperand(1))) {
-if (CN-getValue() == 1) {
- // X = SHL Y, 1 - X = ADD Y, Y
- switch (NVT) {
-default: assert(0 Cannot shift this type!);
-case MVT::i8: Opc = X86::ADD8rr; break;
-case MVT::i16: Opc = X86::ADD16rr; break;
-case MVT::i32: Opc = X86::ADD32rr; break;
- }
- SDOperand Tmp0 = Select(Node-getOperand(0));
- if (Node-hasOneUse())
-return CurDAG-SelectNodeTo(Node, Opc, NVT, Tmp0, Tmp0);
- else
-return CodeGenMap[N] =
- CurDAG-getTargetNode(Opc, NVT, Tmp0, Tmp0);
-}
- }
- break;
-
case ISD::TRUNCATE: {
unsigned Reg;
MVT::ValueType VT;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.19 - 1.20
X86ISelLowering.cpp updated: 1.18 - 1.19
X86ISelLowering.h updated: 1.9 - 1.10
X86InstrInfo.td updated: 1.186 - 1.187
---
Log message:
DAG based isel call support.
---
Diffs of the changes: (+197 -41)
X86ISelDAGToDAG.cpp | 27 +
X86ISelLowering.cpp | 141
X86ISelLowering.h | 11
X86InstrInfo.td | 59 +
4 files changed, 197 insertions(+), 41 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.19
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.20
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.19Wed Dec 21 17:05:39 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jan 4 18:27:02 2006
@@ -410,6 +410,33 @@
return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
+
+case ISD::ConstantFP: {
+ Opc = 0;
+ if (X86ScalarSSE) {
+assert(castConstantFPSDNode(N)-isExactlyValue(+0.0)
+ SSE only supports +0.0);
+Opc = (NVT == MVT::f32) ? X86::FLD0SS : X86::FLD0SD;
+ }
+
+ if (castConstantFPSDNode(N)-isExactlyValue(+0.0) ||
+ castConstantFPSDNode(N)-isExactlyValue(-0.0))
+Opc = X86::FpLD0;
+ else if (castConstantFPSDNode(N)-isExactlyValue(+1.0) ||
+ castConstantFPSDNode(N)-isExactlyValue(-1.0))
+Opc = X86::FpLD1;
+
+ assert(Opc != 0 Unexpected constant!);
+
+ SDOperand Result = CurDAG-getTargetNode(Opc, NVT);
+
+ if (castConstantFPSDNode(N)-getValue() 0.0 ||
+ castConstantFPSDNode(N)-isExactlyValue(-0.0))
+Result = CurDAG-getTargetNode(X86::FpCHS, NVT, Result);
+
+ CodeGenMap[N] = Result;
+ return Result;
+}
}
return SelectCode(N);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.18
llvm/lib/Target/X86/X86ISelLowering.cpp:1.19
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.18Mon Dec 26 21:02:18 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Jan 4 18:27:02 2006
@@ -457,38 +457,117 @@
RetVals.push_back(MVT::i32);
break;
}
- std::vectorSDOperand Ops;
- Ops.push_back(Chain);
- Ops.push_back(Callee);
- Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
- Ops.push_back(DAG.getConstant(0, getPointerTy()));
- SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
- RetVals, Ops);
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
- SDOperand ResultVal;
- switch (RetTyVT) {
- case MVT::isVoid: break;
- default:
-ResultVal = TheCall.getValue(1);
-break;
- case MVT::i1:
- case MVT::i8:
- case MVT::i16:
-ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
-break;
- case MVT::f32:
-// FIXME: we would really like to remember that this FP_ROUND operation is
-// okay to eliminate if we allow excess FP precision.
-ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
-break;
- case MVT::i64:
-ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
-TheCall.getValue(2));
-break;
- }
+ if (X86DAGIsel) {
+std::vectorMVT::ValueType NodeTys;
+NodeTys.push_back(MVT::Other); // Returns a chain
+NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
- return std::make_pair(ResultVal, Chain);
+std::vectorSDOperand Ops;
+Ops.push_back(Chain);
+Ops.push_back(Callee);
+
+Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
+NodeTys, Ops);
+SDOperand InFlag = Chain.getValue(1);
+
+SDOperand RetVal;
+if (RetTyVT != MVT::isVoid) {
+ switch (RetTyVT) {
+ default: assert(0 Unknown value type to return!);
+ case MVT::i1:
+ case MVT::i8:
+RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
+Chain = RetVal.getValue(1);
+break;
+ case MVT::i16:
+RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
+Chain = RetVal.getValue(1);
+break;
+ case MVT::i32:
+RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
+Chain = RetVal.getValue(1);
+break;
+ case MVT::i64: {
+SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
+SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
+ Lo.getValue(2));
+RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
+Chain = Hi.getValue(1);
+break;
+ }
+ case MVT::f32:
+ case MVT::f64: {
+std::vectorMVT::ValueType Tys;
+Tys.push_back(MVT::f64);
+Tys.push_back(MVT::Other);
+std::vectorSDOperand Ops;
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.20 - 1.21
X86InstrInfo.td updated: 1.187 - 1.188
---
Log message:
Added ConstantFP patterns.
---
Diffs of the changes: (+33 -31)
X86ISelDAGToDAG.cpp | 27 ---
X86InstrInfo.td | 37 +
2 files changed, 33 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.20
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.21
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.20Wed Jan 4 18:27:02 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jan 4 20:08:37 2006
@@ -410,33 +410,6 @@
return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
-
-case ISD::ConstantFP: {
- Opc = 0;
- if (X86ScalarSSE) {
-assert(castConstantFPSDNode(N)-isExactlyValue(+0.0)
- SSE only supports +0.0);
-Opc = (NVT == MVT::f32) ? X86::FLD0SS : X86::FLD0SD;
- }
-
- if (castConstantFPSDNode(N)-isExactlyValue(+0.0) ||
- castConstantFPSDNode(N)-isExactlyValue(-0.0))
-Opc = X86::FpLD0;
- else if (castConstantFPSDNode(N)-isExactlyValue(+1.0) ||
- castConstantFPSDNode(N)-isExactlyValue(-1.0))
-Opc = X86::FpLD1;
-
- assert(Opc != 0 Unexpected constant!);
-
- SDOperand Result = CurDAG-getTargetNode(Opc, NVT);
-
- if (castConstantFPSDNode(N)-getValue() 0.0 ||
- castConstantFPSDNode(N)-isExactlyValue(-0.0))
-Result = CurDAG-getTargetNode(X86::FpCHS, NVT, Result);
-
- CodeGenMap[N] = Result;
- return Result;
-}
}
return SelectCode(N);
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.187
llvm/lib/Target/X86/X86InstrInfo.td:1.188
--- llvm/lib/Target/X86/X86InstrInfo.td:1.187 Wed Jan 4 18:27:02 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Wed Jan 4 20:08:37 2006
@@ -244,6 +244,26 @@
return (unsigned)N-getValue() == (unsigned char)N-getValue();
}];
+def fp32imm0 : PatLeaf(f32 fpimm), [{
+ return N-isExactlyValue(+0.0);
+}];
+
+def fp64imm0 : PatLeaf(f64 fpimm), [{
+ return N-isExactlyValue(+0.0);
+}];
+
+def fp64immneg0 : PatLeaf(f64 fpimm), [{
+ return N-isExactlyValue(-0.0);
+}];
+
+def fp64imm1 : PatLeaf(f64 fpimm), [{
+ return N-isExactlyValue(+1.0);
+}];
+
+def fp64immneg1 : PatLeaf(f64 fpimm), [{
+ return N-isExactlyValue(-1.0);
+}];
+
// Helper fragments for loads.
def loadi8 : PatFrag(ops node:$ptr), (i8 (load node:$ptr));
def loadi16 : PatFrag(ops node:$ptr), (i16 (load node:$ptr));
@@ -2187,9 +2207,13 @@
// Pseudo-instructions that map fld0 to xorps/xorpd for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
def FLD0SS : I0x57, MRMSrcReg, (ops FR32:$dst),
- xorps $dst, $dst, [], Requires[HasSSE1], TB;
+ xorps $dst, $dst,
+ [(set FR32:$dst, fp32imm0)],
+ Requires[HasSSE1], TB;
def FLD0SD : I0x57, MRMSrcReg, (ops FR64:$dst),
- xorpd $dst, $dst, [], Requires[HasSSE2], TB, OpSize;
+ xorpd $dst, $dst,
+ [(set FR64:$dst, fp64imm0)],
+ Requires[HasSSE2], TB, OpSize;
let isTwoAddress = 1 in {
// SSE Scalar Arithmetic
@@ -2568,8 +2592,13 @@
def FXCH: FPI0xC8, AddRegFrm, (ops RST:$op), fxch $op, D9;
// Floating point constant loads.
-def FpLD0 : FpI(ops RFP:$dst), ZeroArgFP, [];
-def FpLD1 : FpI(ops RFP:$dst), ZeroArgFP, [];
+def FpLD0 : FpI(ops RFP:$dst), ZeroArgFP,
+[(set RFP:$dst, fp64imm0)];
+def FpLD1 : FpI(ops RFP:$dst), ZeroArgFP,
+[(set RFP:$dst, fp64imm1)];
+
+def : Pat(f64 fp64immneg0), (FpCHS (FpLD0)), Requires[FPStack];
+def : Pat(f64 fp64immneg1), (FpCHS (FpLD1)), Requires[FPStack];
def FLD0 : FPI0xEE, RawFrm, (ops), fldz, D9;
def FLD1 : FPI0xE8, RawFrm, (ops), fld1, D9;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.18 - 1.19
X86ISelLowering.cpp updated: 1.14 - 1.15
X86ISelLowering.h updated: 1.7 - 1.8
X86InstrInfo.td updated: 1.181 - 1.182
---
Log message:
* Fix a GlobalAddress lowering bug.
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
---
Diffs of the changes: (+29 -5)
X86ISelDAGToDAG.cpp |1 +
X86ISelLowering.cpp | 23 ---
X86ISelLowering.h |6 ++
X86InstrInfo.td |4 ++--
4 files changed, 29 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.18
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.19
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.18Tue Dec 20 20:41:57 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Dec 21 17:05:39 2005
@@ -172,6 +172,7 @@
break;
case ISD::GlobalAddress:
+ case ISD::TargetGlobalAddress:
if (AM.GV == 0) {
AM.GV = castGlobalAddressSDNode(N)-getGlobal();
return false;
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.14
llvm/lib/Target/X86/X86ISelLowering.cpp:1.15
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.14Wed Dec 21 14:51:37 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Dec 21 17:05:39 2005
@@ -122,6 +122,7 @@
setOperationAction(ISD::SETCC , MVT::i8 , Custom);
setOperationAction(ISD::SETCC , MVT::i16 , Custom);
setOperationAction(ISD::SETCC , MVT::i32 , Custom);
+setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
}
// We don't have line number support yet.
@@ -1051,6 +1052,7 @@
}
case ISD::GlobalAddress:
GlobalValue *GV = castGlobalAddressSDNode(Op)-getGlobal();
+SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy());
// For Darwin, external and weak symbols are indirect, so we want to load
// the value at address GV, not the value of GV itself. This means that
// the GlobalAddress must be in the base or index register of the address,
@@ -1058,10 +1060,10 @@
if (getTargetMachine().
getSubtargetX86Subtarget().getIndirectExternAndWeakGlobals()
(GV-hasWeakLinkage() || GV-isExternal()))
- return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Op,
- DAG.getSrcValue(NULL));
+ return DAG.getLoad(MVT::i32, DAG.getEntryNode(),
+ GVOp, DAG.getSrcValue(NULL));
else
- return Op;
+ return GVOp;
break;
}
}
@@ -1086,3 +1088,18 @@
case X86ISD::RET_FLAG: return X86ISD::RET_FLAG;
}
}
+
+bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand Op,
+ uint64_t Mask) const {
+
+ unsigned Opc = Op.getOpcode();
+
+ switch (Opc) {
+ default:
+assert(Opc = ISD::BUILTIN_OP_END Expected a target specific node);
+break;
+ case X86ISD::SETCC: return (Mask 1) == 0;
+ }
+
+ return false;
+}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.7
llvm/lib/Target/X86/X86ISelLowering.h:1.8
--- llvm/lib/Target/X86/X86ISelLowering.h:1.7 Wed Dec 21 14:21:51 2005
+++ llvm/lib/Target/X86/X86ISelLowering.h Wed Dec 21 17:05:39 2005
@@ -155,6 +155,12 @@
/// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
+/// isMaskedValueZeroForTargetNode - Return true if 'Op Mask' is known to
+/// be zero. Op is expected to be a target specific node. Used by DAG
+/// combiner.
+virtual bool isMaskedValueZeroForTargetNode(const SDOperand Op,
+uint64_t Mask) const;
+
SDOperand getReturnAddressFrameIndex(SelectionDAG DAG);
private:
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.181
llvm/lib/Target/X86/X86InstrInfo.td:1.182
--- llvm/lib/Target/X86/X86InstrInfo.td:1.181 Wed Dec 21 16:22:16 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Wed Dec 21 17:05:39 2005
@@ -98,8 +98,8 @@
// Define X86 specific addressing mode.
def addr: ComplexPatterni32, 4, SelectAddr, [];
def leaaddr : ComplexPatterni32, 4, SelectLEAAddr,
- [add,
- frameindex, constpool, globaladdr, externalsym];
+ [add, frameindex, constpool,
+ globaladdr, tglobaladdr, externalsym];
//===--===//
// X86 Instruction Format Definitions.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.16 - 1.17
X86ISelLowering.cpp updated: 1.11 - 1.12
X86ISelLowering.h updated: 1.5 - 1.6
X86InstrInfo.td updated: 1.175 - 1.176
X86RegisterInfo.td updated: 1.25 - 1.26
---
Log message:
* Added lowering hook for external weak global address. It inserts a load
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
---
Diffs of the changes: (+135 -22)
X86ISelDAGToDAG.cpp | 17 ---
X86ISelLowering.cpp | 79
X86ISelLowering.h | 17 +++
X86InstrInfo.td | 37 +---
X86RegisterInfo.td |7 +++-
5 files changed, 135 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.16
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.17
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.16Mon Dec 19 16:36:02 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Dec 20 20:39:21 2005
@@ -173,22 +173,7 @@
case ISD::GlobalAddress:
if (AM.GV == 0) {
- GlobalValue *GV = castGlobalAddressSDNode(N)-getGlobal();
- // For Darwin, external and weak symbols are indirect, so we want to load
- // the value at address GV, not the value of GV itself. This means that
- // the GlobalAddress must be in the base or index register of the
address,
- // not the GV offset field.
- if (Subtarget-getIndirectExternAndWeakGlobals()
- (GV-hasWeakLinkage() || GV-isExternal())) {
-AM.Base.Reg =
- CurDAG-getTargetNode(X86::MOV32rm, MVT::i32, MVT::Other,
-CurDAG-getRegister(0, MVT::i32),
-getI8Imm(1), CurDAG-getRegister(0, MVT::i32),
-CurDAG-getTargetGlobalAddress(GV, MVT::i32),
-CurDAG-getEntryNode());
- } else {
-AM.GV = GV;
- }
+ AM.GV = castGlobalAddressSDNode(N)-getGlobal();
return false;
}
break;
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.11
llvm/lib/Target/X86/X86ISelLowering.cpp:1.12
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.11Tue Dec 20 00:22:03 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Dec 20 20:39:21 2005
@@ -197,6 +197,68 @@
return LowerallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args,
DAG);
}
+SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
+ SelectionDAG DAG) {
+ if (!X86DAGIsel)
+return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
+
+ SDOperand Copy;
+ MVT::ValueType OpVT = Op.getValueType();
+ switch (OpVT) {
+default: assert(0 Unknown type to return!);
+case MVT::i32:
+ Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
+ break;
+case MVT::i64: {
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
+ DAG.getConstant(1, MVT::i32));
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
+ DAG.getConstant(0, MVT::i32));
+ Copy = DAG.getCopyToReg(Chain, X86::EAX, Hi, SDOperand());
+ Copy = DAG.getCopyToReg(Copy, X86::EDX, Lo, Copy.getValue(1));
+ break;
+}
+case MVT::f32:
+ assert(X86ScalarSSE MVT::f32 only legal with scalar sse fp);
+ // Fallthrough intended
+case MVT::f64:
+ if (!X86ScalarSSE) {
+std::vectorMVT::ValueType Tys;
+Tys.push_back(MVT::Other);
+Tys.push_back(MVT::Flag);
+std::vectorSDOperand Ops;
+Ops.push_back(Chain);
+Ops.push_back(Op);
+Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
+ } else {
+// Spill the value to memory and reload it into top of stack.
+unsigned Size = MVT::getSizeInBits(OpVT)/8;
+MachineFunction MF = DAG.getMachineFunction();
+int SSFI = MF.getFrameInfo()-CreateStackObject(Size, Size);
+SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
+StackSlot, DAG.getSrcValue(NULL));
+std::vectorMVT::ValueType Tys;
+Tys.push_back(MVT::f64);
+Tys.push_back(MVT::Other);
+std::vectorSDOperand Ops;
+Ops.push_back(Chain);
+Ops.push_back(StackSlot);
+Ops.push_back(DAG.getValueType(OpVT));
+Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
+Tys.clear();
+Tys.push_back(MVT::Other);
+Tys.push_back(MVT::Flag);
+Ops.clear();
+Ops.push_back(Copy.getValue(1));
+Ops.push_back(Copy);
+Copy =
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.17 - 1.18
---
Log message:
Remove ISD::RET select code. Now tblgen'd.
---
Diffs of the changes: (+0 -41)
X86ISelDAGToDAG.cpp | 41 -
1 files changed, 41 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.17
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.18
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.17Tue Dec 20 20:39:21 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Dec 20 20:41:57 2005
@@ -409,47 +409,6 @@
return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
-
-case ISD::RET: {
- SDOperand Chain = Node-getOperand(0); // Token chain.
- unsigned NumOps = Node-getNumOperands();
-
- // Note: A bit of a hack / optimization... Try to delay chain selection
- // as much as possible. So it's more likely it has already been selected
- // for a real use.
- switch (NumOps) {
-default:
- assert(0 Unknown return instruction!);
-case 3:
- Chain = Select(Chain);
- assert(0 Not yet handled return instruction!);
- break;
-case 2: {
- SDOperand Val = Select(Node-getOperand(1));
- Chain = Select(Chain);
- switch (Node-getOperand(1).getValueType()) {
-default:
- assert(0 All other types should have been promoted!!);
-case MVT::i32:
- Chain = CurDAG-getCopyToReg(Chain, X86::EAX, Val);
- break;
-case MVT::f32:
-case MVT::f64:
- assert(0 Not yet handled return instruction!);
- break;
- }
-}
-case 1:
- Chain = Select(Chain);
- break;
- }
- if (X86Lowering.getBytesToPopOnReturn() == 0)
-return CurDAG-SelectNodeTo(Node, X86::RET, MVT::Other, Chain);
- else
-return CurDAG-SelectNodeTo(Node, X86::RET, MVT::Other,
- getI16Imm(X86Lowering.getBytesToPopOnReturn()),
-Chain);
-}
}
return SelectCode(N);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.15 - 1.16 --- Log message: It's essential we clear CodeGenMap after isel every basic block! --- Diffs of the changes: (+1 -0) X86ISelDAGToDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.15 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.16 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.15Sat Dec 17 03:13:43 2005 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Dec 19 16:36:02 2005 @@ -139,6 +139,7 @@ // Codegen the basic block. DAG.setRoot(Select(DAG.getRoot())); + CodeGenMap.clear(); DAG.RemoveDeadNodes(); // Emit machine code to BB. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.14 - 1.15
---
Log message:
Darwin API issue: indirect load of external and weak symbols.
---
Diffs of the changes: (+8 -3)
X86ISelDAGToDAG.cpp | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.14
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.15
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.14Fri Dec 16 20:02:50 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Dec 17 03:13:43 2005
@@ -106,7 +106,7 @@
SDOperand Disp) {
Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
CurDAG-getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) :
AM.Base.Reg;
- Scale = getI8Imm (AM.Scale);
+ Scale = getI8Imm(AM.Scale);
Index = AM.IndexReg;
Disp = AM.GV ? CurDAG-getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
: getI32Imm(AM.Disp);
@@ -179,11 +179,16 @@
// not the GV offset field.
if (Subtarget-getIndirectExternAndWeakGlobals()
(GV-hasWeakLinkage() || GV-isExternal())) {
-break;
+AM.Base.Reg =
+ CurDAG-getTargetNode(X86::MOV32rm, MVT::i32, MVT::Other,
+CurDAG-getRegister(0, MVT::i32),
+getI8Imm(1), CurDAG-getRegister(0, MVT::i32),
+CurDAG-getTargetGlobalAddress(GV, MVT::i32),
+CurDAG-getEntryNode());
} else {
AM.GV = GV;
-return false;
}
+ return false;
}
break;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.11 - 1.12
X86ISelLowering.cpp updated: 1.6 - 1.7
X86InstrInfo.td updated: 1.168 - 1.169
---
Log message:
* Promote all 1 bit entities to 8 bit.
* Handling extload (1 bit - 8 bit) and remove C++ code that handle 1 bit
zextload.
---
Diffs of the changes: (+5 -113)
X86ISelDAGToDAG.cpp | 107
X86ISelLowering.cpp |3 -
X86InstrInfo.td |8 ++-
3 files changed, 5 insertions(+), 113 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.11
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.12
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.11Wed Dec 14 19:02:48 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Dec 15 13:49:23 2005
@@ -22,7 +22,6 @@
#include llvm/Target/TargetMachine.h
#include llvm/Support/Debug.h
#include llvm/ADT/Statistic.h
-#include set
using namespace llvm;
//===--===//
@@ -96,8 +95,6 @@
private:
SDOperand Select(SDOperand N);
-bool isFoldableLoad(SDOperand Op, SDOperand OtherOp,
-bool FloatPromoteOk = false);
bool MatchAddress(SDOperand N, X86ISelAddressMode AM);
bool SelectAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
@@ -362,68 +359,6 @@
return false;
}
-/// NodeTransitivelyUsesValue - Return true if N or any of its uses uses Op.
-/// The DAG cannot have cycles in it, by definition, so the visited set is not
-/// needed to prevent infinite loops. The DAG CAN, however, have unbounded
-/// reuse, so it prevents exponential cases.
-///
-static bool NodeTransitivelyUsesValue(SDOperand N, SDOperand Op,
- std::setSDNode* Visited) {
- if (N == Op) return true;// Found it.
- SDNode *Node = N.Val;
- if (Node-getNumOperands() == 0 || // Leaf?
- Node-getNodeDepth() = Op.getNodeDepth()) return false; // Can't find
it?
- if (!Visited.insert(Node).second) return false; // Already visited?
-
- // Recurse for the first N-1 operands.
- for (unsigned i = 1, e = Node-getNumOperands(); i != e; ++i)
-if (NodeTransitivelyUsesValue(Node-getOperand(i), Op, Visited))
- return true;
-
- // Tail recurse for the last operand.
- return NodeTransitivelyUsesValue(Node-getOperand(0), Op, Visited);
-}
-
-/// isFoldableLoad - Return true if this is a load instruction that can safely
-/// be folded into an operation that uses it.
-bool X86DAGToDAGISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp,
- bool FloatPromoteOk) {
- if (Op.getOpcode() == ISD::LOAD) {
-// FIXME: currently can't fold constant pool indexes.
-if (isaConstantPoolSDNode(Op.getOperand(1)))
- return false;
- } else if (FloatPromoteOk Op.getOpcode() == ISD::EXTLOAD
- castVTSDNode(Op.getOperand(3))-getVT() == MVT::f32) {
-// FIXME: currently can't fold constant pool indexes.
-if (isaConstantPoolSDNode(Op.getOperand(1)))
- return false;
- } else {
-return false;
- }
-
- // If this load has already been emitted, we clearly can't fold it.
- assert(Op.ResNo == 0 Not a use of the value of the load?);
- if (CodeGenMap.count(Op.getValue(1))) return false;
- assert(!CodeGenMap.count(Op.getValue(0))
- Value in map but not token chain?);
- assert(!CodeGenMap.count(Op.getValue(1))
- Token lowered but value not in map?);
-
- // If there is not just one use of its value, we cannot fold.
- if (!Op.Val-hasNUsesOfValue(1, 0)) return false;
-
- // Finally, we cannot fold the load into the operation if this would induce a
- // cycle into the resultant dag. To check for this, see if OtherOp (the
other
- // operand of the operation we are folding the load into) can possible use
the
- // chain node defined by the load.
- if (OtherOp.Val !Op.Val-hasNUsesOfValue(0, 1)) { // Has uses of chain?
-std::setSDNode* Visited;
-if (NodeTransitivelyUsesValue(OtherOp, Op.getValue(1), Visited))
- return false;
- }
- return true;
-}
-
SDOperand X86DAGToDAGISel::Select(SDOperand N) {
SDNode *Node = N.Val;
MVT::ValueType NVT = Node-getValueType(0);
@@ -455,48 +390,6 @@
}
break;
-case ISD::ANY_EXTEND: // treat any extend like zext
-case ISD::ZERO_EXTEND: {
- SDOperand N0 = N.getOperand(0);
- if (N0.getValueType() == MVT::i1) {
-// FIXME: This hack is here for zero extension casts from bool to i8.
-// This would not be needed if bools were promoted by Legalize.
-if (NVT == MVT::i8) {
- Opc = X86::MOV8rr;
-} else if (!isFoldableLoad(N0, SDOperand())) {
- switch (NVT) {
-default: assert(0 Cannot zero extend to this type!);
-case MVT::i16: Opc = X86::MOVZX16rr8; break;
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.8 - 1.9
---
Log message:
For ISD::RET, if # of operands = 2, try selection the real data dep. operand
first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
---
Diffs of the changes: (+10 -2)
X86ISelDAGToDAG.cpp | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.8
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.9
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.8 Fri Dec 9 18:48:20 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Dec 12 14:32:18 2005
@@ -356,15 +356,22 @@
break;
case ISD::RET: {
- SDOperand Chain = Select(N-getOperand(0)); // Token chain.
- switch (N-getNumOperands()) {
+ SDOperand Chain = N-getOperand(0); // Token chain.
+ unsigned NumOps = N-getNumOperands();
+
+ // Note: A bit of a hack / optimization... Try to delay chain selection
+ // as much as possible. So it's more likely it has already been selected
+ // for a real use.
+ switch (NumOps) {
default:
assert(0 Unknown return instruction!);
case 3:
+ Chain = Select(Chain);
assert(0 Not yet handled return instruction!);
break;
case 2: {
SDOperand Val = Select(N-getOperand(1));
+ Chain = Select(Chain);
switch (N-getOperand(1).getValueType()) {
default:
assert(0 All other types should have been promoted!!);
@@ -378,6 +385,7 @@
}
}
case 1:
+ Chain = Select(Chain);
break;
}
if (X86Lowering.getBytesToPopOnReturn() == 0)
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.9 - 1.10
---
Log message:
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
base or index operands being selected.
---
Diffs of the changes: (+48 -17)
X86ISelDAGToDAG.cpp | 65 ++--
1 files changed, 48 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.9
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.10
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.9 Mon Dec 12 14:32:18 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Dec 12 15:49:40 2005
@@ -101,6 +101,17 @@
bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
SDOperand Index, SDOperand Disp);
+inline void getAddressOperands(X86ISelAddressMode AM, SDOperand Base,
+ SDOperand Scale, SDOperand Index,
+ SDOperand Disp) {
+ Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
+CurDAG-getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) :
AM.Base.Reg;
+ Scale = getI8Imm (AM.Scale);
+ Index = AM.IndexReg;
+ Disp = AM.GV ? CurDAG-getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
+: getI32Imm(AM.Disp);
+}
+
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDOperand getI8Imm(unsigned Imm) {
@@ -285,12 +296,7 @@
else
AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
-Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
- CurDAG-getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
-Scale = getI8Imm (AM.Scale);
-Index = AM.IndexReg;
-Disp = AM.GV ? CurDAG-getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
- : getI32Imm(AM.Disp);
+getAddressOperands(AM, Base, Scale, Index, Disp);
return true;
}
return false;
@@ -308,24 +314,49 @@
/// For X86, it always is unless it's just a (Reg + const).
bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand
Scale,
SDOperand Index, SDOperand Disp) {
- if (SelectAddr(N, Base, Scale, Index, Disp)) {
-if (!isRegister0(Base)) {
+ X86ISelAddressMode AM;
+ if (!MatchAddress(N, AM)) {
+bool SelectBase = false;
+bool SelectIndex = false;
+bool Check = false;
+if (AM.BaseType == X86ISelAddressMode::RegBase) {
+ if (AM.Base.Reg.Val) {
+Check = true;
+SelectBase = true;
+ } else {
+AM.Base.Reg = CurDAG-getRegister(0, MVT::i32);
+ }
+}
+
+if (AM.IndexReg.Val) {
+ SelectIndex = true;
+} else {
+ AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
+}
+
+if (Check) {
unsigned Complexity = 0;
- if ((unsigned)castConstantSDNode(Scale)-getValue() 1)
+ if (AM.Scale 1)
Complexity++;
- if (!isRegister0(Index))
+ if (SelectIndex)
Complexity++;
- if (ConstantSDNode *CN = dyn_castConstantSDNode(Disp)) {
-if (!CN-isNullValue()) Complexity++;
- } else {
+ if (AM.GV)
Complexity++;
- }
- return (Complexity 1);
+ else if (AM.Disp 1)
+Complexity++;
+ if (Complexity = 1)
+return false;
}
+
+if (SelectBase)
+ AM.Base.Reg = Select(AM.Base.Reg);
+if (SelectIndex)
+ AM.IndexReg = Select(AM.IndexReg);
+
+getAddressOperands(AM, Base, Scale, Index, Disp);
return true;
- } else {
-return false;
}
+ return false;
}
SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.7 - 1.8
X86InstrInfo.td updated: 1.151 - 1.152
---
Log message:
* Added X86 store patterns.
* Added X86 dec patterns.
---
Diffs of the changes: (+19 -43)
X86ISelDAGToDAG.cpp | 33 -
X86InstrInfo.td | 29 +++--
2 files changed, 19 insertions(+), 43 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.7
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.7 Wed Dec 7 20:01:35 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Dec 9 18:48:20 2005
@@ -387,39 +387,6 @@
getI16Imm(X86Lowering.getBytesToPopOnReturn()),
Chain);
}
-
-case ISD::STORE: {
- SDOperand Chain = Select(N-getOperand(0)); // Token chain.
- SDOperand Tmp1 = Select(N-getOperand(1));
- Opc = 0;
- if (ConstantSDNode *CN = dyn_castConstantSDNode(N-getOperand(1))) {
-switch (CN-getValueType(0)) {
- default: assert(0 Invalid type for operation!);
- case MVT::i1:
- case MVT::i8: Opc = X86::MOV8mi; break;
- case MVT::i16: Opc = X86::MOV16mi; break;
- case MVT::i32: Opc = X86::MOV32mi; break;
-}
- }
-
- if (!Opc) {
-switch (N-getOperand(1).getValueType()) {
- default: assert(0 Cannot store this type!);
- case MVT::i1:
- case MVT::i8: Opc = X86::MOV8mr; break;
- case MVT::i16: Opc = X86::MOV16mr; break;
- case MVT::i32: Opc = X86::MOV32mr; break;
- case MVT::f32: Opc = X86::MOVSSmr; break;
- case MVT::f64: Opc = X86::FST64m; break;
-}
- }
-
- SDOperand Base, Scale, Index, Disp;
- SelectAddr(N-getOperand(2), Base, Scale, Index, Disp);
- return CurDAG-SelectNodeTo(N, Opc, MVT::Other,
- Base, Scale, Index, Disp, Tmp1, Chain)
-.getValue(Op.ResNo);
-}
}
return SelectCode(Op);
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.151
llvm/lib/Target/X86/X86InstrInfo.td:1.152
--- llvm/lib/Target/X86/X86InstrInfo.td:1.151 Fri Dec 9 16:48:48 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Dec 9 18:48:20 2005
@@ -378,11 +378,14 @@
mov{l} {$src, $dst|$dst, $src},
[(set R32:$dst, imm:$src)];
def MOV8mi : Ii8 0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
- mov{b} {$src, $dst|$dst, $src}, [];
+ mov{b} {$src, $dst|$dst, $src},
+ [(store (i8 imm:$src), addr:$dst)];
def MOV16mi : Ii160xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
- mov{w} {$src, $dst|$dst, $src}, [], OpSize;
+ mov{w} {$src, $dst|$dst, $src},
+ [(store (i16 imm:$src), addr:$dst)], OpSize;
def MOV32mi : Ii320xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
- mov{l} {$src, $dst|$dst, $src}, [];
+ mov{l} {$src, $dst|$dst, $src},
+ [(store (i32 imm:$src), addr:$dst)];
def MOV8rm : I0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
mov{b} {$src, $dst|$dst, $src},
@@ -395,11 +398,14 @@
[(set R32:$dst, (load addr:$src))];
def MOV8mr : I0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
-mov{b} {$src, $dst|$dst, $src}, [];
+mov{b} {$src, $dst|$dst, $src},
+[(store R8:$src, addr:$dst)];
def MOV16mr : I0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
-mov{w} {$src, $dst|$dst, $src}, [], OpSize;
+mov{w} {$src, $dst|$dst, $src},
+[(store R16:$src, addr:$dst)], OpSize;
def MOV32mr : I0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
-mov{l} {$src, $dst|$dst, $src}, [];
+mov{l} {$src, $dst|$dst, $src},
+[(store R32:$src, addr:$dst)];
//===--===//
// Fixed-Register Multiplication and Division Instructions...
@@ -687,6 +693,7 @@
def NOT32m : I0xF7, MRM2m, (ops i32mem:$dst), not{l} $dst, [];
}
+// TODO: inc/dec is slow for P4, but fast for Pentium-M.
def INC8r : I0xFE, MRM0r, (ops R8 :$dst, R8 :$src), inc{b} $dst,
[(set R8:$dst, (add R8:$src, 1))];
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
@@ -701,11 +708,13 @@
def INC32m : I0xFF, MRM0m, (ops i32mem:$dst), inc{l} $dst, [];
}
-def DEC8r : I0xFE, MRM1r, (ops R8 :$dst, R8 :$src), dec{b} $dst, [];
+def DEC8r : I0xFE, MRM1r, (ops R8 :$dst, R8 :$src), dec{b} $dst,
+ [(set R8:$dst, (add R8:$src, -1))];
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
-def DEC16r : I0xFF, MRM1r, (ops R16:$dst, R16:$src), dec{w}
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.6 - 1.7
X86InstrInfo.td updated: 1.148 - 1.149
---
Log message:
* Added intelligence to X86 LEA addressing mode matching routine so it returns
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
---
Diffs of the changes: (+103 -84)
X86ISelDAGToDAG.cpp | 158 +++-
X86InstrInfo.td | 29 +
2 files changed, 103 insertions(+), 84 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.6
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.7
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.6 Wed Nov 30 18:43:55 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Dec 7 20:01:35 2005
@@ -36,6 +36,7 @@
enum {
RegBase,
FrameIndexBase,
+ ConstantPoolBase
} BaseType;
struct {// This is really a union, discriminated by BaseType!
@@ -94,8 +95,11 @@
private:
SDOperand Select(SDOperand N);
-void SelectAddress(SDOperand N, X86ISelAddressMode AM);
bool MatchAddress(SDOperand N, X86ISelAddressMode AM);
+bool SelectAddr(SDOperand N, SDOperand Base, SDOperand Scale,
+SDOperand Index, SDOperand Disp);
+bool SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand Scale,
+ SDOperand Index, SDOperand Disp);
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
@@ -130,23 +134,6 @@
ScheduleAndEmitDAG(DAG);
}
-/// SelectAddress - Pattern match the maximal addressing mode for this node.
-void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode AM) {
- MatchAddress(N, AM);
-
- if (AM.BaseType == X86ISelAddressMode::RegBase) {
-if (AM.Base.Reg.Val)
- AM.Base.Reg = Select(AM.Base.Reg);
-else
- AM.Base.Reg = CurDAG-getRegister(0, MVT::i32);
- }
- if (!AM.IndexReg.Val) {
-AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
- } else {
-AM.IndexReg = Select(AM.IndexReg);
- }
-}
-
/// FIXME: copied from X86ISelPattern.cpp
/// MatchAddress - Add the specified node to the specified addressing mode,
/// returning true if it cannot be done. This just pattern matches for the
@@ -161,6 +148,17 @@
return false;
}
break;
+
+ case ISD::ConstantPool:
+if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
+ if (ConstantPoolSDNode *CP = dyn_castConstantPoolSDNode(N)) {
+AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
+AM.Base.Reg = CurDAG-getTargetConstantPool(CP-get(), MVT::i32);
+return false;
+ }
+}
+break;
+
case ISD::GlobalAddress:
if (AM.GV == 0) {
GlobalValue *GV = castGlobalAddressSDNode(N)-getGlobal();
@@ -177,9 +175,11 @@
}
}
break;
+
case ISD::Constant:
AM.Disp += castConstantSDNode(N)-getValue();
return false;
+
case ISD::SHL:
if (AM.IndexReg.Val == 0 AM.Scale == 1)
if (ConstantSDNode *CN = dyn_castConstantSDNode(N.Val-getOperand(1)))
{
@@ -204,6 +204,7 @@
}
}
break;
+
case ISD::MUL:
// X*[3,5,9] - X+X*[2,4,8]
if (AM.IndexReg.Val == 0 AM.BaseType == X86ISelAddressMode::RegBase
@@ -266,6 +267,67 @@
return false;
}
+/// SelectAddr - returns true if it is able pattern match an addressing mode.
+/// It returns the operands which make up the maximal addressing mode it can
+/// match by reference.
+bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand Base, SDOperand
Scale,
+ SDOperand Index, SDOperand Disp) {
+ X86ISelAddressMode AM;
+ if (!MatchAddress(N, AM)) {
+if (AM.BaseType == X86ISelAddressMode::RegBase) {
+ if (AM.Base.Reg.Val)
+AM.Base.Reg = Select(AM.Base.Reg);
+ else
+AM.Base.Reg = CurDAG-getRegister(0, MVT::i32);
+}
+if (AM.IndexReg.Val)
+ AM.IndexReg = Select(AM.IndexReg);
+else
+ AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
+
+Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
+ CurDAG-getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
+Scale = getI8Imm (AM.Scale);
+Index = AM.IndexReg;
+Disp = AM.GV ? CurDAG-getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
+ : getI32Imm(AM.Disp);
+return true;
+ }
+ return false;
+}
+
+static bool isRegister0(SDOperand Op)
+{
+ if (RegisterSDNode *R = dyn_castRegisterSDNode(Op))
+return (R-getReg() == 0);
+ return false;
+}
+
+/// SelectLEAAddr - it calls SelectAddr and determines if the maximal
addressing
+/// mode it matches can be cost effectively emitted as an LEA instruction.
+/// For X86, it always is unless it's just a (Reg + const).
+bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand Base, SDOperand
Scale,
+SDOperand Index, SDOperand Disp) {
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.4 - 1.5
---
Log message:
SelectNodeTo now returns its result, we must pay attention to it.
---
Diffs of the changes: (+18 -20)
X86ISelDAGToDAG.cpp | 38 ++
1 files changed, 18 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.4
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.5
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.4 Tue Nov 29 20:51:20 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Nov 30 16:59:19 2005
@@ -289,8 +289,7 @@
case MVT::i32: Opc = X86::ADD32rr; break;
}
SDOperand Tmp0 = Select(N-getOperand(0));
- CurDAG-SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
- return SDOperand(N, 0);
+ return CurDAG-SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
}
} else {
static const unsigned SHLTab[] = {
@@ -319,8 +318,7 @@
}
SDOperand Tmp0 = Select(N-getOperand(0));
-CurDAG-SelectNodeTo(N, Opc, MVT::i32, Tmp0);
-return SDOperand(N, 0);
+return CurDAG-SelectNodeTo(N, Opc, MVT::i32, Tmp0);
}
break;
@@ -350,13 +348,11 @@
break;
}
if (X86Lowering.getBytesToPopOnReturn() == 0)
-CurDAG-SelectNodeTo(N, X86::RET, MVT::Other, Chain);
+return CurDAG-SelectNodeTo(N, X86::RET, MVT::Other, Chain);
else
-CurDAG-SelectNodeTo(N, X86::RET, MVT::Other,
- getI16Imm(X86Lowering.getBytesToPopOnReturn()),
- Chain);
-
- return SDOperand(N, 0);
+return CurDAG-SelectNodeTo(N, X86::RET, MVT::Other,
+ getI16Imm(X86Lowering.getBytesToPopOnReturn()),
+Chain);
}
case ISD::LOAD: {
@@ -385,15 +381,17 @@
? CurDAG-getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
: getI32Imm(AM.Disp);
if (AM.BaseType == X86ISelAddressMode::RegBase) {
- CurDAG-SelectNodeTo(N, Opc, OpVT, MVT::Other,
- AM.Base.Reg, Scale, AM.IndexReg, Disp, Chain);
+ return CurDAG-SelectNodeTo(N, Opc, OpVT, MVT::Other,
+ AM.Base.Reg, Scale, AM.IndexReg, Disp,
+ Chain)
+.getValue(Op.ResNo);
} else {
SDOperand Base = CurDAG-getFrameIndex(AM.Base.FrameIndex, MVT::i32);
- CurDAG-SelectNodeTo(N, Opc, OpVT, MVT::Other,
- Base, Scale, AM.IndexReg, Disp, Chain);
+ return CurDAG-SelectNodeTo(N, Opc, OpVT, MVT::Other,
+ Base, Scale, AM.IndexReg, Disp, Chain)
+.getValue(Op.ResNo);
}
}
- return SDOperand(N, Op.ResNo);
}
case ISD::STORE: {
@@ -430,13 +428,13 @@
? CurDAG-getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
: getI32Imm(AM.Disp);
if (AM.BaseType == X86ISelAddressMode::RegBase) {
-CurDAG-SelectNodeTo(N, Opc, MVT::Other,
- AM.Base.Reg, Scale, AM.IndexReg, Disp, Tmp1,
- Chain);
+return CurDAG-SelectNodeTo(N, Opc, MVT::Other,
+AM.Base.Reg, Scale, AM.IndexReg, Disp,
Tmp1,
+Chain);
} else {
SDOperand Base = CurDAG-getFrameIndex(AM.Base.FrameIndex, MVT::i32);
-CurDAG-SelectNodeTo(N, Opc, MVT::Other,
- Base, Scale, AM.IndexReg, Disp, Tmp1, Chain);
+return CurDAG-SelectNodeTo(N, Opc, MVT::Other,
+ Base, Scale, AM.IndexReg, Disp, Tmp1, Chain);
}
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.2 - 1.3
---
Log message:
Add load and other support to the dag-dag isel. Patch contributed by Evan
Cheng!
---
Diffs of the changes: (+225 -2)
X86ISelDAGToDAG.cpp | 227 +++-
1 files changed, 225 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.2
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.3
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.2 Wed Nov 16 16:59:19 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Nov 18 20:11:08 2005
@@ -15,6 +15,8 @@
#include X86.h
#include X86Subtarget.h
#include X86ISelLowering.h
+#include llvm/GlobalValue.h
+#include llvm/CodeGen/MachineConstantPool.h
#include llvm/CodeGen/MachineFunction.h
#include llvm/CodeGen/SelectionDAGISel.h
#include llvm/Target/TargetMachine.h
@@ -27,6 +29,32 @@
//===--===//
namespace {
+ /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
+ /// SDOperand's instead of register numbers for the leaves of the matched
+ /// tree.
+ struct X86ISelAddressMode {
+enum {
+ RegBase,
+ FrameIndexBase,
+} BaseType;
+
+struct {// This is really a union, discriminated by BaseType!
+ SDOperand Reg;
+ int FrameIndex;
+} Base;
+
+unsigned Scale;
+SDOperand IndexReg;
+unsigned Disp;
+GlobalValue *GV;
+
+X86ISelAddressMode()
+ : BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
+}
+ };
+}
+
+namespace {
Statistic
NumFPKill(x86-codegen, Number of FP_REG_KILL instructions added);
@@ -66,6 +94,15 @@
private:
SDOperand Select(SDOperand N);
+void SelectAddress(SDOperand N, X86ISelAddressMode AM);
+bool MatchAddress(SDOperand N, X86ISelAddressMode AM);
+
+/// getI8Imm - Return a target constant with the specified value, of type
+/// i8.
+inline SDOperand getI8Imm(unsigned Imm) {
+ return CurDAG-getTargetConstant(Imm, MVT::i8);
+}
+
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDOperand getI16Imm(unsigned Imm) {
@@ -93,6 +130,141 @@
ScheduleAndEmitDAG(DAG);
}
+/// SelectAddress - Pattern match the maximal addressing mode for this node.
+void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode AM) {
+ MatchAddress(N, AM);
+
+ if (AM.BaseType == X86ISelAddressMode::RegBase !AM.Base.Reg.Val) {
+AM.Base.Reg = CurDAG-getRegister(0, MVT::i32);
+ } else {
+AM.Base.Reg = Select(AM.Base.Reg);
+ }
+ if (!AM.IndexReg.Val) {
+AM.IndexReg = CurDAG-getRegister(0, MVT::i32);
+ } else {
+AM.IndexReg = Select(AM.IndexReg);
+ }
+}
+
+/// FIXME: copied from X86ISelPattern.cpp
+/// MatchAddress - Add the specified node to the specified addressing mode,
+/// returning true if it cannot be done. This just pattern matches for the
+/// addressing mode
+bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode AM) {
+ switch (N.getOpcode()) {
+ default: break;
+ case ISD::FrameIndex:
+if (AM.BaseType == X86ISelAddressMode::RegBase AM.Base.Reg.Val == 0) {
+ AM.BaseType = X86ISelAddressMode::FrameIndexBase;
+ AM.Base.FrameIndex = castFrameIndexSDNode(N)-getIndex();
+ return false;
+}
+break;
+ case ISD::GlobalAddress:
+if (AM.GV == 0) {
+ GlobalValue *GV = castGlobalAddressSDNode(N)-getGlobal();
+ // For Darwin, external and weak symbols are indirect, so we want to load
+ // the value at address GV, not the value of GV itself. This means that
+ // the GlobalAddress must be in the base or index register of the
address,
+ // not the GV offset field.
+ if (Subtarget-getIndirectExternAndWeakGlobals()
+ (GV-hasWeakLinkage() || GV-isExternal())) {
+break;
+ } else {
+AM.GV = GV;
+return false;
+ }
+}
+break;
+ case ISD::Constant:
+AM.Disp += castConstantSDNode(N)-getValue();
+return false;
+ case ISD::SHL:
+if (AM.IndexReg.Val == 0 AM.Scale == 1)
+ if (ConstantSDNode *CN = dyn_castConstantSDNode(N.Val-getOperand(1)))
{
+unsigned Val = CN-getValue();
+if (Val == 1 || Val == 2 || Val == 3) {
+ AM.Scale = 1 Val;
+ SDOperand ShVal = N.Val-getOperand(0);
+
+ // Okay, we know that we have a scale by now. However, if the scaled
+ // value is an add of something and a constant, we can fold the
+ // constant into the disp field here.
+ if (ShVal.Val-getOpcode() == ISD::ADD ShVal.hasOneUse()
+ isaConstantSDNode(ShVal.Val-getOperand(1))) {
+AM.IndexReg = ShVal.Val-getOperand(0);
+ConstantSDNode *AddVal =
+ castConstantSDNode(ShVal.Val-getOperand(1));
+AM.Disp += AddVal-getValue() Val;
+
