From: Tom Stellard
This should only make a difference in programs that use a lot of the
vector ALU instructions like BFI_INT and BIT_ALIGN. There is a slight
improvement in the phatk bitcoin mining kernel with this patch on
Evergreen (vector size == 1):
Before:
1173 Instruction Groups / 9520 dw
On 18 June 2013 01:09, Jordan Justen wrote:
> When rendering to a texture with BaseLevel set, the miptree may be laid
> out such that BaseLevel is in level 0 of the miptree (to avoid wasting
> memory on unused levels between 0 and BaseLevel-1). In that case, we
> have to shift our render target'
On 18 June 2013 02:10, Eric Anholt wrote:
> ... and move the mesa-core-specific code into Mesa core. This code had no
> relation to ir_to_mesa.cpp, since it was also used by intel and
> state_tracker, and most of it was duplicated with the standalone compiler
> (which has periodically drifted fr
https://bugs.freedesktop.org/show_bug.cgi?id=65874
Priority: medium
Bug ID: 65874
Keywords: regression
CC: za...@vmware.com
Assignee: mesa-dev@lists.freedesktop.org
Summary: piglit ext_transform_feedback-intervening-read output
... and move the mesa-core-specific code into Mesa core. This code had no
relation to ir_to_mesa.cpp, since it was also used by intel and
state_tracker, and most of it was duplicated with the standalone compiler
(which has periodically drifted from the Mesa copy).
---
src/glsl/glsl_parser_extras.
I noticed this while trying to merge code with the builtin compiler, which
does set it.
Note that this causes two regressions in piglit in
default-precision-sampler.* which try to link without a vertex or fragment
shader, due to being run under the desktop glslparsertest binary (using
ARB_ES3_comp
We were duplicating this code all over the place, and they all would need
updating for the next set of shader targets.
---
src/glsl/glsl_parser_extras.cpp| 35 ++
src/glsl/glsl_parser_extras.h | 3 +++
src/glsl/link_varyings.cpp
We have ir->print() to do the old declaration of a visitor and having the
IR accept the visitor (yuck!). And now you can call _mesa_print_ir()
safely anywhere that you know what an ir_instruction is.
A couple of missing printf("\n")s are added in error paths -- when an
expression is handed to the
From: Paul Berry
Reviewed-by: Eric Anholt
---
src/glsl/ir.h | 4
src/glsl/ir_hierarchical_visitor.h | 2 ++
src/glsl/ir_visitor.h | 2 ++
3 files changed, 8 insertions(+)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 6d41501..9442681 100644
--- a/src/g
No more forgetting to #include "ir_print_visitor.h" when doing temporary
debug code, or forgetting and leaving it in after removing your temporary
debug code. Also, available from C code so you don't need to move the
caller to C++ just to call it (see also: ir_to_mesa.cpp).
---
src/glsl/ir.h
Jordan Justen writes:
> When rendering to a texture with BaseLevel set, the miptree may be laid
> out such that BaseLevel is in level 0 of the miptree (to avoid wasting
> memory on unused levels between 0 and BaseLevel-1). In that case, we
> have to shift our render target's level down to the ap
When rendering to a texture with BaseLevel set, the miptree may be laid
out such that BaseLevel is in level 0 of the miptree (to avoid wasting
memory on unused levels between 0 and BaseLevel-1). In that case, we
have to shift our render target's level down to the appropriate level of
the smaller m
Also add a v2i32 test to the existing v4i32 test.
Note: v2i32 for EG seems slightly out of order based on the normal
ordering. i.e. "SUB_INT * T..." comes before the "SUB_INT T..."
I am not sure if this is correct, but it's how the current R600 back-end
emits the operation order.
Signed-off-by: A
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 2 ++
test/CodeGen/R600/add.ll | 37 +++--
2 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/lib/
The custom lowering causes llc to crash with a segfault.
Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.
Signed-off-by: Aaron Watry
---
lib/Target/R600/R600ISelLowering.cpp | 4 ++--
test/CodeGen/R600/load.vec.ll| 6 +++
First patch fixes load/store for v2i32 on R600. Without this, the
other two will cause make check failures. I've verified the changes
using a Radeon 5400 (Cedar). Note that the previous custom
lowering of v2i32 store was causing silent data corruption.
The other two patches expand add/sub on SI
Kenneth Graunke writes:
> vec4_visitor::generate_code() switches on vec4_instruction::opcode and
> calls into the brw_eu_emit.c layer to generate code for some of them.
> It then has a default case which calls generate_vec4_instruction() to
> handle the rest...which switches on opcode and handles
Sure. I was under the impression that |size| couldn't be both greater than
4 and a non-multiple of 4, but I've reworked the patch to incorporate this
and to be a little more straightforward.
Is the only way to replace "ASAN" with "Address Sanitizer" to change the
subject of this email thread?
Any
Jose Fonseca writes:
> - Original Message -
>> On Sun, 2013-06-16 at 10:22 -0700, Jose Fonseca wrote:
>>
>> > Ok. I think this patch series is sound from an implementation POV. I
>> > see no point in delaying further. We can tweak things afterwards if
>> > deemed necessary.
>> >
>> > Let
- Original Message -
> On Sun, 2013-06-16 at 10:22 -0700, Jose Fonseca wrote:
>
> > Ok. I think this patch series is sound from an implementation POV. I
> > see no point in delaying further. We can tweak things afterwards if
> > deemed necessary.
> >
> > Lets squash the commits, rename
José Fonseca writes:
>> Do you know why this is?
>
> No, I don't have a clear understanding.
OK. Thanks for letting me know.
>> I'd definitely be interested in making apitrace work more transparently
> here.
>
> Me too. But there are so many apps that only work well with
> LD_LIBRARY_PATH, that
On Sun, 2013-06-16 at 10:22 -0700, Jose Fonseca wrote:
> Ok. I think this patch series is sound from an implementation POV. I
> see no point in delaying further. We can tweak things afterwards if
> deemed necessary.
>
> Lets squash the commits, rename the XYZW formats to go from
> low->high b
On Mon, 2013-06-17 at 01:11 +1000, Jonathan Gray wrote:
> byteswap.h and bswap_32 aren't portable, replace them with calls to
> gallium's util_bswap32 as suggested by Mark Kettenis. Lets these files
> build on OpenBSD.
>
> Signed-off-by: Jonathan Gray
Pushed, thanks!
--
Earthling Michel Dänz
On 06/14/2013 05:12 PM, Myles C. Maxfield wrote:
Sorry for the triple post; I received a bounce email the first time and got
sent to the spam folder the second time, so I'm trying a third time.
Hello, all. I was running Mesa with Address Sanitizer [1] turned on, and found
one place where ASAN
On 06/16/2013 05:24 AM, Dave Airlie wrote:
I noticed this code didn't work as advertised while doing some passing around
of TGSI shaders and trying to reparse them, and things failing.
This seems to fix it here for at least the small test case I hacked into a
graw test.
Signed-off-by: Dave Airl
On 06/16/2013 11:57 AM, Frank Henigman wrote:
This works (has been in Chrome OS for a while) but only for vertex
shaders, not geometry shaders nor llvmpipe. I'm afraid I'm completely
ignorant about AMD drivers.
This applies on top of my recently posted memory saving patches.
Without them the cac
Looks good to me.
Jose
- Original Message -
> From: Roland Scheidegger
>
> For conditional rendering this makes it possible to skip rendering
> if either the predicate is true or false, as supported by d3d10
> (in fact previously it was sort of implied skip rendering if predicate
> is f
On Mon, Jun 17, 2013 at 06:43:09AM -0700, Vincent Lejeune wrote:
> Hi,
>
> these patches fix 2 bugs in R600 backend.
> The first one use the rv710/rv730 correct encoding for TEX clause with more
> than 8 instructions.
> This bug has been spoted there :
>
> https://bugs.freedesktop.org/show_bug.
On Mon, Jun 17, 2013 at 9:43 AM, Vincent Lejeune wrote:
> Hi,
>
> these patches fix 2 bugs in R600 backend.
> The first one use the rv710/rv730 correct encoding for TEX clause with more
> than 8 instructions.
> This bug has been spoted there :
>
> https://bugs.freedesktop.org/show_bug.cgi?id=6425
Hi,
these patches fix 2 bugs in R600 backend.
The first one use the rv710/rv730 correct encoding for TEX clause with more
than 8 instructions.
This bug has been spoted there :
https://bugs.freedesktop.org/show_bug.cgi?id=64257
The other patch fix a typo that causes instructions not to use PV/PS
https://bugs.freedesktop.org/show_bug.cgi?id=63435
Stefan Dirsch changed:
What|Removed |Added
CC||sndir...@suse.de
--
You are receiving t
On Mon, Jun 17, 2013 at 07:47:11AM +0200, Michel Dänzer wrote:
> On Mon, 2013-06-17 at 01:11 +1000, Jonathan Gray wrote:
> > byteswap.h and bswap_32 aren't portable, replace them with calls to
> > gallium's util_bswap32 as suggested by Mark Kettenis. Lets these files
> > build on OpenBSD.
> >
> >
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