---
src/gbm/main/gbm.h | 10 +-
src/mapi/glapi/glapi.h | 17 +
src/mesa/main/context.c | 45 -
src/mesa/program/program.h | 8 +---
src/mesa/swrast/s_context.h | 10 +-
src/mesa/tnl/t_context.h
---
doxygen/all.doxy | 1 +
src/gbm/gbm.doxy_text| 15 ++
src/mesa/drivers/dri/i965/i965.doxy_text | 176 +
src/mesa/main/main.doxy_text | 257 +++
src/mesa/program/program.doxy_text |
---
src/gbm/main/gbm.h | 10 +-
src/mapi/glapi/glapi.h | 17 +
src/mesa/main/context.c | 45 -
src/mesa/program/program.h | 8 +---
src/mesa/swrast/s_context.h | 10 +-
src/mesa/tnl/t_context.h
---
doxygen/all.doxy | 1 +
src/gbm/gbm.doxy_text| 15 ++
src/mesa/drivers/dri/i965/i965.doxy_text | 176 +
src/mesa/main/main.doxy_text | 257 +++
src/mesa/program/program.doxy_text |
Hello all,
I really apologize, being new to git send-email and git format I managed to
make a number of mistakes when I sent the patches for documentation:
1) I sent the patch set twice.
2) The second time I sent the patch set, I sent the first patch twice.
The threads for each are
https://bugs.freedesktop.org/show_bug.cgi?id=70264
--- Comment #1 from Pekka Paalanen ppaala...@gmail.com ---
That proposed fix does not sound right. If you look at pkg-config manual, there
are the PKG_CONFIG_ALLOW_SYSTEM_CFLAGS and PKG_CONFIG_ALLOW_SYSTEM_LIBS
environment variables. pkg-config
Suppose we create a wl_egl_window and an EGLSurface. Then we call
eglMakeCurrent(dpy,surf,surf,ctx) with that surface, render and swap.
Later we destroy the surface and the window, and we make current
another surface. That resulted in two invalid writes because
the surface, which is refcounted,
Hi everybody!
I see lines like
[ 362.708791] thunderbird-bin[1888]: segfault at 8 ip b0f3f3aa sp bf93fd54
error 4 in i915_dri.so[b0a02000+fc]
[ 846.063129] firefox[2008]: segfault at 8 ip b0af63aa sp bff96c74 error 4 in
i915_dri.so[b05b9000+fc]
after every start of
- gsampler2DRect
- optional `comp` parameter
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 16
1 file changed, 16 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index d40888d..aa40876 100644
---
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 45 ++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index
This series adds support for the following textureGather* enhancements
that are part of ARB_gpu_shader5:
- new textureGatherOffset variants
- nonconstant offset for all textureGatherOffset variants, when GLSL 4.00 or
ARB_gpu_shader5 is in use. If only ARB_texture_gather is enabled, const
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index
Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to be
a constant expression.
With that extension, it is relaxed to be any dynamically uniform
expression. If the value is not dynamically uniform, the results
are undefined.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 61c4bf5..19500d1 100644
---
The generator code ends up clearer this way than if we had to sniff
via mlen. Implemented via the gather4_po message in hardware, which is
present in Gen7 and later.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The commit message is wrong -- there is no requirement for the offset
to be dynamically uniform, either in the spec or in the i965
implementation in later patches.
On Tue, Oct 8, 2013 at 10:34 PM, Chris Forbes chr...@ijw.co.nz wrote:
Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to
https://bugs.freedesktop.org/show_bug.cgi?id=70123
--- Comment #3 from Jeff Blake jeffbla...@gmail.com ---
Unfortunately this doesn't fix the issue. When I get a spare moment I'll try
the patch on the desktop pc (which has a different card).
--
You are receiving this mail because:
You are the
On Mon, Oct 07, 2013 at 04:31:20PM -0700, Kenneth Graunke wrote:
Currently, all that matters is that we copy the correct number of bits,
so any format that has 32-bits of data will work fine.
Once BLORP begins handling format conversions, the sampler will need to
correctly interpret the
On Mon, Oct 07, 2013 at 04:31:22PM -0700, Kenneth Graunke wrote:
The previous code for sRGB overrides assumes that the source and
destination formats are equal, other than the color space. This won't
be feasible when we add support for format conversions.
Here are a few cases, and how the
https://bugs.freedesktop.org/show_bug.cgi?id=70123
--- Comment #4 from Christian König deathsim...@vodafone.de ---
(In reply to comment #3)
Unfortunately this doesn't fix the issue. When I get a spare moment I'll try
the patch on the desktop pc (which has a different card).
Please try to
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_state_draw.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 626ba95..d20658e 100644
From: Marek Olšák marek.ol...@amd.com
This doesn't fix any known issue. I'm just following the docs.
---
src/gallium/drivers/radeonsi/si_state.c | 10 ++
src/gallium/drivers/radeonsi/si_state_draw.c | 26 +-
2 files changed, 27 insertions(+), 9 deletions(-)
3rd patch is reviewed-by:Vincent Lejeunevljn at ovi.com
The first one
Subject: [PATCH 1/4] R600/SI: Mark the EXEC register as reserved
This prevents the machine verifier from complaining about uses of
an undefined physical register.
---
lib/Target/R600/SIRegisterInfo.cpp | 3 ++-
1 file
The series is
Reviewed-by: Michel Dänzer michel.daen...@amd.com
--
Earthling Michel Dänzer| http://www.amd.com
Libre software enthusiast |Mesa and X developer
___
mesa-dev mailing list
From: Marek Olšák marek.ol...@amd.com
The timeout of 0 is equivalent to calling fence_signalled, which is not very
useful here.
---
src/gallium/state_trackers/vdpau/presentation.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/vdpau/presentation.c
We hadn't run into order of operation warnings before, apparently, since
addition is so low on the order.
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/main/macros.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
Fixes 3 texelFetch tests in piglit all.tests.
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 72 +++---
1 file changed, 17 insertions(+), 55 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_tex_layout.c |
On 10/08/2013 11:36 AM, Eric Anholt wrote:
We hadn't run into order of operation warnings before, apparently, since
addition is so low on the order.
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/main/macros.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Am 08.10.2013 02:23, schrieb Brian Paul:
The new function replaces four old functions: set_fragment/vertex/
geometry/compute_sampler_views().
Note: at this time, it's expected that the 'start' parameter will
always be zero.
---
This change touches quite a few files. I've probably
Series Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
On Sat, Sep 14, 2013 at 1:00 PM, Paul Berry stereotype...@gmail.com wrote:
This patch adds a location element to struct glsl_struct_field, so
that we can keep track of the gl_varying_slot associated with each
built-in geometry shader
On 10/08/2013 10:36 AM, Eric Anholt wrote:
We hadn't run into order of operation warnings before, apparently, since
addition is so low on the order.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/main/macros.h | 2 +-
1 file
On 09/28/2013 02:59 PM, Paul Berry wrote:
On 27 September 2013 14:32, Ian Romanick i...@freedesktop.org
mailto:i...@freedesktop.org wrote:
There are some bits of this patch I'm trying to understand. I think
they can be cleared up by one question below...
On 09/14/2013 01:00
On 10/07/2013 04:31 PM, Kenneth Graunke wrote:
The previous code for sRGB overrides assumes that the source and
destination formats are equal, other than the color space. This won't
be feasible when we add support for format conversions.
Here are a few cases, and how the old code handled
On 10/07/2013 04:31 PM, Kenneth Graunke wrote:
BLORP performs blits by drawing a rectangle with a shader that samples
from the source texture, and writes color data to the destination.
The sampler always returns 32-bit RGBA float data, regardless of the
source format's component ordering or
On 10/08/2013 10:36 AM, Eric Anholt wrote:
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
I think we didn't bother with that patch because
On 10/07/2013 04:31 PM, Kenneth Graunke wrote:
This series introduces support for blitting and CopyTexSubImage with
format conversions via the BLORP engine. Previously, we fell back to
the meta paths, which fell back to unpack/pack code, which was pretty
dire for performance.
In
Am 08.10.2013 19:13, schrieb Marek Olšák:
From: Marek Olšák marek.ol...@amd.com
The timeout of 0 is equivalent to calling fence_signalled, which is not very
useful here.
Grigori already attached the same fix to the bug
https://bugs.freedesktop.org/show_bug.cgi?id=68792.
He's probably
Brian Paul bri...@vmware.com writes:
On 10/08/2013 11:36 AM, Eric Anholt wrote:
We hadn't run into order of operation warnings before, apparently, since
addition is so low on the order.
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/main/macros.h | 2 +-
1 file changed, 1
Ok. I didn't know Grigori had been working on it.
Marek
On Tue, Oct 8, 2013 at 8:40 PM, Christian König deathsim...@vodafone.de wrote:
Am 08.10.2013 19:13, schrieb Marek Olšák:
From: Marek Olšák marek.ol...@amd.com
The timeout of 0 is equivalent to calling fence_signalled, which is not
only 8 and 32 bit integers were supported before.
Signed-off-by: Zack Rusin za...@vmware.com
---
src/gallium/auxiliary/gallivm/lp_bld_printf.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_printf.c
The code introduces two new 32bit integer multiplication opcodes which
can be used to produce correct 64 bit results. GLSL, OpenCL and D3D10+
require them. We use two seperate opcodes, because they match the
behavior of GLSL and OpenCL, are a lot easier to add than a single
opcode with multiple
Both the imul_hi and umul_hi are working with this patch.
Signed-off-by: Zack Rusin za...@vmware.com
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 60 ++
1 file changed, 60 insertions(+)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
On 10/08/2013 02:34 AM, Chris Forbes wrote:
Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
1 file changed, 1
On 10/08/2013 02:34 AM, Chris Forbes wrote:
This series adds support for the following textureGather* enhancements
that are part of ARB_gpu_shader5:
- new textureGatherOffset variants
- nonconstant offset for all textureGatherOffset variants, when GLSL 4.00 or
ARB_gpu_shader5 is in use.
Chia-I Wu olva...@gmail.com writes:
From: Chia-I Wu o...@lunarg.com
FS_OPCODE_OVERWRITE_DST is used to indicate that the destination register is
(completely) overwritten. No code is emitted, but the liveness analysis can
use it as a hint to add the destination register to DEF bitset. This
Am 08.10.2013 21:22, schrieb Zack Rusin:
Both the imul_hi and umul_hi are working with this patch.
Signed-off-by: Zack Rusin za...@vmware.com
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 60
++
1 file changed, 60 insertions(+)
diff --git
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r300/r300_flush.c | 13 ++-
src/gallium/drivers/r300/r300_screen.c| 28 +++---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 56 +++
src/gallium/winsys/radeon/drm/radeon_winsys.h |
From: Marek Olšák marek.ol...@amd.com
This was horribly, horribly broken. The limit was 1024 fences created
from the start of the application and as you probably know, pipe fences are
not reusable. If you wanted to use one fence per frame, you could only do
that for 1024 frames, whish was pretty
Do the ARB_gpu_shader5 tests in piglit (fs-imulExtended,
fs-umulExtended) tests pass?
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Tapani Pälli tapani.pa...@intel.com writes:
Patch introduces ir_cache class that can serialize a gl_shader
to memory with help of memory_writer class and also unserialize
it back with help of memory_map class.
This can be used by the shader compiler to cache individual shaders
and skip
Ian Romanick i...@freedesktop.org writes:
On 10/08/2013 10:36 AM, Eric Anholt wrote:
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
I
On 10/08/2013 11:22 AM, Ian Romanick wrote:
On 10/08/2013 10:36 AM, Eric Anholt wrote:
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
I
On 10/08/2013 10:36 AM, Eric Anholt wrote:
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
Ah, I see it now:
From the Sandybridge PRM,
Kenneth Graunke kenn...@whitecape.org writes:
BLORP performs blits by drawing a rectangle with a shader that samples
from the source texture, and writes color data to the destination.
The sampler always returns 32-bit RGBA float data, regardless of the
source format's component ordering or
On 10/07/2013 04:31 PM, Kenneth Graunke wrote:
BLORP performs blits by drawing a rectangle with a shader that samples
from the source texture, and writes color data to the destination.
The sampler always returns 32-bit RGBA float data, regardless of the
source format's component ordering or
Am 08.10.2013 22:00, schrieb Matt Turner:
Do the ARB_gpu_shader5 tests in piglit (fs-imulExtended,
fs-umulExtended) tests pass?
Since the patch makes no attempt to translate it from glsl, I can't see
how it would. Might be a nice addition though, but it would require glsl
version and extension
On 10/08/2013 01:42 PM, Eric Anholt wrote:
Kenneth Graunke kenn...@whitecape.org writes:
BLORP performs blits by drawing a rectangle with a shader that samples
from the source texture, and writes color data to the destination.
The sampler always returns 32-bit RGBA float data, regardless of
As we're moving towards expanding the number of subpixel
bits and the width of the variables used in the computations
we need to make this code a bit more centralized.
Signed-off-by: Zack Rusin za...@vmware.com
---
src/gallium/drivers/llvmpipe/lp_rast.h | 9 +
Since it sounds like valve won't be able to fix dota2's rendering to use
ARB_mbr soon, here's a series to add just a little bit of tracking that
works around most of the overhead of not using ARB_mbr with their
rendering pattern. 7.69854% +/- 0.909163% (n=3) fps improvement with
default settings.
If glBufferData(), glBufferSubData(0, obj-Size), or similar happens, we
get a new drm_intel_bo for the buffer object, and thus need to re-upload
texture buffer state so we point at the new data.
Fixes the new piglit GL_ARB_texture_buffer_object/data-sync
Cc: 9.2 mesa-sta...@lists.freedesktop.org
Since src_offset was always 0, it wasn't doing anything for us beyond
intel_bufferobj_buffer().
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 14 --
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 15 ++-
src/mesa/drivers/dri/i965/intel_buffer_objects.h | 5
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 7ddeb6e..a2046c3 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++
This was mostly for the i915 system-memory VBO code, which we don't have
any more, but since that existed we've ended up producing dependencies on
it being there.
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 4
1 file changed, 4 insertions(+)
diff --git
I noticed this while looking for a cite for the similar requirement I was
going to put on texture buffer objects.
We don't actually have a test for this, but the
GL_ARB_texture_buffer_range alignment test we have makes me reasonably
confident that this works, too.
This causes a regression to be
Supporting this extension turns out to simplify our code a bit over not
supporting this extension, once the glBufferSubData() synchronization code
lands.
---
docs/GL3.txt | 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 1 +
---
src/mesa/drivers/dri/i965/brw_draw.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index b6cfd53..0acd089 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++
The brw_prepare_vertices that sets up buffers[] depends on these
parameters, so don't let brw_prepare_vertices() skip it.
---
src/mesa/drivers/dri/i965/brw_draw.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
On DOTA2, framerate on dota2-de1.dem in windowed mode on my laptop
improves by 7.69854% +/- 0.909163% (n=3). In a microbenchmark hitting
this code path (wall time of piglit vbo-subdata-many), runtime decreases
from 0.8 to 0.05 seconds.
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 24
Sorry, that was a bit sloppy on my part..
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Oct 9, 2013 at 10:00 AM, Eric Anholt e...@anholt.net wrote:
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 5 October 2013 12:10, Kenneth Graunke kenn...@whitecape.org wrote:
On 10/02/2013 05:45 PM, Paul Berry wrote:
Previously, we erroneously used the name gl_in for both the block
name and the instance name.
---
src/glsl/builtin_variables.cpp | 2 +-
1 file changed, 1 insertion(+), 1
Interface declarations have two names associated with them: the block
name and the instance name. It's the block name that needs to be
passed to get_interface_instance(). This patch renames the argument
so that there's no confusion.
---
src/glsl/glsl_types.cpp | 8
On 10/08/2013 02:17 PM, Paul Berry wrote:
Interface declarations have two names associated with them: the block
name and the instance name. It's the block name that needs to be
passed to get_interface_instance(). This patch renames the argument
so that there's no confusion.
---
On 5 October 2013 12:12, Kenneth Graunke kenn...@whitecape.org wrote:
On 10/02/2013 05:45 PM, Paul Berry wrote:
GLSL reserves identifiers beginning with gl_ or containing __, but
we haven't been consistent about enforcing this rule. This patch
makes a new function to check whether
On Tuesday 08 October 2013, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
This was horribly, horribly broken. The limit was 1024 fences created
from the start of the application and as you probably know, pipe fences are
not reusable. If you wanted to use one fence per frame, you
On 5 October 2013 12:25, Kenneth Graunke kenn...@whitecape.org wrote:
On 10/02/2013 05:45 PM, Paul Berry wrote:
This patch modifies the get_variable_being_redeclared() function so
that it no longer relies on the ast_declaration for the variable being
redeclared. In future patches, this
Prerequisites:
- Kernel patches: [1]
(do 'make headers_install' and update libdrm headers after compiling
the kernel)
- Mesa patch: [2]
This is an update from my previous RFC patches [3]. Most notable
change is that the resource streamer is an experimental feature
disabled by
Used to toggle the resource streamer within a batchbuffer
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_reg.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h
export INTEL_RESOURCE_STREAMER={0,1} To switch on/off resource streamer.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h |1 +
src/mesa/drivers/dri/i965/intel_context.c | 24
2 files changed, 25
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Bspec: Prior to changing the Surface State Base Address, the resouce streamer
must be disabled within a batch buffer where the RS is enabled. RS is
re-enabled again once the SBA is updated.
The resource streamer can be toggled within a batch using MI_RS_CONTROL.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c | 14 ++
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 14 ++
2 files changed, 28 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 4d1a65e..031e21e 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into.
Each binding table offset in the binding table pool is unique per
each shader stage that are enabled within a batch.
Update the on-chip binding table for every generated texture surface_state
entries. Instead of generating binding tables manually, we update individual
slots of surface state entries using the new EDIT commands for gen7.5
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
When hardware-generated binding tables are taken into use, skip uploading
of binding tables generated manually by the driver.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 12 ++--
1 file changed, 10 insertions(+), 2
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 36
src/mesa/drivers/dri/i965/brw_defines.h|5
src/mesa/drivers/dri/i965/brw_state.h | 15 +-
3 files changed, 55
When surface_state pointing to pull constant surfaces are changed, update
on-chip binding table. Same with VS ubo surface states.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_vs_surface_state.c |9 +
1 file changed, 9 insertions(+)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index
When hw-generated binding tables are enabled edit the binding table
state for new SURFACE_STATE entries that are generated in the blorp path.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 ++-
1 file changed, 14
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.
Note that the the
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Hash: SHA1
On 10/08/2013 01:28 PM, Eric Anholt wrote:
Ian Romanick i...@freedesktop.org writes:
On 10/08/2013 10:36 AM, Eric Anholt wrote:
We had a fixup for gen4's 3d-layout cubemaps (which, iirc,
we'd experimentally found to be necessary!), but while the
On Wednesday, October 09, 2013 12:41:37 AM Abdiel Janulgue wrote:
Prerequisites:
- Kernel patches: [1]
(do 'make headers_install' and update libdrm headers after compiling
the kernel)
- Mesa patch: [2]
Series lives on http://cgit.freedesktop.org/~abj/mesa/ mesa_rs branch
Sorry, I didn't realize this. You are right. My bad. Regardless of my
comment, I still wonder what people's opinion on this patch is.
Marek
On Tue, Oct 8, 2013 at 11:28 PM, Fredrik Höglund fred...@kde.org wrote:
On Tuesday 08 October 2013, Marek Olšák wrote:
From: Marek Olšák
On 10/08/2013 10:36 AM, Eric Anholt wrote:
Fixes 3 texelFetch tests in piglit all.tests.
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 72 +++---
1 file changed, 17 insertions(+), 55 deletions(-)
Patch 3/3 is
On 10/08/2013 10:36 AM, Eric Anholt wrote:
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
Cc: 9.1 9.2 mesa-sta...@lists.freedesktop.org
---
On 10/08/2013 12:51 AM, Knut Petersen wrote:
Hi everybody!
I see lines like
[ 362.708791] thunderbird-bin[1888]: segfault at 8 ip b0f3f3aa sp bf93fd54
error 4 in i915_dri.so[b0a02000+fc]
[ 846.063129] firefox[2008]: segfault at 8 ip b0af63aa sp bff96c74 error 4 in
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