Due to the destination register width of 1 or 2, these instructions get
ExecSize 1 or 2. But dir and offset (used as src0) are both registers
of width 4, violating the execsize = width assertion.
I honestly don't think this could have ever worked.
Fixes Piglit's polygon-offset and
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Aug 6, 2014 at 6:57 PM, Kenneth Graunke kenn...@whitecape.org wrote:
Due to the destination register width of 1 or 2, these instructions get
ExecSize 1 or 2. But dir and offset (used as src0) are both registers
of width 4, violating the
On Friday, August 01, 2014 12:53:34 AM Jordan Justen wrote:
In the gen6 PRM Volume 1 Part 1: Graphics Core, Section
7.18.3.7.1 (Surface Arrays For all surfaces other than separate
stencil buffer):
[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the
value calculated in the
On 06.08.2014 03:08, Jason Ekstrand wrote:
Module: Mesa
Branch: master
Commit: 850fb0d1dca616179d3239a7b7bd94fe1979604c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=850fb0d1dca616179d3239a7b7bd94fe1979604c
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Thu Jul 10
On 06.08.2014 18:28, Michel Dänzer wrote:
On 06.08.2014 03:08, Jason Ekstrand wrote:
Module: Mesa
Branch: master
Commit: 850fb0d1dca616179d3239a7b7bd94fe1979604c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=850fb0d1dca616179d3239a7b7bd94fe1979604c
Author: Jason Ekstrand
On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Tue, Aug 5, 2014 at 5:25 PM, Roland Scheidegger srol...@vmware.com wrote:
From a gallium perspective, indirect temp regs are already working - so
something like
MOV TEMP[0], TEMP[TEMP[1].x] should work.
Indirect
On 08/05/2014 05:41 PM, Michel Dänzer wrote:
On 31.07.2014 15:05, Michel Dänzer wrote:
On 30.07.2014 20:11, Tapani Pälli wrote:
Current version can create ir_expression where operands have
different base type, patch adds support for unsigned type.
Signed-off-by: Tapani Pälli
Patch removes old variable based logic for handling a break inside
switch. Switch is put inside a loop so that existing infrastructure
for loop flow control can be used for the switch, now also dead code
elimination works properly.
Possible 'continue' call inside a switch needs now special
What is this patch good for?
Marek
On Tue, Aug 5, 2014 at 7:31 PM, Christian König deathsim...@vodafone.de wrote:
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
src/gallium/drivers/radeon/r600_pipe_common.c | 9 ++
What is this patch good for?
Nothing in particular, I just wanted to test how much overhead creating
a new BO each time we do transfer_inline_write actually makes.
BTW: Implementing transfer_inline_write using userptrs was just a prove
of concept. It turned out to actually be way slower than
For patch 1 2:
Reviewed-by: Marek Olšák marek.ol...@amd.com
How was the DMA code tested? I think the best thing would be to switch
resource_copy_region to dma_copy just for testing and run piglit. (you
also probably want to avoid recursion between dma_copy and
resource_copy_region)
Marek
On
On Tue, Aug 5, 2014 at 7:31 PM, Christian König deathsim...@vodafone.de wrote:
From: Christian König christian.koe...@amd.com
Not completely implemented, cause we need DMA copy support for every hw
generation.
Signed-off-by: Christian König christian.koe...@amd.com
---
I only know about AMD_pinned_memory, which is for buffers only. I
don't know about an API for creating textures from user pointers. Yes,
there are pixel buffer objects, but they are a lot more difficult to
implement and they are defined such that a zero-copy approach to get a
texture is not
On Tue, Aug 05, 2014 at 09:14:55PM +0300, Pohjolainen, Topi wrote:
On Thu, Jul 24, 2014 at 07:54:12PM -0700, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_cfg.h | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.h
Am 06.08.2014 um 13:42 schrieb Marek Olšák:
For patch 1 2:
Reviewed-by: Marek Olšák marek.ol...@amd.com
How was the DMA code tested? I think the best thing would be to switch
resource_copy_region to dma_copy just for testing and run piglit. (you
also probably want to avoid recursion between
Am 06.08.2014 um 13:45 schrieb Marek Olšák:
On Tue, Aug 5, 2014 at 7:31 PM, Christian König deathsim...@vodafone.de wrote:
From: Christian König christian.koe...@amd.com
Not completely implemented, cause we need DMA copy support for every hw
generation.
Signed-off-by: Christian König
On Thu, Jul 24, 2014 at 07:54:18PM -0700, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 80
src/mesa/drivers/dri/i965/brw_shader.h | 5 ++
2 files changed, 85 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
On Wed, Aug 6, 2014 at 2:44 PM, Christian König deathsim...@vodafone.de wrote:
Am 06.08.2014 um 13:45 schrieb Marek Olšák:
On Tue, Aug 5, 2014 at 7:31 PM, Christian König deathsim...@vodafone.de
wrote:
From: Christian König christian.koe...@amd.com
Not completely implemented, cause we need
2014-08-04 21:25 GMT+02:00 Eric Anholt e...@anholt.net:
thomashellan...@gmail.com writes:
From: Thomas Helland thomashellan...@gmail.com
When writing that A || (A B) patch some
days ago I also wrote some other patches
that have no impact on my collection of shaders.
(shader-db + Some TF2
From: Marek Olšák marek.ol...@amd.com
This validates all bound buffers (CB, ZB, textures, DMA) at the beginning
of CS. This fixes bo-space_accouned assertion failures.
Tested by: Jochen Rollwagen joro-2...@t-online.de
Cc: mesa-sta...@lists.freedesktop.org
---
From: Marek Olšák marek.ol...@amd.com
If the driver crashes in create_xx_shader, you want to see the shader.
---
src/mesa/state_tracker/st_program.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/src/mesa/state_tracker/st_program.c
From: Marek Olšák marek.ol...@amd.com
The code is rewritten to take known constraints into account, while always
using 0 by default.
This should improve performance for multi-SE parts in theory.
A debug option is also added for easier debugging. (If there are hangs,
use the option. If the hangs
From: Marek Olšák marek.ol...@amd.com
This isn't documented anywhere, but it's the only thing that works
for this case.
---
src/gallium/drivers/radeonsi/si_state_draw.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
On 08/05/2014 10:35 AM, Roland Scheidegger wrote:
Am 30.07.2014 19:08, schrieb Brian Paul:
Compute the bitmask of supported array types once instead of every
time we call a GL vertex array function.
---
src/mesa/main/mtypes.h |3 ++
src/mesa/main/varray.c | 86
On Wed, Aug 6, 2014 at 9:28 AM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
This validates all bound buffers (CB, ZB, textures, DMA) at the beginning
of CS. This fixes bo-space_accouned assertion failures.
Tested by: Jochen Rollwagen joro-2...@t-online.de
Cc:
On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
The code is rewritten to take known constraints into account, while always
using 0 by default.
This should improve performance for multi-SE parts in theory.
A debug option is also
On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
This isn't documented anywhere, but it's the only thing that works
for this case.
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_state_draw.c
On Aug 5, 2014, at 9:40 PM, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
If the vertex shader has no position but the gs has, the clipvertex output
was -1 (because it's the same as vs position in this case if there's no
explicit clipvertex output). This caused
On 07/30/2014 04:11 AM, Tapani Pälli wrote:
Current version can create ir_expression where operands have
different base type, patch adds support for unsigned type.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
https://bugs.freedesktop.org/show_bug.cgi?id=80880
---
Am 06.08.2014 13:00, schrieb Marek Olšák:
On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Tue, Aug 5, 2014 at 5:25 PM, Roland Scheidegger srol...@vmware.com
wrote:
From a gallium perspective, indirect temp regs are already working - so
something like
MOV TEMP[0],
On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger srol...@vmware.com wrote:
Am 06.08.2014 13:00, schrieb Marek Olšák:
On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Tue, Aug 5, 2014 at 5:25 PM, Roland Scheidegger srol...@vmware.com
wrote:
From a gallium
On Wed, Aug 6, 2014 at 9:33 AM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
If the driver crashes in create_xx_shader, you want to see the shader.
Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
---
src/mesa/state_tracker/st_program.c | 22 ++
Am 06.08.2014 17:03, schrieb Ilia Mirkin:
On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger srol...@vmware.com
wrote:
Am 06.08.2014 13:00, schrieb Marek Olšák:
On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Tue, Aug 5, 2014 at 5:25 PM, Roland Scheidegger
On Wed, Aug 6, 2014 at 11:15 AM, Roland Scheidegger srol...@vmware.com wrote:
Am 06.08.2014 17:03, schrieb Ilia Mirkin:
On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger srol...@vmware.com
wrote:
Am 06.08.2014 13:00, schrieb Marek Olšák:
On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin
Replace the plain sampler index with a register reference to a sampler.
We also need to keep track of the sampler array size when there is a
relative reference so that we can mark the whole array used.
To facilitate implementation, we add a separate ADDR register that
exclusively handles the
Am 06.08.2014 17:20, schrieb Ilia Mirkin:
On Wed, Aug 6, 2014 at 11:15 AM, Roland Scheidegger srol...@vmware.com
wrote:
Am 06.08.2014 17:03, schrieb Ilia Mirkin:
On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger srol...@vmware.com
wrote:
Am 06.08.2014 13:00, schrieb Marek Olšák:
On Wed,
On Wed, Aug 6, 2014 at 4:01 PM, Alex Deucher alexdeuc...@gmail.com wrote:
On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
The code is rewritten to take known constraints into account, while always
using 0 by default.
This should
I guess PIPE_SHADER_CAP_MAX_ADDRS is now useless, because it can be
derived from GLSL_FEATURE_LEVEL, right?
Marek
On Wed, Aug 6, 2014 at 5:25 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
Replace the plain sampler index with a register reference to a sampler.
We also need to keep track of the
On Wed, Aug 6, 2014 at 11:30 AM, Marek Olšák mar...@gmail.com wrote:
On Wed, Aug 6, 2014 at 4:01 PM, Alex Deucher alexdeuc...@gmail.com wrote:
On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
The code is rewritten to take known
pc-MaxAddressRegs = pc-MaxNativeAddressRegs =
_min(screen-get_shader_param(screen, sh, PIPE_SHADER_CAP_MAX_ADDRS),
MAX_PROGRAM_ADDRESS_REGS);
Not really sure what that's referring to... ARB_vp/fp or something?
Anyways, this is definitely a bit of a violation
On Wed, Aug 6, 2014 at 5:53 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
pc-MaxAddressRegs = pc-MaxNativeAddressRegs =
_min(screen-get_shader_param(screen, sh, PIPE_SHADER_CAP_MAX_ADDRS),
MAX_PROGRAM_ADDRESS_REGS);
Not really sure what that's referring
On Mon, Aug 4, 2014 at 6:48 AM, Andreas Boll andreas.boll@gmail.com wrote:
The initial firmware for hawaii does not support type3 nop packet.
Detect the new hawaii firmware with query RADEON_INFO_ACCEL_WORKING2.
If the returned value is 3, then the new firmware is used.
This patch uses
This adds a boolean in the gl_extensions struct for
GL_ARB_texture_compression_bptc as well as an entry in extension_table.
---
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/main/extensions.c
Adds the ‘bptc’ layout to get_channel_bits. The channel bits for BPTC depend
on the mode but as it only has to be an approximation we can set it to 4 like
for S3TC.
---
src/mesa/main/format_info.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/format_info.py
If the name of a compressed texture format has ‘FLOAT’ in it it will now set
the data type of the format to GL_FLOAT. This will be needed for the BPTC
half-float formats.
---
src/mesa/main/format_info.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Enables BPTC texture compression on the software rasterizer.
---
src/mesa/main/extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index f3197f9..7732249 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
Here is a v2 of the BPTC texture compression series. The main
difference is that instead of going via DXT3 for the UNORM formats it
now always uses the custom naïve compressor for all formats. This
doesn't give very good-looking results but it is fast and doesn't add
any dependencies. There was
Adds functions to fetch from any of the four BPTC-compressed formats.
v2: Set the alpha component to 1.0 when fetching from the half-float formats
instead of leaving it uninitialised. Don't linearize the alpha component
when fetching from sRGB.
---
src/mesa/Makefile.sources| 1
Once we add BPTC texture support we will need to generate mipmaps for
compressed floating point textures too. Most of the code seems to already be
there but it just needs a few extra lines to get it to use GL_FLOAT instead of
GL_UNSIGNED_BYTE as the type for the temporary buffers.
---
This adds the following four Mesa image format enums which correspond to the
four BPTC compressed texture formats:
MESA_FORMAT_BPTC_RGBA_UNORM
MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM
MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT
MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT
It also updates the format information
The signed and unsigned half-float BPTC-compressed formats were being reported
as having a base format of GL_RGBA but they don't store an alpha channel so it
should be GL_RGB.
---
src/mesa/main/texcompress.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
---
docs/GL3.txt| 2 +-
docs/relnotes/10.3.html | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index e241257..973495c 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -138,7 +138,7 @@ GL 4.1:
GL 4.2:
GLSL 4.2
Previously the Meta implementation of glGetTexImage would fall back to
_mesa_get_teximage if the texturing is not using an unsigned normalised
format. However in order to support the half-float formats of BPTC textures we
can make it render to a floating-point renderbuffer instead. This patch
This adds compressors for all four of the BPTC compressed-texture formats. The
compressor is written from scratch and takes a very simple approach. It always
uses a single mode of the BPTC format (4 for unorm and 3 for half-floats) and
picks the two endpoints by dividing the texels into those
Enables the BPTC extension on Gen=7 and adds the necessary format mappings to
get the right surface type value.
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 5 +
src/mesa/drivers/dri/i965/intel_extensions.c| 2 ++
2 files changed, 7 insertions(+)
diff --git
I'd just liked to point out that I made a nearly identical patch before
this patch was posted but I didn't get any review despite prodding
people a few times on #dri-devel. Maybe we should try to get into the
habit of searching patchwork for existing patches before posting to the
list. Does anyone
This looks fine to me.
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On Wed, Aug 6, 2014 at 9:27 AM, Neil Roberts n...@linux.intel.com wrote:
Adds the ‘bptc’ layout to get_channel_bits. The channel bits for BPTC
depend
on the mode but as it only has to be an approximation we can set
Looks fine
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On Wed, Aug 6, 2014 at 9:27 AM, Neil Roberts n...@linux.intel.com wrote:
If the name of a compressed texture format has ‘FLOAT’ in it it will now
set
the data type of the format to GL_FLOAT. This will be needed for the BPTC
Sorry, said that just a little early. Do we really want 4 bits for a
floating-point format? How many bits does nvidia report?
--Jason
On Wed, Aug 6, 2014 at 9:55 AM, Jason Ekstrand ja...@jlekstrand.net wrote:
This looks fine to me.
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On
Michael,
Could you please point me at the failing tests. I don't have a radeon, but
I can run with llvmpipe or dri swrast and try to find the bug that way.
--Jason Ekstrand
On Wed, Aug 6, 2014 at 2:36 AM, Michel Dänzer mic...@daenzer.net wrote:
On 06.08.2014 18:28, Michel Dänzer wrote:
On
Red-only formats should be x001 and RG formats should be xy01.
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/mesa/main/formats.csv | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index
Michael,
With the two patches I just sent to the list, the generated format_info
structure is now binary-identical to the original structure commited to git
with the following two exceptions: The string name parameter for
MESA_FORMAT_R9G9B9E5_FLOAT was updated from MESA_FORMAT_RGB9_E5 to
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/mesa/main/formats.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index f45e34b..eade6fa 100644
--- a/src/mesa/main/formats.csv
+++
FYI, it seems to be DrawPixels(GL_STENCIL_INDEX) that is broken. We
actually use S8 texturing for DrawPixels and some of the functions you
changed probably don't support S8 anymore.
Marek
On Wed, Aug 6, 2014 at 7:37 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
Michael,
With the two patches I
On Tue, Aug 5, 2014 at 10:21 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Thu, Jul 24, 2014 at 07:54:15PM -0700, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 24
src/mesa/drivers/dri/i965/brw_cfg.h | 2 ++
2 files changed, 26
On Wed, Aug 6, 2014 at 5:22 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Tue, Aug 05, 2014 at 09:14:55PM +0300, Pohjolainen, Topi wrote:
On Thu, Jul 24, 2014 at 07:54:12PM -0700, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_cfg.h | 8
1 file changed, 8
From: Ville Syrjälä ville.syrj...@linux.intel.com
I had a few rainy days during my summer vacation so I decided to fix a
chromnium-bsu texturing problem that was nagging me for a while now. I
ended up fixing a few other things too that I spotted mostly from reading
the code.
The aniso vs. mip
From: Ville Syrjälä ville.syrj...@linux.intel.com
Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.
Bugzilla:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Check that the target is GL_TEXTURE_CUBE_MAP before emitting
TEXCOORDTYPE_VECTOR texture coordinates.
I'm not sure if the hardware would like CARTESIAN coordinates
with cube maps, and as I'm too lazy to find out just emit the
VECTOR coordinates
From: Ville Syrjälä ville.syrj...@linux.intel.com
ctx.hw_stencil is not used anywhere so kill it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
src/mesa/drivers/dri/i915/intel_context.c | 1 -
src/mesa/drivers/dri/i915/intel_context.h | 1 -
2 files changed, 2 deletions(-)
From: Ville Syrjälä ville.syrj...@linux.intel.com
Gen2 doesn't support depth/stencil textures, and since
commit c1d4d4999303f9167b20f4e0674b9436e6295cf7
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Thu Apr 24 14:11:43 2014 +0300
i915: Don't advertise Z formats in
From: Ville Syrjälä ville.syrj...@linux.intel.com
According to gen2 BSpec the pipeline must be flushed at least up to the
windower before changing the scissor rect enable field. Emitting the
3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient
to do that.
gen3 BSpec no longer
From: Ville Syrjälä ville.syrj...@linux.intel.com
Gen2 doesn't have fragmnts shaders so we shouldn't be calling
_mesa_meta_glsl_Clear() on gen2. Restore the appropriate
ARB_fragment_shader check to the clear path which was lost in:
commit 94f22fbe787214580a1a13a774114d2650c166cb
Author: Tapani
From: Ville Syrjälä ville.syrj...@linux.intel.com
TEXTURE_SET() is the only register macro that forgets to wrap the
argument evaluation in parens. Only simple integers are passed to this
macro so there's no bug but sitll it seems prudent to add the
parens.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
gen2 doesn't supporte linear mip filter with anisotropic min/mag
filtering. The hardware would automagically downgrade the min/mag
filters to linear in such cases, which IMO looks worse than forcing
the mip filter to nearest.
Signed-off-by: Ville
From: Ville Syrjälä ville.syrj...@linux.intel.com
The spec says using DOT4 for alpha is undefined unless DOT4 is also used
for color. It seems to do the right thing anyway, but better safe than sorry.
Also override numAlphaArgs to 2 for DOT4 since that's what it wants.
This migth fix something
On Wed, Aug 6, 2014 at 9:50 AM, Neil Roberts n...@linux.intel.com wrote:
I'd just liked to point out that I made a nearly identical patch before
this patch was posted but I didn't get any review despite prodding
people a few times on #dri-devel. Maybe we should try to get into the
habit of
Yes -- there's no interaction between patches 3 and 4. Blorp only
shares the generator.
On Tue, Aug 5, 2014 at 1:32 PM, Ian Romanick i...@freedesktop.org wrote:
Does it still build with patch 3 without patch 4?
On 08/04/2014 01:58 AM, Chris Forbes wrote:
Signed-off-by: Chris Forbes
Does this actually work on all Gen7?
The IVB PRM Vol 4 Part 1 Page 83 says:
Errata: BC6H_SF16, BC6H_UF16, and BC7_SRGB are not supported and
may result in data corruption if used.
On Thu, Aug 7, 2014 at 4:27 AM, Neil Roberts n...@linux.intel.com wrote:
Here is a v2 of the BPTC texture
I'd like to start merging the VC4 driver. I've got a lot of things
working under sim (piglit's at 5212/6726 for a slightly-trimmed
quick.py), and once I find where I put my serial cable I hope to get the
kernel fixed up and passing even more than that on HW.
I'm at 80 commits right now, with 3
ville.syrj...@linux.intel.com writes:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we
On 08/06/2014 12:40 PM, Chris Forbes wrote:
Yes -- there's no interaction between patches 3 and 4. Blorp only
shares the generator.
Okay. Then these two are also
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On Tue, Aug 5, 2014 at 1:32 PM, Ian Romanick i...@freedesktop.org wrote:
Does
ville.syrj...@linux.intel.com writes:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Gen2 doesn't have fragmnts shaders so we shouldn't be calling
spelling^
Other than that, patches 4-9 are:
Reviewed-by: Eric Anholt e...@anholt.net
pgp3isQE9B0y5.pgp
Description: PGP
OK, assuming no one complains, I'll push the series later today.
On Thu, Aug 7, 2014 at 8:44 AM, Ian Romanick i...@freedesktop.org wrote:
On 08/06/2014 12:40 PM, Chris Forbes wrote:
Yes -- there's no interaction between patches 3 and 4. Blorp only
shares the generator.
Okay. Then these two
Am 06.08.2014 22:33, schrieb Eric Anholt:
I'd like to start merging the VC4 driver. I've got a lot of things
working under sim (piglit's at 5212/6726 for a slightly-trimmed
quick.py), and once I find where I put my serial cable I hope to get the
kernel fixed up and passing even more than that
Signed-off-by: Jan Vesely jan.ves...@rutgers.edu
---
src/gallium/drivers/r600/evergreen_compute.c | 14 --
src/gallium/drivers/r600/evergreen_compute.h | 1 -
src/gallium/drivers/radeonsi/si_compute.c| 6 +++---
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git
Signed-off-by: Jan Vesely jan.ves...@rutgers.edu
---
src/gallium/state_trackers/clover/core/kernel.cpp | 162 --
1 file changed, 85 insertions(+), 77 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp
Future commits add implicit parameters so
we can no longer rely on shader param size
Signed-off-by: Jan Vesely jan.ves...@rutgers.edu
---
src/gallium/drivers/ilo/ilo_gpgpu.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 2 +-
This respin includes Francisco's approach of providing implicit
in the arg vector passed from clover, and Tom's idea of appending
implicit args after the kernel args.
I assumed it's not safe to modify exec.input, so the input vector is copied
before appending work dim.
Passes get-work-dim piglit
On Wed, Aug 6, 2014 at 10:31 AM, Jason Ekstrand ja...@jlekstrand.net wrote:
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/mesa/main/formats.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index
From: Marek Olšák marek.ol...@amd.com
This will help to get rid of the buffer_get_virtual_address calls.
---
src/gallium/drivers/radeon/r600_buffer_common.c | 7 +--
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_texture.c | 1 +
3 files changed,
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_compute.c | 10
src/gallium/drivers/radeonsi/si_descriptors.c | 33 ---
src/gallium/drivers/radeonsi/si_dma.c | 12 +-
src/gallium/drivers/radeonsi/si_hw_context.c | 2
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_cs.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_cs.h
b/src/gallium/drivers/radeon/r600_cs.h
index b30b465..3cee760 100644
--- a/src/gallium/drivers/radeon/r600_cs.h
+++
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/evergreen_compute.c| 5 +--
src/gallium/drivers/r600/evergreen_hw_context.c | 6 ++--
src/gallium/drivers/r600/evergreen_state.c | 47 +++--
src/gallium/drivers/r600/r600_hw_context.c | 4 +--
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_query.c | 14 ++
src/gallium/drivers/radeon/r600_streamout.c | 9 +++--
src/gallium/drivers/radeon/r600_texture.c | 12 +---
3 files changed, 14 insertions(+), 21 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
R600-R700 don't support virtual memory.
---
src/gallium/drivers/r600/r600_state.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
On Wed, Aug 6, 2014 at 11:19 AM, Matt Turner matts...@gmail.com wrote:
On Tue, Aug 5, 2014 at 10:21 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Thu, Jul 24, 2014 at 07:54:15PM -0700, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 24
From: Marek Olšák marek.ol...@amd.com
This limit is fixed in Mesa core and cannot be changed.
It only affects ARB_vertex_program and ARB_fragment_program.
The minimum value for ARB_vertex_program is 1 according to the spec.
The maximum value for ARB_vertex_program is limited to 1 by Mesa core.
Roland Scheidegger srol...@vmware.com writes:
Am 06.08.2014 22:33, schrieb Eric Anholt:
+ * When building using the simulator (on x86), we advertise ourselves as the
+ * i965 driver so that you can just make a directory with a link from
+ * i965_dri.so to the built vc4_dri.so, and point
https://bugs.freedesktop.org/show_bug.cgi?id=82268
Priority: medium
Bug ID: 82268
Assignee: mesa-dev@lists.freedesktop.org
Summary: Add support for the OpenRISC architecture (or1k)
Severity: enhancement
Classification: Unclassified
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