On Fri, Sep 19, 2014 at 07:57:00PM -0700, Matt Turner wrote:
---
This also means I'll drop 05/20.
v2: Just pass block to emit_before(), rather than trying to get rid
of emit_before().
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
On 24.09.2014 14:01, Ilia Mirkin wrote:
For 3d textures, NumLayers is set to 1, which is not what we want. This
fixes the newly added gl-layer-render-storage test (which constructs
immutable 3d textures). Fixes regression introduced in d82bd7eb060.
Bugzilla:
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #14 from smoki smoki00...@gmail.com ---
Tried both patches, neither does not fix the bug.
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https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #15 from Ilia Mirkin imir...@alum.mit.edu ---
(In reply to comment #14)
Tried both patches, neither does not fix the bug.
Which patches are both patches? Can you confirm whether
http://patchwork.freedesktop.org/patch/34010/ has any
https://bugs.freedesktop.org/show_bug.cgi?id=84145
Benjamin Bellec b.bel...@gmail.com changed:
What|Removed |Added
CC||b.bel...@gmail.com
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #17 from smoki smoki00...@gmail.com ---
Created attachment 106762
-- https://bugs.freedesktop.org/attachment.cgi?id=106762action=edit
borked.jpg
(In reply to comment #15)
(In reply to comment #14)
Tried both patches, neither
On Tuesday, September 23, 2014 01:25:55 PM Matt Turner wrote:
On Tue, Sep 23, 2014 at 1:10 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
On Thu, Aug 28, 2014 at 8:10 PM, Matt Turner matts...@gmail.com wrote:
+int jump = brw_inst_imm_d(brw, insn);
+int jump_compacted
On Friday, September 19, 2014 05:47:58 PM Matt Turner wrote:
On Thu, Aug 28, 2014 at 8:10 PM, Matt Turner matts...@gmail.com wrote:
This series adds instruction compaction support for G45 and Gen5
and enables compaction of control flow instructions.
Ken reviewed the first four patches I
Maybe something similar also needs to be done for cubemaps, because
they are just layered textures in disguise?
Marek
On Wed, Sep 24, 2014 at 7:01 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
For 3d textures, NumLayers is set to 1, which is not what we want. This
fixes the newly added
https://bugs.freedesktop.org/show_bug.cgi?id=84186
Michel Dänzer mic...@daenzer.net changed:
What|Removed |Added
Assignee|xorg-driver-...@lists.x.org
On 22/09/14 00:44, Emil Velikov wrote:
Avoid building the relatively large object every time and forcing
on the non-vl targets. This gives us the following size improvement
textdata bss dec hex filename
5898697 189212 1977864 8065773 7b12ed before/nouveau_dri.so
5771203
ubo offsets are assigned by link_uniform_blocks since 514f8c7e
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/link_uniforms.cpp | 34 --
src/glsl/linker.h | 3 ---
2 files changed, 37 deletions(-)
diff --git a/src/glsl/link_uniforms.cpp
On Wed, Sep 24, 2014 at 4:10 AM, Ian Romanick i...@freedesktop.org wrote:
On 09/23/2014 03:39 PM, Erik Faye-Lund wrote:
Our current atan()-approximation is pretty inaccurate at 1.0, so
let's try to improve the situation by doing a direct approximation
without going through atan.
This new
On 23/09/14 21:23, Tom Stellard wrote:
LLVM commit r218316 removes the JITMemoryManager class, which is
the parent for a seemingly important class in gallivm. In order to
fix the build, I've wrapped most of lp_bld_misc.cpp in
if HAVE_LLVM 0x0306 and modifyed the
Tapani Pälli tapani.pa...@intel.com writes:
Patch fixes the slot count used by vector types and adds 1 slot
to be used by image and sampler types.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
https://bugs.freedesktop.org/show_bug.cgi?id=82921
---
src/glsl/glsl_types.cpp | 18
Hi Matt,
Am Montag, 22. September 2014, 11:48:29 schrieb Matt Turner:
On Fri, Sep 12, 2014 at 4:56 AM, Marc Dietrich marvi...@gmx.de wrote:
File specific optimization as used for src/mesa/main/streaming-load-memcpy.c
currently will cause problems with LTO in the future
(see:
Hello,
Thanks for the reply. I'll download and build piglit, take a look at the
various tests written in it and either come up with a project to work on,
or wait for some ideas from mentors to take on as a project. I will like to
know whether any documentation work could be a viable project?
Hey guys,
I don't think this is a Mesa issue but I didn't know where else to
start. I tried using the #radeon channel but it wont let me post
anything.
I'm having some corruption and freezing issues with my 6670 that I would
like to help find the cause of. For more details and a screenshot see:
On Wed, Sep 24, 2014 at 9:31 AM, Timothy Arceri t_arc...@yahoo.com.au wrote:
Hey guys,
I don't think this is a Mesa issue but I didn't know where else to
start. I tried using the #radeon channel but it wont let me post
anything.
I'm having some corruption and freezing issues with my 6670
On Wed, Sep 24, 2014 at 8:31 AM, Timothy Arceri t_arc...@yahoo.com.au wrote:
Hey guys,
I don't think this is a Mesa issue but I didn't know where else to
start. I tried using the #radeon channel but it wont let me post
anything.
You have to be a registered user with nickserv on freenode to
And use pass caller= for _mesa_FramebufferTexture().
---
src/mesa/main/fbobject.c | 60 +++---
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index ae3a418..8283373 100644
---
Hi Juliet,
There's definitely work that can be done for Piglit. For example,
porting the old Glean tests to piglit's framework.
I suggest we move this conversation to the Piglit mailing list though.
The list is pig...@lists.freedesktop.org and you can subscribe at
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #18 from Christoph Haag haa...@frickel.club ---
Weird.
Mesa git master + *only* the last patch did fix it for me.
--
You are receiving this mail because:
You are the assignee for the bug.
Hi Jose,
On Wednesday, September 24, 2014 12:42:24 Jose Fonseca wrote:
That said, the way we use these things are still a bit in flux. Mathias
has some pending patches. BTW, Mathis, should I submit your patches
for making llvmpipe thread safe? Also, what are your thoughts on this
The disguise of cubemap's layeredness is insufficient to trip up this
code :) They still get their NumLayers set, and the resources still
have an array size. Perhaps there's a scenario I'm not considering?
On Wed, Sep 24, 2014 at 5:23 AM, Marek Olšák mar...@gmail.com wrote:
Maybe something
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #19 from smoki smoki00...@gmail.com ---
(In reply to comment #18)
Weird.
Mesa git master + *only* the last patch did fix it for me.
Weird or not, doublechecked and it does not work for me :). Previosly patched
with
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #20 from smoki smoki00...@gmail.com ---
Oh my it worked :), it is about s3tc i removed lib so picture is without s3tc
:D https://bugs.freedesktop.org/attachment.cgi?id=106762
So yeah, it is fixed for me too.
--
You are
Hi Emil,
-Original Message-
From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
Sent: Tuesday, September 23, 2014 3:49 PM
To: Liu, Leo; mesa-dev@lists.freedesktop.org
Cc: emil.l.veli...@gmail.com; Koenig, Christian
Subject: Re: [Mesa-dev] [PATCH 2/6] st/va: skeleton VAAPI state tracker
Nice catch.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 09/24/2014 04:09 AM, Tapani Pälli wrote:
ubo offsets are assigned by link_uniform_blocks since 514f8c7e
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/link_uniforms.cpp | 34
Cubemaps have array_size == 1, but you can still set the target to 2D
and set first_layer = last_layer = 6 in the sample view. Instead of
checking array_size, maybe NumLayers should be used instead. Just
guessing.
Marek
On Wed, Sep 24, 2014 at 5:05 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Wed, Sep 24, 2014 at 12:20 PM, Marek Olšák mar...@gmail.com wrote:
Cubemaps have array_size == 1, but you can still set the target to 2D
Are you *sure* about that? Everything I'm seeing indicates that
cubemaps have array_size == 6. For example this code in nv50_tex.c:
depth =
Le mardi 23 septembre 2014, 16:23:03 Tom Stellard a écrit :
LLVM commit r218316 removes the JITMemoryManager class, which is
the parent for a seemingly important class in gallivm. In order to
fix the build, I've wrapped most of lp_bld_misc.cpp in
if HAVE_LLVM 0x0306 and modifyed the
On Tue, Sep 23, 2014 at 12:50 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
On Thu, Aug 28, 2014 at 8:10 PM, Matt Turner matts...@gmail.com wrote:
The array was previously indexed in units of brw_compact_inst (8-bytes),
but before compaction all instructions are uncompacted, so every odd
Reviewed-by: Matt Turner matts...@gmail.com
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On Wed, Aug 27, 2014 at 4:12 AM, Tapani Pälli tapani.pa...@intel.com wrote:
Patch fixes the slot count used by vector types and adds 1 slot
to be used by image and sampler types.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
https://bugs.freedesktop.org/show_bug.cgi?id=82921
Prefix with
Interesting, I didn't know about that. Nevermind. st/mesa indeed sets it to 6.
Marek
On Wed, Sep 24, 2014 at 6:26 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Wed, Sep 24, 2014 at 12:20 PM, Marek Olšák mar...@gmail.com wrote:
Cubemaps have array_size == 1, but you can still set the target to
Yes cubemaps should have array_size == 6 always in gallium. You just
have to be careful whenever translating things from mesa to gallium as
things like that won't be true in core mesa of course (similar to 1d
array textures having height and so on) due to OpenGL weirdness for
historical reasons.
On 08/28/2014 08:10 PM, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 5617947..dd32175
There are a bunch of other places that do special things for
BRW_OPCODE_NOP. Do any of those also need changes?
On 08/28/2014 08:10 PM, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_disasm.c | 5 +++--
2 files changed, 4 insertions(+),
On 08/28/2014 08:10 PM, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 39
++
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index
From: Christian König christian.koe...@amd.com
This patch adds a skeleton VA-API state tracker,
which is filled with live in the subsequent patches.
v2: fixes in configure.ac and va state_tracker Makefile.am
Signed-off-by: Christian König christian.koe...@amd.com
Signed-off-by: Leo Liu
Patches 1 through 4, 6, and 14 are
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Assuming sufficient pigliting, patch 9 is
Acked-by: Ian Romanick ian.d.roman...@intel.com
I sent a couple minor questions on a few others. The remaining will be
left to more capable hands.
On 08/28/2014
On Wed, Sep 24, 2014 at 10:36 AM, Ian Romanick i...@freedesktop.org wrote:
On 08/28/2014 08:10 PM, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git
On Wed, Sep 24, 2014 at 10:41 AM, Ian Romanick i...@freedesktop.org wrote:
There are a bunch of other places that do special things for
BRW_OPCODE_NOP. Do any of those also need changes?
There's really not many. The main use of NOP is when we change the
opcode of an instruction we want to
On Wed, Sep 24, 2014 at 10:43 AM, Ian Romanick i...@freedesktop.org wrote:
On 08/28/2014 08:10 PM, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 39
++
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git
Marek/Roland -- do either of those comments count as a R-b? I'd like
to push this out tonight, pending a full piglit run.
On Wed, Sep 24, 2014 at 1:35 PM, Roland Scheidegger srol...@vmware.com wrote:
Yes cubemaps should have array_size == 6 always in gallium. You just
have to be careful
On Mon, Sep 22, 2014 at 5:11 AM, Tapani Pälli tapani.pa...@intel.com wrote:
From: Kalyan Kondapally kalyan.kondapa...@intel.com
According to GLSL(4.2) and GLSL-ES (1.0, 3.0) spec, Structures must
have the same name to be considered same type. We currently ignore
the name check while checking
On Mon, Sep 22, 2014 at 5:11 AM, Tapani Pälli tapani.pa...@intel.com wrote:
From: Kalyan Kondapally kalyan.kondapa...@intel.com
According to GLSL(4.2) and GLSL-ES (1.0, 3.0) spec, Structures must
have the same name to be considered same type. We currently ignore
the name check while checking
Hi,
On Wednesday, September 24, 2014 12:42:24 Jose Fonseca wrote:
We're not the only one with similar needs. Webkit has similar needs.
Though they opted by using LLVMCreateSimpleMCJITMemoryManager
https://trac.webkit.org/browser/trunk/Tools/ReducedFTL/ReducedFTL.c#L321
and implemeting
From: Damien Lespiau damien.lesp...@intel.com
This commands has seen the addition of 2 dwords that allow to specify
which channels of which attributes need to be forwarded to the fragment
shader.
v2: Rebase forward a year (done by Ken).
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
On Skylake, the MOCS bits are an index into a table of 63 different,
configurable cache configurations. As for previous GENs, we only care about
WB and WT, which are available in the documented default set. Define
SKL_MOCS_WB and SKL_MOCS_WT to the indices for those configucations and use
those
From: Kenneth Graunke kenn...@whitecape.org
Otherwise they overlap and horrible things happen. All the new DWords
are for fast color clear values, which we don't do yet.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
From: Jordan Justen jordan.l.jus...@intel.com
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 9 +
1 file changed, 9 insertions(+)
diff --git
SKL updates the resolve rectangle scaling factors again.
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
As of BDW, this workaround is no longer necessary: WM HW will internally manage
the draining pipe and flushing of the caches when this commands is issued.
The PIPE_CONTROL restrictions are removed.
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
---
From: Kenneth Graunke kenn...@whitecape.org
On SKL, 3DSTATE_CONSTANT_* command is not committed until we give
the corresponding 3DSTATE_BINDING_TABLE_POINTERS_* command. If we
fail to do so, the constant buffers wont be read and push constants
will be wrong.
Signed-off-by: Kenneth Graunke
From: Kenneth Graunke kenn...@whitecape.org
Skylake has separate controls for enabling the Z Clip Test for the near
and far planes. For now, maintain the legacy behavior by setting both.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
From: Jordan Justen jordan.l.jus...@intel.com
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/intel_screen.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
From: Kenneth Graunke kenn...@whitecape.org
Skylake's 3DSTATE_DS packet has a few more fields; we don't support
domain shaders yet though.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/gen8_disable.c | 15
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
---
include/pci_ids/i965_pci_ids.h | 15 +++
src/mesa/drivers/dri/i965/brw_device_info.c | 29 +
2 files changed, 44 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h
From: Kenneth Graunke kenn...@whitecape.org
Skylake introduces a new base address for a feature we don't yet expose.
Setting these to 0 should be safe.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
They are the same as for BDW, so just add a case for SKL to the init switch.
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
From: Kenneth Graunke kenn...@whitecape.org
Skylake uploads the stencil reference values in DW3 of the
3DSTATE_WM_DEPTH_STENCIL packet, rather than in COLOR_CALC_STATE.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
From: Kenneth Graunke kenn...@whitecape.org
We will need to allocate more DWords on Skylake.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 26 --
1 file changed,
From: Kenneth Graunke kenn...@whitecape.org
Skylake has some extra bits in PIPELINE_SELECT, none of which are
interesting for a 3D driver. In order to selectively change them, it
also introduces new mask bits in 15:8. We care about the Pipeline
Selection bits (1:0), so set the mask to 0x3.
Here's a set of 16 patches to bring up mesa on Skylake (GEN 9). This is
just initial enabling, there's more work to do. Most patches have been
written/reviewed/signed-off by at least two developers and are ready to go.
There are a few new patches from me in the set that haven't been reviewed
Roland Scheidegger srol...@vmware.com writes:
Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
to util code. That plus the things I already mentioned should be all
needed I think. But I strongly believe either this needs to be done or
we should revert it.
What's the
On Wednesday, September 24, 2014 12:28:20 PM Kristian Høgsberg wrote:
On Skylake, the MOCS bits are an index into a table of 63 different,
configurable cache configurations. As for previous GENs, we only care about
WB and WT, which are available in the documented default set. Define
On Wednesday, September 24, 2014 12:28:06 PM Kristian Høgsberg wrote:
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
---
include/pci_ids/i965_pci_ids.h | 15 +++
src/mesa/drivers/dri/i965/brw_device_info.c | 29
+
2 files changed,
On Wednesday, September 24, 2014 12:28:13 PM Kristian Høgsberg wrote:
From: Kenneth Graunke kenn...@whitecape.org
Otherwise they overlap and horrible things happen. All the new DWords
are for fast color clear values, which we don't do yet.
This is no longer true. I see nothing prohibiting
On Wednesday, September 24, 2014 12:28:21 PM Kristian Høgsberg wrote:
As of BDW, this workaround is no longer necessary: WM HW will internally
manage
the draining pipe and flushing of the caches when this commands is issued.
The PIPE_CONTROL restrictions are removed.
Signed-off-by: Kristian
On Wed, Sep 24, 2014 at 12:52 PM, Eric Anholt e...@anholt.net wrote:
Roland Scheidegger srol...@vmware.com writes:
Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
to util code. That plus the things I already mentioned should be all
needed I think. But I strongly
On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg k...@bitplanet.net wrote:
They are the same as for BDW, so just add a case for SKL to the init switch.
Confirmed. I should have added case 9 in my series, I suppose.
The BSpec isn't clear, but I think CHV and SKL have the same changes
for
On Wed, Sep 24, 2014 at 11:56 AM, Matt Turner matts...@gmail.com wrote:
On Mon, Sep 22, 2014 at 5:11 AM, Tapani Pälli tapani.pa...@intel.com wrote:
From: Kalyan Kondapally kalyan.kondapa...@intel.com
According to GLSL(4.2) and GLSL-ES (1.0, 3.0) spec, Structures must
have the same name to
On Wed, Sep 24, 2014 at 1:39 PM, kalyan kondapally
kondapallykalyancontrib...@gmail.com wrote:
This would ignore the case when record A is anonymous but record B is not.
Bah, I think you're right.
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mesa-dev mailing list
I don't really qualified to review, IIRC I mentioned it was tricky to
see if it's right when you pushed it first, and this has not changed.
Some comment inline though...
Am 24.09.2014 20:30, schrieb Ilia Mirkin:
Marek/Roland -- do either of those comments count as a R-b? I'd like
to push this
On Wed, Sep 24, 2014 at 5:17 PM, Roland Scheidegger srol...@vmware.com wrote:
I don't really qualified to review, IIRC I mentioned it was tricky to
see if it's right when you pushed it first, and this has not changed.
Some comment inline though...
Am 24.09.2014 20:30, schrieb Ilia Mirkin:
Am 24.09.2014 21:52, schrieb Eric Anholt:
Roland Scheidegger srol...@vmware.com writes:
Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
to util code. That plus the things I already mentioned should be all
needed I think. But I strongly believe either this needs to be
Am 24.09.2014 23:23, schrieb Ilia Mirkin:
On Wed, Sep 24, 2014 at 5:17 PM, Roland Scheidegger srol...@vmware.com
wrote:
I don't really qualified to review, IIRC I mentioned it was tricky to
see if it's right when you pushed it first, and this has not changed.
Some comment inline though...
On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg k...@bitplanet.net wrote:
From: Damien Lespiau damien.lesp...@intel.com
This commands has seen the addition of 2 dwords that allow to specify
which channels of which attributes need to be forwarded to the fragment
shader.
v2: Rebase
On 09/24/2014 12:52 PM, Eric Anholt wrote:
Roland Scheidegger srol...@vmware.com writes:
Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
to util code. That plus the things I already mentioned should be all
needed I think. But I strongly believe either this needs to be
On 25 September 2014 08:51, Ian Romanick i...@freedesktop.org wrote:
On 09/24/2014 12:52 PM, Eric Anholt wrote:
Roland Scheidegger srol...@vmware.com writes:
Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
to util code. That plus the things I already mentioned should
On Wed, Sep 24, 2014 at 3:33 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg k...@bitplanet.net
wrote:
From: Damien Lespiau damien.lesp...@intel.com
This commands has seen the addition of 2 dwords that allow to specify
which channels of which
On Wed, Sep 24, 2014 at 12:57 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On Wednesday, September 24, 2014 12:28:20 PM Kristian Høgsberg wrote:
On Skylake, the MOCS bits are an index into a table of 63 different,
configurable cache configurations. As for previous GENs, we only care
On Wed, Sep 24, 2014 at 3:57 PM, Dave Airlie airl...@gmail.com wrote:
On 25 September 2014 08:51, Ian Romanick i...@freedesktop.org wrote:
On 09/24/2014 12:52 PM, Eric Anholt wrote:
Roland Scheidegger srol...@vmware.com writes:
Oh yes and missing ALIGN + MAX2 too. I guess we could easily move
On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg k...@bitplanet.net wrote:
Here's a set of 16 patches to bring up mesa on Skylake (GEN 9). This is
just initial enabling, there's more work to do. Most patches have been
written/reviewed/signed-off by at least two developers and are ready to
Hi Juliet,
sorry about the delay, thanks for the email. I don't personally work on mesa
so I'll wait if anyone on the list has a project to propose here.
On Sat, Sep 20, 2014 at 07:52:38PM +0100, Juliet Fru wrote:
I am Juliet Fru, a second year student of Computer Engineering at the
University
On Wed, Sep 24, 2014 at 6:25 AM, Marc Dietrich marvi...@gmx.de wrote:
Am Montag, 22. September 2014, 11:48:29 schrieb Matt Turner:
We need a configure check for support for __attribute__((target)). I'm
going to send a series that adds support for this (and does the check
for existing attribute
What happens is that a SPLIT operation is part of the spill node, and as
a pseudo op, the instruction gets erased after processing its first def.
However the later defs still need to refer to it, so instead delay
spilling until after that whole RA node is done processing.
Bugzilla:
From: Michel Dänzer michel.daen...@amd.com
The draw module would still try to use gallivm, causing many piglit tests
to fail with an assertion failure. llvmpipe might have been similarly
affected.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/auxiliary/draw/draw_context.c
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