Restores proper immediate tearing swap behaviour for
OpenGL bufferswap under DRI3/Present.
Cc: "10.3 10.4"
v2: Add Frank Binns signed off by for his original earlier
patch from April 2014, which is identical to this one, and
Chris Wilsons reviewed tag from May 2014 for that patch, ergo
also for
Ok, third iteration of the series. Incorporated all the review
comments of Axel Davy and Eric Anholt and retested for extra
paranoia. Thanks!
-mario
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/m
glXSwapBuffersMscOML() with target_msc=divisor=remainder=0 gets
translated into target_msc=divisor=0 but remainder=1 by the mesa
api. This is done for server DRI2 where there needs to be a way
to tell the server-side DRI2ScheduleSwap implementation if a call
to glXSwapBuffers() or glXSwapBuffersMsc
The code for emitting INTEL_swap_events swap completion
events needs to translate from 32-Bit sbc on the wire to
64-Bit sbc for the events and handle wraparound accordingly.
It assumed that events would be sent by the server in the
order their corresponding swap requests were emitted from
the clie
targetSBC == 0 is a special case, which asks the function
to block until all pending OpenGL bufferswap requests have
completed.
Currently the function just falls through for targetSBC == 0,
returning bogus results.
This breaks applications originally written and tested against
DRI2 which also rel
Prevent calls to glXGetSyncValuesOML() and glXWaitForMscOML()
from overwriting the (ust,msc) values of the last successfull
swapbuffers call (PresentPixmapCompleteNotify event), as
glXWaitForSbcOML() relies on those values corresponding to
the most recent completed swap, not to whatever was last
re
On Friday, November 21, 2014 10:23:43 AM Matt Turner wrote:
> On Tue, Nov 11, 2014 at 9:41 AM, Matt Turner wrote:
> > The rest of our backend optimizations have replaced the need for this
> > since it was written.
> >
> > instructions in affected programs: 30626 -> 30564 (-0.20%)
> >
> > Hurts
Yep, my implementation leaked this detail to be handled by the caller.
This looks nicer as it's all isolated in the class.
Reviewed-by: Tapani Pälli
On 12/05/2014 12:00 AM, Carl Worth wrote:
There is an internal implementation detail that the hash table
underlying the struct string_to_uint_ma
This was an oversight in the original patch. When PolygonMode is
used, then front faces, back faces, or both may be rendered as
points and are affected by point sprite state.
Note that SNB/IVB can't actually be fully conformant here, for
a legacy context -- we don't have separate sets of pointspri
And move it above its first use in brw_fs_generator.cpp.
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 -
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 140 -
2 files changed, 70 insertions(+), 72 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
Now that the caller passes in the shader debug name, we don't need this
anymore.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp| 2 +-
src/mesa/drivers/dri/i965/brw_fs.h | 2 --
src/mesa/d
With everything in place, we can now use the scalar backend compiler for
vertex shaders on BDW+. We make scalar vertex shaders the default on
BDW+ but add a new vec4vs debug option to force the vec4 backend.
No piglit regressions.
Performance impact is minimal, I see a ~1.5 improvement on the T-
We don't propagate the saturate bit and some instructions can't
saturate at all. If the source has saturate set, just skip propagation.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drive
This chunk of code is repeated in a few places, and we're going to add
a MESA_SHADER_VERTEX case to it soon.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 37
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/src/me
This flag signals that we have a SIMD8 VS shader so we can set up the
corresponding state accordingly. This boils down to setting
the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull
constant buffers use dword pitch.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_
These structs aren't vec4 specific, they are shared by shader stages
operating on Vertex URB Entries (VUEs). VUEs are the data structures in
the URB that hold vertex data between the pipeline geometry stages.
Using vue in the name instead of vec4 makes a lot more sense, especially
when we add scal
Here's v3 of the scalar vs series. Changes from v2
- Bail out of constant propagation early if source is saturated (from Matt).
- Fixed the half-finished, broken vec4 -> vue key and prog_data rename.
- Add '***' around attr regsisters in debug output if they end up
as destinations.
- Ad
This is all we need from the generator for SIMD8 vertex shaders. This
opcode is just the send instruction, all the hard work will happen
in the visitor using LOAD_PAYLOAD.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
src/mesa/drivers/dri/i965/
Now that fs_visitor::run is back to being only fragment
shader compilation, we can clean up a few stage == MESA_SHADER_FRAGMENT
conditions and rename it to run_fs.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 32 ++--
src/mesa/drivers/dr
fs_generator no longer knows what stage it's generating code for, so
we have to set the debug name of the shader from the call site.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 4 +++-
src/mesa/drivers/dri/i965/brw_fs.cpp| 17 --
The scalar vertex shader will use the ATTR register file for vertex
attributes. This patch adds support for the ATTR file to fs_visitor.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
This patch uses the previous refactoring to add a new run_vs() method
that generates vertex shader code using the scalar visitor and
optimizer.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 111 +-
src/mesa/drivers/dri/i965/brw_fs.h | 21 +
This removes all stage specific data from the generator, and lets us
create a generator for any stage.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 5 ++---
src/mesa/drivers/dri/i965/brw_fs.cpp| 2 +-
src/mesa/drivers/dri/i965/brw_fs.h
On Thu, Dec 4, 2014 at 7:54 PM, Carl Worth wrote:
> On Thu, Dec 04 2014, Carl Worth wrote:
>> So I think I'll follow up with a separate patch to clean these up.
>
> Before I do that, I noticed the following in util/macros.h:
>
> /**
> * Unreachable macro. Useful for suppressing "c
On 12/03/2014 05:42 PM, Kenneth Graunke wrote:
> BRW_NEW_VERTICES is flagged every time we draw a primitive. Having
> the brw_vs_prog atom depend on BRW_NEW_VERTICES meant that we had to
> compute the VS program key and do a program cache lookup for every
> single primitive. This is painfully exp
On Thu, Dec 04, 2014 at 07:48:06PM -0800, Ben Widawsky wrote:
> On Thu, Dec 04, 2014 at 05:08:21PM -0800, Matt Turner wrote:
> > On Thu, Dec 4, 2014 at 3:37 PM, Ben Widawsky
> > wrote:
> > > The GS has an interesting use for mul. It's essentially used as a fancy
> > > mov (in
> > > fact, I am not
On Thu, Dec 04, 2014 at 05:17:05PM -0800, Kenneth Graunke wrote:
> On Thursday, December 04, 2014 03:37:17 PM Ben Widawsky wrote:
> > The GS has an interesting use for mul. It's essentially used as a fancy mov
> > (in
> > fact, I am not sure why a mov isn't used). The documentation in the
> > fun
On Thu, Dec 04 2014, Carl Worth wrote:
> So I think I'll follow up with a separate patch to clean these up.
Before I do that, I noticed the following in util/macros.h:
/**
* Unreachable macro. Useful for suppressing "control reaches end of
non-void
* function" warnings.
On Thu, Dec 04, 2014 at 05:08:21PM -0800, Matt Turner wrote:
> On Thu, Dec 4, 2014 at 3:37 PM, Ben Widawsky
> wrote:
> > The GS has an interesting use for mul. It's essentially used as a fancy mov
> > (in
> > fact, I am not sure why a mov isn't used). The documentation in the
> > function has
>
On Thu, Dec 04 2014, Matt Turner wrote:
> On Thu, Dec 4, 2014 at 2:00 PM, Carl Worth wrote:
>> + assert(!"Should not get here.");
>> + return error_type;
>
> Let's just use unreachable("not reached") here.
That's a good idea. I copied this line from the surrounding code in the
same file, (the
On Thu, Dec 04 2014, Ian Romanick wrote:
> Shouldn't type be glsl_base_type instead of unsigned?
Yes, thanks for the catch. Fixed.
>> + if (shadow)
>> +return (array ? sampler2DArrayShadow_type : sampler2DShadow_type
>> +);
>
> It's weird that the closing paren ended up here.
On Thu, Dec 4, 2014 at 7:34 PM, Brian Paul wrote:
> On 12/04/2014 05:01 PM, Ilia Mirkin wrote:
>>
>> Signed-off-by: Ilia Mirkin
>> Cc: "10.3 10.4"
>> ---
>> src/gallium/auxiliary/indices/u_primconvert.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/src/gallium/auxiliary/indice
On Thu, Dec 4, 2014 at 6:54 PM, Ian Romanick wrote:
> On 12/04/2014 04:33 PM, Matt Turner wrote:
>> On Thu, Dec 4, 2014 at 4:26 PM, Ian Romanick wrote:
>>> On 12/04/2014 03:05 PM, Matt Turner wrote:
Jason realized that we could fix the result of the CMP instruction on
Gen <= 5 by doing
On Thu, Dec 04 2014, Ian Romanick wrote:
> Should this just get squashed with the previous commit?
Yes. I only hesitated because I wrote the second and not the first, (so
I didn't want to lose authorship in the history).
But it's not useful to have an iterate in the history that actually does
the
On 12/04/2014 04:37 PM, Matt Turner wrote:
> The LINE instruction performs a multiply-add instruction (a * b + c)
> where b and c are scalar arguments. It reads b and c from offsets in
> src0 such that you can load them (it they're representable) as a
> vector-float immediate with a single instruct
On 12/04/2014 04:37 PM, Matt Turner wrote:
> The LINE instruction performs a multiply-add instruction (a * b + c)
> where b and c are scalar arguments. It reads b and c from offsets in
> src0 such that you can load them (it they're representable) as a
if?
> vect
On 12/04/2014 06:06 PM, Matt Turner wrote:
> On Fri, Nov 21, 2014 at 10:23 AM, Matt Turner wrote:
>> Thoughts?
>
> Ping^2
Seems reasonable enough... any progress on the "common ternary pattern"
better? (I deleted the original message, so I reviewed the patch from
the list archive.)
> _
On 12/04/2014 04:33 PM, Matt Turner wrote:
> On Thu, Dec 4, 2014 at 4:26 PM, Ian Romanick wrote:
>> On 12/04/2014 03:05 PM, Matt Turner wrote:
>>> Jason realized that we could fix the result of the CMP instruction on
>>> Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
>>> backend
Mario Kleiner writes:
> A slightly updated and extended series of the dri3/present fixes for Mesa i
> sent last week.
>
> Patch 1 and 2 are same as before. Patch 3 now has signed off by Frank Binns
> and reviewed by Chris Wilson. Patch 4 and 5 are additional fixes. The last
> one makes INTEL_swap
Mario Kleiner writes:
> Restores proper immediate tearing swap behaviour for
> OpenGL bufferswap under DRI3/Present.
>
> Cc: "10.3 10.4"
>
> v2: Add Frank Binns signed off by for his original earlier
> patch from April 2014, which is identical to this one, and
> Chris Wilsons reviewed tag from M
Mario Kleiner writes:
> On 12/04/2014 11:48 AM, Axel Davy wrote:
>> Le 04/12/2014 11:44, Axel Davy a écrit :
>>> On 02/12/2014 20:53, Mario Kleiner wrote :
targetSBC == 0 is a special case, which asks the function
to block until all pending OpenGL bufferswap requests have
completed
Mario Kleiner writes:
> glXSwapBuffersMscOML() with target_msc=divisor=remainder=0 gets
> translated into target_msc=divisor=0 but remainder=1 by the mesa
> api. This is done for server DRI2 where there needs to be a way
> to tell the server-side DRI2ScheduleSwap implementation if a call
> to glX
https://bugs.freedesktop.org/show_bug.cgi?id=86980
Vinson Lee changed:
What|Removed |Added
Blocks||79706
--
You are receiving this mail becau
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Vinson Lee changed:
What|Removed |Added
Depends on||86980
--
You are receiving this mail becau
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Vinson Lee changed:
What|Removed |Added
Depends on||86944
--
You are receiving this mail becau
https://bugs.freedesktop.org/show_bug.cgi?id=86944
Vinson Lee changed:
What|Removed |Added
Blocks||79706
--
You are receiving this mail becau
https://bugs.freedesktop.org/show_bug.cgi?id=86939
Vinson Lee changed:
What|Removed |Added
Blocks||79706
--
You are receiving this mail becau
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Vinson Lee changed:
What|Removed |Added
Depends on||86939
--
You are receiving this mail becau
Matt Turner writes:
> Cuts an instruction from two shaders in Tesseract, by allowing the
> (x+y) cmp 0 -> x cmp -y optimization to take place.
>
> instructions in affected programs: 1198 -> 1194 (-0.33%)
Reviewed-by: Eric Anholt
signature.asc
Description: PGP signature
___
On Fri, Nov 21, 2014 at 10:23 AM, Matt Turner wrote:
> Thoughts?
Ping^2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Cuts an instruction from two shaders in Tesseract, by allowing the
(x+y) cmp 0 -> x cmp -y optimization to take place.
instructions in affected programs: 1198 -> 1194 (-0.33%)
---
src/glsl/opt_algebraic.cpp | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/glsl/opt_algebraic
On Thu, Dec 4, 2014 at 5:48 PM, Kenneth Graunke wrote:
> Some comments would be nice:
>
> /**
> * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
> *
> * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
> * If we need a proper boolean value, we have to
On Thursday, December 04, 2014 03:05:59 PM Matt Turner wrote:
> Jason realized that we could fix the result of the CMP instruction on
> Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
> backend before use, rather than when the bool was created. The FS does
> this and it saves some
Hello,
Building recent mesa git i found that most video players that use VDPAu
hardware decoding fail with
vl/vl_stubs.c:45:vl_video_buffer_formats: Assertion `0' failed.
Trace/breakpoint trap
for example trying to play a 1080p h264 video that worked with hw
decoding:
$ mpv /media/bigdata/
On Thursday, December 04, 2014 03:37:17 PM Ben Widawsky wrote:
> The GS has an interesting use for mul. It's essentially used as a fancy mov
> (in
> fact, I am not sure why a mov isn't used). The documentation in the function
> has
> a very good explanation from Paul on the mechanics.
>
> CHV ha
On Thu, Dec 4, 2014 at 3:37 PM, Ben Widawsky
wrote:
> The GS has an interesting use for mul. It's essentially used as a fancy mov
> (in
> fact, I am not sure why a mov isn't used). The documentation in the function
> has
> a very good explanation from Paul on the mechanics.
What do you mean? Th
LGTM. Reviewed-by: Brian Paul
On 12/04/2014 04:25 PM, srol...@vmware.com wrote:
From: Roland Scheidegger
The original idea was to optimize away the condition by integrating it directly
into the CMP instruction. However, with native integers this requires an extra
I2F instruction. It is also
Safe from causing optimization loops, since we don't constant propagate
VF arguments.
(for this and the previous patch):
total instructions in shared programs: 4289075 -> 4271932 (-0.40%)
instructions in affected programs: 1616779 -> 1599636 (-1.06%)
---
src/mesa/drivers/dri/i965/brw_fs_cse.c
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 4ae35ac..2f99d65 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/m
The LINE instruction performs a multiply-add instruction (a * b + c)
where b and c are scalar arguments. It reads b and c from offsets in
src0 such that you can load them (it they're representable) as a
vector-float immediate with a single instruction.
Hurts some programs, but that'll all get bett
The PRMs say that
region must be a replicated scalar
(with HorzStride = VertStride = 0).
but apparently that doesn't actually apply to all generations. I did
notice when implementing the optimization later in this series that G45
and ILK needed this regioning.
---
src/mesa/drivers/dri/i96
On 12/04/2014 05:01 PM, Ilia Mirkin wrote:
Signed-off-by: Ilia Mirkin
Cc: "10.3 10.4"
---
src/gallium/auxiliary/indices/u_primconvert.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/auxiliary/indices/u_primconvert.c
b/src/gallium/auxiliary/indices/u_primconvert.c
index 9
On Thu, Dec 4, 2014 at 4:26 PM, Ian Romanick wrote:
> On 12/04/2014 03:05 PM, Matt Turner wrote:
>> Jason realized that we could fix the result of the CMP instruction on
>> Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
>> backend before use, rather than when the bool was create
On Thu, Dec 4, 2014 at 4:22 PM, Ian Romanick wrote:
> On 12/04/2014 03:05 PM, Matt Turner wrote:
>> This is a revert of commit 4656c14e ("i965/fs: Change the type of
>> booleans to UD and emit correct immediates") plus some small additional
>
> Commit 4656c14e contained some shader-db data... does
On 12/04/2014 03:05 PM, Matt Turner wrote:
> Jason realized that we could fix the result of the CMP instruction on
> Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
> backend before use, rather than when the bool was created. The FS does
> this and it saves some unnecessary resolv
On 12/04/2014 03:05 PM, Matt Turner wrote:
> This is a revert of commit 4656c14e ("i965/fs: Change the type of
> booleans to UD and emit correct immediates") plus some small additional
Commit 4656c14e contained some shader-db data... does this pseudo-revert
have shader-db changes?
> fixes, like c
Matt Turner writes:
> ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 10 ++
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 10 ++
> 2 files changed, 20 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_
This series is
Reviewed-by: Jason Ekstrand
On Thu, Dec 4, 2014 at 3:05 PM, Matt Turner wrote:
> Jason realized that we could fix the result of the CMP instruction on
> Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
> backend before use, rather than when the bool was created.
The index_bias (aka base_vertex) applies to the downstream draw just as
much, since the actual index values are never modified.
Signed-off-by: Ilia Mirkin
Cc: "10.3 10.4"
---
src/gallium/auxiliary/indices/u_primconvert.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/auxiliary/
Signed-off-by: Ilia Mirkin
Cc: "10.4 10.3"
---
src/gallium/auxiliary/indices/u_primconvert.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/indices/u_primconvert.c
b/src/gallium/auxiliary/indices/u_primconvert.c
index 539ca53..4632781 100644
--- a/src/
Signed-off-by: Ilia Mirkin
Cc: "10.3 10.4"
---
src/gallium/auxiliary/indices/u_primconvert.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/auxiliary/indices/u_primconvert.c
b/src/gallium/auxiliary/indices/u_primconvert.c
index 95a2478..539ca53 100644
--- a/src/gallium/auxili
The GS has an interesting use for mul. It's essentially used as a fancy mov (in
fact, I am not sure why a mov isn't used). The documentation in the function has
a very good explanation from Paul on the mechanics.
CHV has some quirks with regard to multiplication. While the documentation is
somewha
From: Roland Scheidegger
The original idea was to optimize away the condition by integrating it directly
into the CMP instruction. However, with native integers this requires an extra
I2F instruction. It is also fishy because the negation used didn't really honor
ieee754 float comparison rules, n
Jason realized that we could fix the result of the CMP instruction on
Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
backend before use, rather than when the bool was created. The FS does
this and it saves some unnecessary resolves.
On Ironlake:
total instructions in shared pro
This is a revert of commit 4656c14e ("i965/fs: Change the type of
booleans to UD and emit correct immediates") plus some small additional
fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD
to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f80
as UD and as a li
---
src/mesa/drivers/dri/i965/brw_fs.h | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index b29b6b0..c7bc55c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -119,6 +119
---
Ken pointed this out in his review, and I fixed it in the FS, but apparently
forgot to fix it in the vec4 code.
src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate
On Thu, Dec 4, 2014 at 2:00 PM, Carl Worth wrote:
> + assert(!"Should not get here.");
> + return error_type;
Let's just use unreachable("not reached") here.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailm
On Wed, Dec 3, 2014 at 5:58 PM, Kenneth Graunke wrote:
> On Tuesday, December 02, 2014 10:34:49 AM Matt Turner wrote:
>> On Tue, Dec 2, 2014 at 3:50 AM, Kenneth Graunke
>> wrote:
>> > The "Pixel Shader Computed Depth Mode" value is entirely based on the
>> > shader program, so we can easily do i
On 12/04/2014 02:00 PM, Carl Worth wrote:
> There is an internal implementation detail that the hash table
> underlying the struct string_to_uint_map stores each value internally
> as (value+1). The user needn't be very concerned with this (other than
> knowing that a value of UINT_MAX cannot be st
On 12/04/2014 02:00 PM, Carl Worth wrote:
> This is similar to the existing functions get_instance, get_array_instance,
> etc. for getting a type singleton. The new get_sampler_instance() function
> will be used by the upcoming shader cache.
> ---
> src/glsl/glsl_types.cpp | 111
> +++
On 12/02/2014 09:54 AM, Ilia Mirkin wrote:
> I believe the issue is that _mesa_TextureView should be checking the
> target internal format against _mesa_base_tex_format() and returning a
> GL_INVALID_VALUE error (? the spec conveniently lists errors as
> 'TODO') if it returns -1. Chris -- thoughts?
Ugh, yes, I'll fix that and land it at the same time.
Thanks :)
On Fri, Dec 5, 2014 at 11:12 AM, Ian Romanick wrote:
> On 11/29/2014 12:54 PM, Chris Forbes wrote:
>> Fixes the piglit test: spec/glsl-es-3.00/compiler/undef-GL_ES.vert
>>
>> Signed-off-by: Chris Forbes
>> ---
>> src/glsl/glcpp/gl
On 11/29/2014 12:54 PM, Chris Forbes wrote:
> Fixes the piglit test: spec/glsl-es-3.00/compiler/undef-GL_ES.vert
>
> Signed-off-by: Chris Forbes
> ---
> src/glsl/glcpp/glcpp-parse.y | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/gls
On 11/04/2014 04:20 AM, Tapani Pälli wrote:
> Note that some of the GLSL specifications explicitly state this as
> compile error, some simply state that 'it is an error'.
>
> Signed-off-by: Tapani Pälli
> ---
> src/glsl/glsl_parser.yy | 13 -
> 1 file changed, 12 insertions(+), 1 del
There is an internal implementation detail that the hash table
underlying the struct string_to_uint_map stores each value internally
as (value+1). The user needn't be very concerned with this (other than
knowing that a value of UINT_MAX cannot be stored) since put() adds 1
and get() subtracts 1.
H
From: Tapani Pälli
Shader binary cache requires this to be able to cache hash data from
the gl_shader_program structure.
Signed-off-by: Tapani Pälli
Reviewed-by: Paul Berry
Reviewed-by: Carl Worth
---
src/mesa/program/hash_table.h | 8
1 file changed, 8 insertions(+)
diff --git a/s
This is similar to the existing functions get_instance, get_array_instance,
etc. for getting a type singleton. The new get_sampler_instance() function
will be used by the upcoming shader cache.
---
src/glsl/glsl_types.cpp | 111
src/glsl/glsl_types.
On 12/04/2014 11:20 AM, Axel Davy wrote:
On 02/12/2014 20:53, Mario Kleiner wrote :
Restores proper immediate tearing swap behaviour for
OpenGL bufferswap under DRI3/Present.
+ if (priv->swap_interval == 0)
+ options |= XCB_PRESENT_OPTION_ASYNC;
+
back->busy = 1;
Cu
On 12/04/2014 11:48 AM, Axel Davy wrote:
Le 04/12/2014 11:44, Axel Davy a écrit :
On 02/12/2014 20:53, Mario Kleiner wrote :
targetSBC == 0 is a special case, which asks the function
to block until all pending OpenGL bufferswap requests have
completed.
Currently the function just falls through
Am 04.12.2014 um 20:49 schrieb Marek Olšák:
> I agree that this should be fixed properly, but my time is limited at
> the moment. We know there's a problem with our shader backend, because
> there are issues with other games too. We can fix it later and we
> certainly won't forget about it.
>
> No
I certainly don't want to deter you from pushing a quick fix now.
If possible I'd just like any further information you might have
collected while debugging this issue in the hope we can figure out a
more comprehensive solution should be.
Because I'm sure other drivers (including VMware's svg
I agree that this should be fixed properly, but my time is limited at
the moment. We know there's a problem with our shader backend, because
there are issues with other games too. We can fix it later and we
certainly won't forget about it.
Note that r600g is using a lot of these non-standard legac
Oh hm. Apparently EXT_sRGB is required for this [or ES3, but that's
not available on the driver I'm interested quite yet]. I'll see if
that can be added easily.
On Thu, Dec 4, 2014 at 12:42 PM, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
> ---
>
> https://www.opengl.org/registry/specs/EXT/te
On Wed, Dec 3, 2014 at 3:53 PM, Ben Widawsky
wrote:
> SKL moves the GS threadcount to dw8 from dw7, and no longer does the divide
> by 2
> thing.
>
> Only compile test.
>
> Cc: Kristian Høgsberg
> Signed-off-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/gen8_gs_state.c | 29 ++
The problem is, while glsl was quite lenient in older versions wrt
precision or things like div by zero, starting with glsl 4.10 you are
_required_ to return +-/Inf for divs by zero. Hence if you use hacks
here to make some app run, you _will_ have to fix that properly in the
future in any case.
(T
https://bugs.freedesktop.org/show_bug.cgi?id=84186
Mathias Brodala changed:
What|Removed |Added
CC|i...@noctus.net |
--
You are receiving this mail becau
I'm also concerned this sort of ad-hoc re-interpretation of opcode
semantics will come to bytes us later, as different state trackers might
want different semantics.
I think we might need to redefine TGSI_OPCODE_RCP opcode or introduce a
TGSI_OPCODE_RCP_LEGACY opcode.
Also, do we know exactl
Returning FLT_MAX instead of 0 also works, which is similar to another
hw instruction: V_RCP_CLAMP_F32.
The Unreal engine is a pretty big target with a lot of apps out there.
I'm afraid a driconf option isn't feasible.
Marek
On Thu, Dec 4, 2014 at 5:39 PM, Roland Scheidegger wrote:
> Hmm I have
Signed-off-by: Ilia Mirkin
---
https://www.opengl.org/registry/specs/EXT/texture_sRGB_decode.txt
Explicitly talks about ES, other drivers seem to expose it. Not sure about ES1.
src/mesa/main/extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/extensio
1 - 100 of 120 matches
Mail list logo
