Re: [Mesa-dev] [PATCH 1/4] tgsi/lowering: add support for lowering FLR and CEIL

2016-04-14 0:42 GMT+02:00 Rob Clark : > From: Russell King > > Add support for lowering FLR and CEIL to FRC/SUB and FRC/ADD > instructions for GPUs that support FRC but not FLR or CEIL. Since > these uses FRC, it is invalid to ask for FLR or CEIL to be lowered > along with FRC, so add an assert t

Re: [Mesa-dev] [PATCH 1/2] tgsi/lowering: add support to lower FLR

Hi Rob 2016-04-14 0:23 GMT+02:00 Rob Clark : > I'll dig up Russell's patchset and resend it.. I kind of forgot about > it until I saw these patches and didn't realize it didn't end up on > mesa-dev. Anyways, his patchset looked good to me, so it has my r-b > already. Great! > > Christian, if y

Re: [Mesa-dev] [PATCH v2 01/20] radeonsi: lower compute shader arguments

Patches - 2-4, 7-8, 12-14 & 17 - are all: Reviewed-by: Edward O'Callaghan The series was: Tested-by: Edward O'Callaghan On 2016-04-14 05:29, Bas Nieuwenhuizen wrote: Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/

Re: [Mesa-dev] [PATCH] clover: Fix build against LLVM SVN >= r266163

On 14.04.2016 03:59, Francisco Jerez wrote: > Michel Dänzer writes: > >> From: Michel Dänzer >> >> createInternalizePass now takes a callback instead of a StringSet. >> >> Signed-off-by: Michel Dänzer >> --- >> src/gallium/state_trackers/clover/llvm/invocation.cpp | 17 + >> 1

Re: [Mesa-dev] Mesa (master): 29 new commits

On 12.04.2016 21:33, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote: > > URL: > http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a4b74d1ba2c156766a7a5dbfef099c7db5d6694 > Author: Marek Olšák > Date: Mon Apr 11 19:56:07 2016 +0200 > > gallium/radeon: relax requirements on VRAM placements on AP

Re: [Mesa-dev] [PATCH 1/2] radeonsi: fix NUM_SGPRS calculation once more

On 13.04.2016 21:36, Marek Olšák wrote: > On Wed, Apr 13, 2016 at 2:19 PM, Marek Olšák wrote: >> From: Marek Olšák >> >> This fixes GS piglit failures after adding SI_PARAM_SHADER_BUFFERS, >> which bumped NUM_USER_SGPRS and uncovered this bug on SI. >> >> If this was fixed in LLVM, these workarou

[Mesa-dev] [PATCH v3] docs: expand "all drivers" to the list of drivers.

At some place, "all drivers" wasn't useful anymore, the "all DONE" list already had all the currently supported drivers. Also, the syntax "all drivers" isn't future proof, if a new drivers comes up (we never know) it will be considered done although by default it might not be. Finally, expanding

[Mesa-dev] [PATCH 03/13] winsys/amdgpu: add support for const IB

From: Marek Olšák v2: use the correct IB to update request (Bas Nieuwenhuizen) --- src/gallium/drivers/radeon/radeon_winsys.h | 18 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 48 +++--- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 9 +- 3 files changed,

[Mesa-dev] [PATCH 11/13] radeonsi: Use CE for vertex buffers.

Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 28 --- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 46d00b4..5e26760

[Mesa-dev] [PATCH 12/13] gallium/util: Add u_bit_scan_consecutive_range64.

For use by radeonsi. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/auxiliary/util/u_math.h | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/auxiliary/util/u_math.h b/src/gallium/auxiliary/util/u_math.h index b4ac0db..3a468e4 100644 --- a/src/gallium/auxiliary/util/u_ma

[Mesa-dev] [PATCH 08/13] radeonsi: Add CE synchronization.

Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_pipe.h | 2 ++ src/gallium/drivers/radeonsi/si_state_draw.c | 24 2 files changed, 26 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h i

[Mesa-dev] [PATCH 06/13] radeonsi: Add dirty_mask to descriptor list.

We can then upload only the dirty ones with the constant engine. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++ src/gallium/drivers/radeonsi/si_state.h | 1 + 2 files changed, 24 insertions(+) diff --git a/src/gallium/driv

[Mesa-dev] [PATCH 13/13] radeonsi: Use CE for all descriptors.

Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 46 +-- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 5e26760..5ddb16

[Mesa-dev] [PATCH 09/13] radeonsi: Allocate chunks of CE ram.

Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 29 ++- src/gallium/drivers/radeonsi/si_pipe.h| 1 - src/gallium/drivers/radeonsi/si_state.h | 3 +++ 3 files changed, 23 insertions(+), 10 deletions(-) diff --git a/src/g

[Mesa-dev] [PATCH 02/13] winsys/amdgpu: split IB data into a new structure in preparation for CE

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 6 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 68 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 16 4 files changed, 48 insertions(+)

[Mesa-dev] [PATCH 07/13] radeonsi: Add CE packet definitions.

Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/sid.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h index f0aa605..1072e0a 100644 --- a/src/gallium/drivers/radeonsi/sid.h +++ b/src/gallium/drive

[Mesa-dev] [PATCH 10/13] radeonsi: Add CE uploader.

Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++ src/gallium/drivers/radeonsi/si_pipe.c| 11 +++ src/gallium/drivers/radeonsi/si_pipe.h| 3 +++ 3 files changed, 37 insertions(+) diff --git a/src/gallium/driv

[Mesa-dev] [PATCH 04/13] winsys/amdgpu: Enlarge const IB size.

Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 19 --- 1

[Mesa-dev] [PATCH 05/13] radeonsi: Create CE IB.

Based on work by Marek Olšák. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeon/r600_pipe_common.c | 1 + src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeonsi/si_hw_context.c | 4 +++- src/gallium/drivers/radeonsi/si_pipe.c| 7 +++ src/gall

[Mesa-dev] [PATCH 01/13] gallium/radeon: move ring_type into winsyses

From: Marek Olšák Not used by drivers. --- src/gallium/drivers/radeon/radeon_winsys.h| 1 - src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 8 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 1 + src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 10 +- src/gallium/winsys/ra

[Mesa-dev] [PATCH 00/13] Use the constant engine in radeonsi

This series implements updating descriptors using the constant engine. This should result in a 0%-3% improvement for CPU bound applications, as we only have to upload the change descriptors from the CPU. There are very slight performance advantages on the GPU too, as the CE uploads the data direct

Re: [Mesa-dev] Rework uniform storage

On 04/13/2016 03:23 PM, Jakob Sinclair wrote: > Hi! This idea was first suggested by Tim Arceri and it's about how mesa > handles uniform storage. > > If you look at the struct gl_uniform_storage you will notice that we > have two variables here that stores the data: > > unsigned num_driver_s

Re: [Mesa-dev] [PATCH 01/47] nir: rewrite nir_foreach_block and friends

On Wed, Apr 13, 2016 at 2:06 PM, Connor Abbott wrote: > On Wed, Apr 13, 2016 at 3:20 PM, Jason Ekstrand > wrote: > > > > > > On Wed, Apr 13, 2016 at 12:15 PM, Connor Abbott > wrote: > >> > >> On Wed, Apr 13, 2016 at 2:49 PM, Jason Ekstrand > >> wrote: > >> > > >> > > >> > On Wed, Apr 13, 2016

Re: [Mesa-dev] [PATCH] nvc0: allow to use compute support on GM200

Reviewed-by: Ilia Mirkin On Wed, Apr 13, 2016 at 6:46 PM, Samuel Pitoiset wrote: > This works like a charm but please not that NVF0_COMPUTE have to be set > because compute support is still not enabled by default on GK110+. This > will require more testing to make sure it won't break the 3D stat

[Mesa-dev] [PATCH] nvc0: allow to use compute support on GM200

This works like a charm but please not that NVF0_COMPUTE have to be set because compute support is still not enabled by default on GK110+. This will require more testing to make sure it won't break the 3D state. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv_object.xml.h |

Re: [Mesa-dev] [PATCH] glsl: Properly handle ldexp(0.0f, non-zero-exp).

On Wed, Apr 13, 2016 at 12:07 PM, Matt Turner wrote: > --- i965 is going to stop using this code, but I thought it'd be nice to fix this and also to note what is the remaining failure on the dEQP ldexp tests. The GLSL spec says "If this product is too large to be represented in the floating-poin

Re: [Mesa-dev] [PATCH 1/3] glsl: removing double semi-colons

It looks like there are a couple other instances dangling around the tree. src/glx/dri2_glx.c, src/mesa/math/m_debug_norm.c, etc. I did 'grep -r ';[[:space:]]*;' src/'. Most of the hits were for-loops. On 04/13/2016 09:43 AM, Jakob Sinclair wrote: > Trivial change. Removing unnecessary semi-colo

[Mesa-dev] [PATCH 1/4] tgsi/lowering: add support for lowering FLR and CEIL

From: Russell King Add support for lowering FLR and CEIL to FRC/SUB and FRC/ADD instructions for GPUs that support FRC but not FLR or CEIL. Since these uses FRC, it is invalid to ask for FLR or CEIL to be lowered along with FRC, so add an assert to catch this invalid configuration. We also need

[Mesa-dev] [PATCH 4/4] tgsi/lowering: improved lowering for LRP

From: Russell King Provide an improved lowering for LRP, which can be implemented in two MAD instructions with a bit of rearranging of the equation, rather than the literal implementation of two multiplies, an add and a subtract. Signed-off-by: Russell King Reviewed-by: Rob Clark --- src/gall

[Mesa-dev] [PATCH 2/4] tgsi/lowering: add support for lowering TRUNC

From: Russell King Add support for lowering TRUNC using the following sequence: FRC tmpA, |src| SUB tmpA, |src|, tmpA CMP dst, -tmpA, tmpA Note that this is incompatible with FRC lowering. Signed-off-by: Russell King Reviewed-by: Rob Clark --- src/gallium/auxiliary/t

[Mesa-dev] [PATCH 3/4] tgsi/lowering: improved lowering for XPD

From: Russell King Improve XPD lowering to consume less instructions by using the MAD instruction to perform the multiply and subtraction together. Signed-off-by: Russell King Reviewed-by: Rob Clark --- src/gallium/auxiliary/tgsi/tgsi_lowering.c | 35 +++--- 1 file cha

Re: [Mesa-dev] [PATCH 1/2] tgsi/lowering: add support to lower FLR

I'll dig up Russell's patchset and resend it.. I kind of forgot about it until I saw these patches and didn't realize it didn't end up on mesa-dev. Anyways, his patchset looked good to me, so it has my r-b already. Christian, if you don't already, I'd recommend running piglit.. I think it should

[Mesa-dev] Rework uniform storage

Hi! This idea was first suggested by Tim Arceri and it's about how mesa handles uniform storage. If you look at the struct gl_uniform_storage you will notice that we have two variables here that stores the data: unsigned num_driver_storage; struct gl_uniform_driver_storage *driver_storag

Re: [Mesa-dev] [PATCH 2/2] tgsi/lowering: add support to lower CEIL

Am 13.04.2016 um 22:51 schrieb Christian Gmeiner: > Signed-off-by: Christian Gmeiner > --- > src/gallium/auxiliary/tgsi/tgsi_lowering.c | 54 > ++ > src/gallium/auxiliary/tgsi/tgsi_lowering.h | 1 + > 2 files changed, 55 insertions(+) > > diff --git a/src/gallium/au

Re: [Mesa-dev] [PATCH 01/47] nir: rewrite nir_foreach_block and friends

Quoting Connor Abbott [sni] > > Well, I could make the change, but at this point it would be a bit > more involved. I'd have to figure out how to get the list of files > changed with each commit and then run a sed job on only them > (otherwise I'd re-swap the arguments for everything else), and th

Re: [Mesa-dev] ARB_framebuffer_no_attachments for llvm and soft pipes

On 14 April 2016 at 01:37, Roland Scheidegger wrote: > Am 13.04.2016 um 03:35 schrieb eocallag...@alterapraxis.com: >> On 2016-04-11 22:27, Roland Scheidegger wrote: >>> Am 10.04.2016 um 09:41 schrieb Edward O'Callaghan: All the piglits pass for these two as-is. However, some of the piglits >

Re: [Mesa-dev] [PATCH 1/2] tgsi/lowering: add support to lower FLR

On Wed, Apr 13, 2016 at 05:03:42PM -0400, Rob Clark wrote: > On Wed, Apr 13, 2016 at 4:50 PM, Christian Gmeiner > wrote: > > Signed-off-by: Christian Gmeiner > > btw, Russell sent me a patchset a while back which included FLR/CEIL > and some others.. and also properly fixed up LIT in case of low

[Mesa-dev] [PATCH 1/2] i965/fs: Use UD type for offsets in VARYING_PULL_CONSTANT_LOAD

Reveiewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 954f782..944ad

[Mesa-dev] [PATCH 2/2] i965/vec4: Use UD rather than D for uniform indirects

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 2 +- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index e4e8c38..4516c9a

Re: [Mesa-dev] [PATCH 01/47] nir: rewrite nir_foreach_block and friends

On Wed, Apr 13, 2016 at 3:20 PM, Jason Ekstrand wrote: > > > On Wed, Apr 13, 2016 at 12:15 PM, Connor Abbott wrote: >> >> On Wed, Apr 13, 2016 at 2:49 PM, Jason Ekstrand >> wrote: >> > >> > >> > On Wed, Apr 13, 2016 at 8:15 AM, Jason Ekstrand >> > wrote: >> >> >> >> >> >> On Apr 13, 2016 4:57 A

Re: [Mesa-dev] [PATCH 1/3] glsl: removing double semi-colons

This series is, Reviewed-by: Edward O'Callaghan On 2016-04-14 02:43, Jakob Sinclair wrote: Trivial change. Removing unnecessary semi-colons from the code. I don't have push access so someone reviewing this can push it. Signed-off-by: Jakob Sinclair --- src/compiler/glsl/ast_function.cpp

Re: [Mesa-dev] [PATCH 1/2] tgsi/lowering: add support to lower FLR

On Wed, Apr 13, 2016 at 4:50 PM, Christian Gmeiner wrote: > Signed-off-by: Christian Gmeiner btw, Russell sent me a patchset a while back which included FLR/CEIL and some others.. and also properly fixed up LIT in case of lowering FLR.. so I think his patchset was more complete. Perhaps he coul

Re: [Mesa-dev] Fwd: New Defects reported by Coverity Scan for Mesa

There are four different places where the program pointer may jump to 'cleanup:' while the mutex is still possilby being locked. Two of those cases are when mtx_lock(pthread_mutex_lock) fails to lock the mutex. However, this can't be a problem because the mutex is either not in "locked" state be

[Mesa-dev] [PATCH v2] xlib: do not cache return value of glXChooseVisual/glXGetVisualFromFBConfig

The returned XVisualInfo from glXChooseVisual/glXGetVisualFromFBConfig is being cached in XMesaVisual.vishandle (and unconditionally overwritten on subsequent calls). However, these entry points are specified to return XVisualInfo instances to be owned by the caller and freed with XFree(), so the

[Mesa-dev] [Bug 94086] Multiple conflicting libGL libraries installed

https://bugs.freedesktop.org/show_bug.cgi?id=94086 --- Comment #3 from Emil Velikov --- If you ignore the presence of dri powered libGL (one in src/glx) there're two libGL implementations - one 'classic' (src/mesa/foo) and one gallium (src/gallium/foo). OSMesa is, was actually, in a similar boat

[Mesa-dev] [PATCH 2/2] tgsi/lowering: add support to lower CEIL

Signed-off-by: Christian Gmeiner --- src/gallium/auxiliary/tgsi/tgsi_lowering.c | 54 ++ src/gallium/auxiliary/tgsi/tgsi_lowering.h | 1 + 2 files changed, 55 insertions(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_lowering.c b/src/gallium/auxiliary/tgsi/tgsi_low

[Mesa-dev] [PATCH 1/2] tgsi/lowering: add support to lower FLR

Signed-off-by: Christian Gmeiner --- src/gallium/auxiliary/tgsi/tgsi_lowering.c | 54 ++ src/gallium/auxiliary/tgsi/tgsi_lowering.h | 1 + 2 files changed, 55 insertions(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_lowering.c b/src/gallium/auxiliary/tgsi/tgsi_low

Re: [Mesa-dev] [RFC 24/24] nvc0: expose GLSL version 420 on GK104

Reviewed-by: Ilia Mirkin Maybe even make it 440 while you're at it? No harm done, we have all the features. It'll get clamped down by mesa core for now having this or that extension. On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > Other chipsets will be added later. > > Signed-off-by:

Re: [Mesa-dev] [RFC 23/24] nvc0: enable ARB_shader_image_load_store on GK104

On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > From: Ilia Mirkin That doesn't need to come from me... make yourself the author. > > This exposes 8 images for all shader types. > > Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin > --- > src/gallium/drivers/nouveau/nvc0/nv

Re: [Mesa-dev] [RFC 20/24] nvc0/ir: prevent out of bounds when no images are bound

On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > Checking if the image address is not 0 should be enough to prevent > read faults. To improve robustness, make sure that the destination > value of atomic operations is correctly initialized in case the > instruction is not performed. > > Si

Re: [Mesa-dev] [RFC 21/24] nvc0: reduce GL_MAX_3D_TEXTURE_SIZE to 2048 on Kepler+

Reviewed-by: Ilia Mirkin Cc: "11.1 11.2" On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > The blob sets it to 2048 and using 4096 reports an INVALID_DATA error > with RT_ARRAY_MODE when z is 4096. Suggested by Ilia Mirkin. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/driver

Re: [Mesa-dev] [RFC 22/24] nvc0: inform users that 3D images are not fully supported

I would recommend using a pipe_debug_message here as well. Either way, Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > 3D images are a bit more complicated to implement and will probably > requires a bunch of headaches and we don't care for now because they >

Re: [Mesa-dev] [RFC 19/24] nvc0/ir: add indirect support for images on Kepler

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > This fixes arb_shader_image_load_store-indexing and > arb_shader_image_load_store-max-images. > > Signed-off-by: Samuel Pitoiset > --- > .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 42 > +++

Re: [Mesa-dev] [RFC 18/24] nvc0/ir: fix 1D arrays images for Kepler

On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > For 1D arrays, the array index is stored in the Z component. > > Signed-off-by: Samuel Pitoiset > --- > .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 17 > + > 1 file changed, 13 insertions(+), 4 deletions(-)

Re: [Mesa-dev] [RFC 17/24] nvc0/ir: fix cube images for Kepler

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > Like 2d array images, the z-dimension needs to be clamped. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 +- > 1 file changed, 5 insertions

Re: [Mesa-dev] [RFC 15/24] nv50/ir: make use of OP_SUQ for surfaces query

On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > This implements RESQ for surfaces which comes from imageSize() GLSL > bultin. As the dimensions are sticked into the driver constant buffer, > this only has to be lowered with loads. > > Signed-off-by: Samuel Pitoiset > --- > .../drivers/

Re: [Mesa-dev] [RFC 14/24] nv50/ir: add OP_BUFQ for buffers query

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > TGSI RESQ allows both images and buffers but we have to make a > distinction between these two type of resources in our lowering pass. > Introducing OP_BUFQ which is a fake operand will allow to implement > OP_SUQ

Re: [Mesa-dev] [RFC 13/24] nv50/ir: enable early fragment test with explicit user control

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > This feature can be enabled in two ways: as an optimization and by > explicit user control (with OpenGL 4.2 or ARB_shader_image_load_store). > > This makes use of the recent TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL to

Re: [Mesa-dev] [RFC 12/24] nvc0/ir: fix constraints for OP_SUSTx on Kepler

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > Destination type is actually always 32-bits, so typeSizeof() returns 4 > and no sources are condensed. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 4 +++- > 1

Re: [Mesa-dev] [RFC 11/24] nv50/ir: re-introduce TGSI lowering pass for images

The .raw stuff is never true. I'd just kill it off for now. On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > This is loosely based on the previous lowering pass wrote by calim > four years ago. I did clean the code and fixed some issues. > > Signed-off-by: Samuel Pitoiset > --- > .../d

Re: [Mesa-dev] [RFC 10/24] nv50/ir: add support for TGSI image declarations

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: > Old and dead resource code will be removed once images are completely > done. Based on original patch by Ilia Mirkin. > > Signed-off-by: Samuel Pitoiset > --- > .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp

Re: [Mesa-dev] [RFC 09/24] nvc0: add missing glMemoryBarrier bits

Reviewed-by: Ilia Mirkin If you wanted to play around with it to figure out which bit was which, I wouldn't object. I think someone pushed (or has sent) a more complete mem barrier test. Although such guessing can't be conclusive, so perhaps might as well just leave it like this... Oh, but one t

Re: [Mesa-dev] [RFC 08/24] nvc0: enable RGB10_A2UI format on GK104

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: > No clue why this was not enabled by default before, maybe because > the SULDP conversion was wrong. Anyway, this helps in fixing all > rgb10_a2ui piglit tests. > > Signed-off-by: Samuel Pitoiset > --- > src/gall

Re: [Mesa-dev] [RFC 07/24] nvc0: shift address with blocksize for image buffers

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: > This fixes a bunch of dEQP image buffers related tests. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/src/gal

Re: [Mesa-dev] [RFC 05/24] nvc0: compute correct image dimensions based on the target

On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: > Loosely based on softpipe but with some changes, this computes correct > width, height and depth of different targets to help in processing > coordinates from the codegen part. > > This fixes a ton of dEQP/piglit tests. > > Signed-off-by: S

Re: [Mesa-dev] [RFC 06/24] nvc0: fix address offset when images have multiple levels

Reviewed-by: Ilia Mirkin On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: > This fixes arb_shader_image_load_store-level. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/gallium/drivers/n

[Mesa-dev] [Bug 94086] Multiple conflicting libGL libraries installed

https://bugs.freedesktop.org/show_bug.cgi?id=94086 --- Comment #2 from Chuck Atkins --- > Fwiw I'd rather have a configure error, if one tries to build conflicting > (at install time) files. The glx options are implemented differently than the osmesa ones, even though they try to accomplish the

Re: [Mesa-dev] [RFC 04/24] nvc0: bind images on 3D shaders for Kepler

On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: > Similar to surfaces validation for compute shaders. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++- > src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 26 > -

Re: [Mesa-dev] [RFC 03/24] nvc0: bind images on compute shaders for Kepler

On Wed, Apr 13, 2016 at 11:26 AM, Samuel Pitoiset wrote: > > > On 04/13/2016 03:38 AM, Ilia Mirkin wrote: >> >> On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset >> wrote: >>> >>> Old surfaces validation code will be removed once images are completely >>> done for Fermi/Kepler, that explains why I

Re: [Mesa-dev] [PATCH v2] gallium/swr: fold the almost identical Makefiles

> On Apr 13, 2016, at 2:21 PM, Emil Velikov wrote: > > On 13 April 2016 at 19:13, Rowley, Timothy O > wrote: >> Testing this, I needed to make the following change to >> install-gallium-links.mk to avoid a segfault while building. If that’s the >> right approach, the egl_LTLIBRARIES line pr

[Mesa-dev] [PATCH] install-gallium-links.mk: handle multiple libraries

Need to prevent bash from interpreting whitespace between libraries as a command line. --- install-gallium-links.mk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/install-gallium-links.mk b/install-gallium-links.mk index 4010cad..ac5a499 100644 --- a/install-gallium-link

Re: [Mesa-dev] [PATCH 3/3] nir/algebraic: Add lowering for ldexp

On Wed, Apr 13, 2016 at 12:37 PM, Jason Ekstrand wrote: > The algorithm used is different from both the naieve suggestion from the > GLSL spec and the one used in GLSL IR today. Unfortunately, the GLSL IR > implementation doesn't handle some of the corner cases correctly and Let's change this to

[Mesa-dev] [PATCH 3/3] nir/algebraic: Add lowering for ldexp

The algorithm used is different from both the naieve suggestion from the GLSL spec and the one used in GLSL IR today. Unfortunately, the GLSL IR implementation doesn't handle some of the corner cases correctly and neither does a naieve f * 2.0^exp implementation. Assuming that hardware does the s

[Mesa-dev] [PATCH 1/3] nir: Add more modulus opcodes

These are all needed for SPIR-V Reviewed-by: Rob Clark --- src/compiler/nir/nir_opcodes.py | 16 +++- src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py i

[Mesa-dev] [PATCH 2/3] i965: Implement the new imod and irem opcodes

--- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 36 ++ src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 36 ++ 2 files changed, 72 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp i

[Mesa-dev] [PATCH v2 09/20] radeonsi: don't pass scratch buffer to user SGPRs

As far as I can see we use relocations for clover too. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_compute.c | 8 1 file changed, 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src

[Mesa-dev] [PATCH v2 05/20] radeonsi: set maximum work group size based on block size

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 12 1 file changed, 12 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 72baaac

[Mesa-dev] [PATCH v2 14/20] radeonsi: update predicate condition for compute dispatches

Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_compute.c | 6 ++ src/gallium/drivers/radeonsi/si_pipe.h| 9 + 2 files changed, 15 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 6a4db3a.

[Mesa-dev] [PATCH v2 20/20] radeonsi: enable TGSI support cap for compute shaders

v2: Use chip_class instead of family. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Nicolai Hähnle --- docs/GL3.txt | 4 ++-- docs/relnotes/11.3.0.html | 1 + src/gallium/drivers/radeon/r600_pipe_common.c | 21 - src/gal

[Mesa-dev] [PATCH v2 12/20] radeonsi: only emit compute shader state when switching shaders

v2: - Do check if anything changed earlier - Use emitted_program instead of emitted_bo to prevent shaders with shader->bo = NULL confusing the check - Use radeon_set_sh_reg* Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_compute.c | 145 ++-

[Mesa-dev] [PATCH v2 13/20] radeonsi: implement TGSI compute dispatch

v2: - Use radeon_set_sh_reg_seq. - Set predicate bit for conditional rendering. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_compute.c | 104 ++ 1 file changed, 77 insertions(+), 27 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si

[Mesa-dev] [PATCH v2 11/20] radeonsi: rework compute scratch buffer

Instead of having a scratch buffer per program, have one per context. Also removed the per kernel wave count calculations, but that only helped if the total number of waves in the dispatch was smaller than sctx->scratch_waves. v2: Fix style issue. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: M

[Mesa-dev] [PATCH v2 19/20] mesa/st: enable compute shaders if images are also supported

v2: Also depend on atomic counters. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Nicolai Hähnle --- src/mesa/state_tracker/st_extensions.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c

[Mesa-dev] [PATCH v2 18/20] radeonsi: clean up compute flush

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_pipe.h | 3 --- src/gallium/drivers/radeonsi/si_state_draw.c | 27 ++- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/src/ga

[Mesa-dev] [PATCH v2 08/20] radeonsi: split input upload off from si_launch_grid

Also uses a dynamically allocated buffer using u_upload_alloc. The old buffer per program approach required serializing all dispatches of the same program. v2: - Clarified commit message. - Use radeon_set_sh_reg_seq. - Also upload input buffer for clover kernels, even when input_size

[Mesa-dev] [PATCH v2 04/20] radeonsi: implement shared atomics

v2: - Use single region - Use get_memory_ptr Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_shader.c | 77 +++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/rade

[Mesa-dev] [PATCH v2 03/20] radeonsi: implement shared memory load/store

v2: - Use single region - Combine address calculation Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_shader.c | 84 +++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/dr

[Mesa-dev] [PATCH v2 07/20] radeonsi: implement TGSI compute shader creation

v2: Moved scratch_enabled initialization after compile. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_compute.c | 74 +++ 1 file changed, 56 insertions(+), 18 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/dr

[Mesa-dev] [PATCH v2 17/20] radeonsi: do not do two full flushes on every compute dispatch

v2: Add more CS_PARTIAL_FLUSH events. Essentially every place with waits on finishing for pixel shaders also has a write after read hazard with compute shaders. Invalidating L2 waits implicitly on pixel and compute shaders, so, we don't need a CS_PARTIAL_FLUSH for switching FBO. Signed-off-by: B

[Mesa-dev] [PATCH v2 10/20] radeonsi: do per cs setup for compute shaders once per cs

Also removes PKT3_CONTEXT_CONTROL as that is already being done by si_begin_new_cs, when emitting init_config. v2: - Use radeon_set_sh_reg_seq. - Also set COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 for CIK+ Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/rade

[Mesa-dev] [PATCH v2 06/20] radeonsi: update shader count for compute shaders

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 6748f8

[Mesa-dev] [PATCH v2 15/20] radeonsi: split texture decompression for compute shaders

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_blit.c | 13 +++-- src/gallium/drivers/radeonsi/si_compute.c| 2 ++ src/gallium/drivers/radeonsi/si_pipe.h | 3 ++- src/gallium/drivers/radeonsi/si

[Mesa-dev] [PATCH v2 16/20] radeonsi: split setting graphics and compute descriptors

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_compute.c | 3 ++ src/gallium/drivers/radeonsi/si_descriptors.c | 61 ++- src/gallium/drivers/radeonsi/si_state.h | 7 ++- src/gallium/dr

[Mesa-dev] [PATCH v2 01/20] radeonsi: lower compute shader arguments

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 41 src/gallium/drivers/radeonsi/si_shader.h | 7 ++ 2 files changed, 48 insertions(+) diff --git a/src/gallium/drivers/rad

[Mesa-dev] [PATCH v2 02/20] radeonsi: add shared memory

Declares the shared memory as a global variable so that LLVM is aware of it and it does not conflict with passes like AMDGPUPromoteAlloca. v2: - Use ctx->i8. - Dropped null-check for declare_memory_region. - Changed memory region array to single region. Signed-off-by: Bas Nieuwenhuizen -

Re: [Mesa-dev] [PATCH v2] gallium/swr: fold the almost identical Makefiles

On 13 April 2016 at 19:13, Rowley, Timothy O wrote: > Testing this, I needed to make the following change to > install-gallium-links.mk to avoid a segfault while building. If that’s the > right approach, the egl_LTLIBRARIES line probably needs the same treatment > for future proofing. > > diff

Re: [Mesa-dev] [PATCH 01/47] nir: rewrite nir_foreach_block and friends

On Wed, Apr 13, 2016 at 12:15 PM, Connor Abbott wrote: > On Wed, Apr 13, 2016 at 2:49 PM, Jason Ekstrand > wrote: > > > > > > On Wed, Apr 13, 2016 at 8:15 AM, Jason Ekstrand > > wrote: > >> > >> > >> On Apr 13, 2016 4:57 AM, "Rob Clark" wrote: > >> > > >> > On Wed, Apr 13, 2016 at 12:34 AM, Co

Re: [Mesa-dev] [PATCH 4/4] appveyor: Run unit tests.

Am 13.04.2016 um 21:04 schrieb Jose Fonseca: > --- > appveyor.yml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/appveyor.yml b/appveyor.yml > index bf7ac75..2e9b9d6 100644 > --- a/appveyor.yml > +++ b/appveyor.yml > @@ -65,6 +65,9 @@ install: > build_script: > - scons -j%NUMBER_OF

Re: [Mesa-dev] [PATCH 3/5] nir: Avoid structure initalization expressions.

On Wed, Apr 13, 2016 at 11:53 AM, Jose Fonseca wrote: > On 13/04/16 19:35, Jason Ekstrand wrote: > >> >> >> On Wed, Apr 13, 2016 at 10:19 AM, Emil Velikov > > wrote: >> >> From: Jose Fonseca mailto:jfons...@vmware.com>> >> >> Not supported by MSVC, and com

Re: [Mesa-dev] [PATCH 01/47] nir: rewrite nir_foreach_block and friends

On Wed, Apr 13, 2016 at 2:49 PM, Jason Ekstrand wrote: > > > On Wed, Apr 13, 2016 at 8:15 AM, Jason Ekstrand > wrote: >> >> >> On Apr 13, 2016 4:57 AM, "Rob Clark" wrote: >> > >> > On Wed, Apr 13, 2016 at 12:34 AM, Connor Abbott >> > wrote: >> > > Previously, these were functions which took a c

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