Re: [Mesa-dev] [PATCH 03/18] nir: add new intrinsic field for storing component offset

On Saturday, June 11, 2016 9:03:23 AM PDT Timothy Arceri wrote: > This offset is used for packing. > --- > src/compiler/nir/nir.h| 6 ++ > src/compiler/nir/nir_intrinsics.h | 8 > src/compiler/nir/nir_lower_io.c | 8 > src/compiler/nir/nir_print.c | 3 +++

Re: [Mesa-dev] [PATCH 1/4] i965: Fix issues with number of VS URB entries on Cherryview/Broxton.

Series Reviewed-by: Jordan Justen On 2016-06-10 14:19:43, Kenneth Graunke wrote: > Cherryview/Broxton annoyingly have a minimum number of VS URB entries > of 34, which is not a multiple of 8. When the VS size is less than 9, > the number of VS entries has to be a

Re: [Mesa-dev] [PATCH 2/4] i965: Fix multiplication of immediates on Cherryview/Broxton.

On 2016-06-10 14:19:44, Kenneth Graunke wrote: > Cherryview and Broxton don't support DW x DW multiplication. We have > piles of code to handle this, but apparently weren't retyping in the > immediate case. > > For example, > tests/spec/arb_tessellation_shader/execution/dvec3-vs-tcs-tes > makes

Re: [Mesa-dev] [PATCH] i965/fs: Fix regs_written for SIMD-lowered instructions some more.

Reviewed-by: Jordan Justen On 2016-06-10 22:39:23, Francisco Jerez wrote: > ISTR having suggested this during review of the recent FP64 changes to > the SIMD lowering pass, but it doesn't look like it was taken into > account in the end. Using the

Re: [Mesa-dev] [PATCH 8/8] i965: Use the correct number of threads for compute shaders.

Series Reviewed-by: Jordan Justen On 2016-06-10 13:05:20, Kenneth Graunke wrote: > We were programming the number of threads per subslice, when we should > have been programming the total number of threads on the GPU as a whole. > > Thanks to Curro and Jordan for

[Mesa-dev] [PATCH 2/3] i965: Keep track of the per-thread scratch allocation in brw_stage_state.

This will be used to find out what per-thread slot size a previously allocated scratch BO was used with in order to fix a hardware race condition without introducing additional stalls or memory allocations. Instead of calling brw_get_scratch_bo() manually from the various codegen functions, call a

[Mesa-dev] [PATCH 1/3] i965: Fix scratch overallocation if the original slot size was already a power of two.

The bitwise arithmetic trick used in brw_get_scratch_size() to clamp the scratch allocation to 1KB has the unintended side effect that it will cause us to allocate 2x the required amount of scratch space if the original per-thread scratch size happened to be already a power of two. Instead use

[Mesa-dev] [PATCH 3/3] i965: Fix cross-primitive scratch corruption when changing the per-thread allocation.

I haven't found any mention of this in the hardware docs, but experimentally what seems to be going on is that when the per-thread scratch slot size is changed between two pipelined draw calls, shader invocations using the old and new scratch size setting may end up being executed in parallel,

Re: [Mesa-dev] [PATCH 4/8] i965: Account for poor address calculations in Haswell CS scratch size.

On 2016-06-10 13:05:16, Kenneth Graunke wrote: > Curro figured this out by investigating the simulator. Apparently > there's also a workaround in the Windows driver. I'm not sure it's > actually documented anywhere. > > We were underallocating the scratch buffer by a factor of 128/70. > > Cc:

Re: [Mesa-dev] [PATCH] i965/compiler: Bring back the INTEL_PRECISE_TRIG environment variable

On Saturday, June 11, 2016 1:22:00 PM PDT Jason Ekstrand wrote: > This was removed in d9546b0c5d and replced with the precise_trig driconf > option. However, we still need precise trig in the Vulkan driver so this > commit brings back the environment variable and compiler->precise_trig is >

[Mesa-dev] [PATCH] i965/compiler: Bring back the INTEL_PRECISE_TRIG environment variable

This was removed in d9546b0c5d and replced with the precise_trig driconf option. However, we still need precise trig in the Vulkan driver so this commit brings back the environment variable and compiler->precise_trig is effectively the logical OR of the two. Bugzilla:

Re: [Mesa-dev] [Mesa-stable] [PATCH 7/8] i965: Assert that the scratch spaces are in range.

Kenneth Graunke writes: > I don't know that anything actually guarantees this, but if we exceed > the limits, we may end up overflowing and trashing random buffers that > happen to be nearby in the VMA space, leading to rendering corruption, > hangs, or worse. > > We

[Mesa-dev] [RFC 3/3] u_vbuf: use single vertex buffer if needed

From: "Wladimir J. van der Laan" CONST, VERTEX and INSTANCE attributes into one vertex buffer if necessary due to hardware constraints. Signed-off-by: Wladimir J. van der Laan --- src/gallium/auxiliary/util/u_vbuf.c | 28 1 file

[Mesa-dev] [RFC 2/3] u_vbuf: add logic to use a limited number of vbufs

From: "Wladimir J. van der Laan" Make it possible to limit the number of vertex buffers as there exist GPUs with less then 32 supported vertex buffers. Signed-off-by: Wladimir J. van der Laan --- src/gallium/auxiliary/util/u_vbuf.c | 45

[Mesa-dev] [RFC 1/3] gallium: add PIPE_CAP_MAX_VERTEX_BUFFERS

Signed-off-by: Christian Gmeiner --- src/gallium/docs/source/screen.rst | 1 + src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++ src/gallium/drivers/i915/i915_screen.c | 2 ++ src/gallium/drivers/ilo/ilo_screen.c | 2 ++

[Mesa-dev] [RFC 0/3] Support GPUs with less then 32 vertex buffers

To be able to upstream etnaviv mesa driver it is needed to get all gallium changes reviewed (and upstreamed) first. And I will start with the vertex buffer topic. The current u_vbuf source assumes that every GPU supports 32 vertext buffers. Vivante GPUs do support a different number of vertext

[Mesa-dev] [PATCH] gallium: add API for setting window rectangles

Window rectangles apply to all framebuffer operations, either in inclusive or exclusive mode. They may also be specified as part of a blit operation. In exclusive mode, any fragment inside any of the specified rectangles will be discarded. In inclusive mode, any fragment outside every rectangle

Re: [Mesa-dev] [PATCH] llvmpipe: don't use 3-component formats, except 32-bit x 3 formats

On 10/06/16 22:02, Roland Scheidegger wrote: Am 10.06.2016 um 20:58 schrieb Brian Paul: This basically disallows all 8-bit x 3 and 16-bit x 3 formats for textures and render targets. Some 3-component formats were already disallowed before. This avoids problems with GL_ARB_copy_image. v2: the

Re: [Mesa-dev] [PATCH v2 2/2] gallivm: Fix trivial sign warnings

On 10/06/16 04:01, Jan Vesely wrote: From: Jan Vesely v2: include whitespace fixes Signed-off-by: Jan Vesely --- src/gallium/auxiliary/gallivm/lp_bld_conv.c | 4 ++-- src/gallium/auxiliary/gallivm/lp_bld_logic.c| 10 ++

Re: [Mesa-dev] [PATCH] llvmpipe: hack-fix bugs due to bogus bind flags

On 11/06/16 00:19, srol...@vmware.com wrote: From: Roland Scheidegger The gallium contract would be that bind flags must indicate all possible bindings a resource might get used, but fact is the mesa state tracker does not set bind flags correctly, and this is more or less

Re: [Mesa-dev] [PATCH 00/64] i965: Start using ISL for filling out surface states

For those of you who like branches. The whole series can be found here: https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/i965-isl-v1 On Sat, Jun 11, 2016 at 9:02 AM, Jason Ekstrand wrote: > We would like to eventually start using ISL inside of the GL driver to

[Mesa-dev] [PATCH 24/64] isl/state: Emit no-op mip tail setup on SKL

This hasn't ever been a problem in the past but it is recommended by the hardware docs. --- src/intel/isl/isl_surface_state.c | 8 1 file changed, 8 insertions(+) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 0d26619..fe0402f 100644 ---

[Mesa-dev] [PATCH 64/64] i965/context: Remove some unnecessary vfuncs

--- src/mesa/drivers/dri/i965/brw_context.h | 17 - src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +-- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 1 - src/mesa/drivers/dri/i965/gen8_surface_state.c| 1 - 4 files changed, 1 insertion(+), 21

[Mesa-dev] [PATCH 48/64] i965/blorp: Use the generic ISL path for texture surfaces on gen6

--- src/mesa/drivers/dri/i965/gen6_blorp.c | 77 +- 1 file changed, 2 insertions(+), 75 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c index 3af9c95..4620da2 100644 ---

[Mesa-dev] [PATCH 56/64] i965/gen7: Use the generic ISL-based path for texture surfaces

--- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 169 +- 1 file changed, 1 insertion(+), 168 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 2a7ae31..bdb4f66 100644 ---

[Mesa-dev] [PATCH 53/64] i965/state: Add generic surface update functions based on ISL

--- src/mesa/drivers/dri/i965/brw_state.h| 9 ++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 184 +++ 2 files changed, 193 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index ba441cd..1667ee0

[Mesa-dev] [PATCH 27/64] isl/state: Add assertions for buffer surface restrictions

--- src/intel/isl/isl_surface_state.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 8f223d1..ca13175 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -416,6

[Mesa-dev] [PATCH 59/64] i965/gen4-6: Use the generic ISL-based path for texture surfaces

--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 94 +--- 1 file changed, 1 insertion(+), 93 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index a9540b4..c310b15 100644 ---

[Mesa-dev] [PATCH 50/64] i965/blorp: Use a generic ISL path for texture surfaces on gen8

--- src/mesa/drivers/dri/i965/gen8_blorp.c | 47 +++--- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c index b5c600b..918f3d6 100644 ---

[Mesa-dev] [PATCH 54/64] i965/gen8: Use the generic ISL-based path for texture surfaces

--- src/mesa/drivers/dri/i965/gen8_surface_state.c | 213 + 1 file changed, 1 insertion(+), 212 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index f4375ea..ed26271 100644 ---

[Mesa-dev] [PATCH 49/64] i965/state: Add a helper for emitting a surface state using isl

--- src/mesa/drivers/dri/i965/brw_state.h| 8 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 81 2 files changed, 89 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index eec4bae..ba441cd

[Mesa-dev] [PATCH 61/64] i965/state: Account for the element size in emit_buffer_surface_state

--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 9 + src/mesa/drivers/dri/i965/gen8_surface_state.c| 9 + 3 files changed, 16 insertions(+), 13 deletions(-) diff --git

[Mesa-dev] [PATCH 58/64] i965/gen6: Use the generic ISL-based path for renderbuffer surfaces

--- src/mesa/drivers/dri/i965/gen6_surface_state.c | 100 + 1 file changed, 1 insertion(+), 99 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c index d892c93..84b8ef4 100644 ---

[Mesa-dev] [PATCH 40/64] i965/miptree: Add a helper for getting an isl_surf from a miptree

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 171 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 + 2 files changed, 175 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 60/64] isl/formats: Mark RAW as having a block size of 1 byte

--- src/intel/isl/isl_format_layout.csv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv index a39093e..7d3c3de 100644 --- a/src/intel/isl/isl_format_layout.csv +++ b/src/intel/isl/isl_format_layout.csv

[Mesa-dev] [PATCH 15/64] isl/state: Return an extent3d from the halign/valign helper

--- src/intel/isl/isl_surface_state.c | 28 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 50570aa..1e94e60 100644 --- a/src/intel/isl/isl_surface_state.c +++

[Mesa-dev] [PATCH 25/64] isl/state: Use TILEWALK_XMAJOR for linear surfaces on gen7

This matches better what happens on gen8 where the "Tiled Surface" and "Tile Walke" bits are combined into a single two-bit value. This is also more consistent with what the GL driver does. --- src/intel/isl/isl_surface_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[Mesa-dev] [PATCH 36/64] isl: Add support for filling out surface states all the way back to gen4

--- src/intel/isl/Makefile.am | 12 src/intel/isl/Makefile.sources| 13 +++-- src/intel/isl/isl.c | 28 +++ src/intel/isl/isl_priv.h | 24 src/intel/isl/isl_surface_state.c | 58

[Mesa-dev] [PATCH 52/64] i965/surface_state: Rename brw_update to gen4_update

We're about to add generic versions which work across gens and those should have the brw name. --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c

[Mesa-dev] [PATCH 46/64] i965/blorp: Use the generic ISL path for texture surfaces on gen7

--- src/mesa/drivers/dri/i965/gen7_blorp.c | 97 ++ 1 file changed, 3 insertions(+), 94 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c index 353a60f..3300adc 100644 ---

[Mesa-dev] [PATCH 63/64] i965: Get rid of gen6_surface_state.c

The only useful thing left was gen6_init_vtable_surface_functions which we can easily put in brw_wm_surface_state.c. --- src/mesa/drivers/dri/i965/Makefile.sources | 1 - src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 src/mesa/drivers/dri/i965/gen6_surface_state.c | 48

[Mesa-dev] [PATCH 38/64] isl/state: Add support for handling color control surfaces

--- src/intel/isl/isl.h | 6 ++ src/intel/isl/isl_surface_state.c | 42 --- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 36038bc..a987482 100644 --- a/src/intel/isl/isl.h +++

[Mesa-dev] [PATCH 43/64] i965/blorp: Add a generic ISL-based surface state emit path

--- src/mesa/drivers/dri/i965/brw_blorp.c | 146 ++ src/mesa/drivers/dri/i965/brw_blorp.h | 6 ++ 2 files changed, 152 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 9590968..1089a49 100644 ---

[Mesa-dev] [PATCH 45/64] i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen7

--- src/mesa/drivers/dri/i965/gen7_blorp.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c index 270fe57..353a60f 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.c +++

[Mesa-dev] [PATCH 57/64] i965/gen7: Use the generic ISL-based path for renderbuffer surfaces

--- src/mesa/drivers/dri/i965/brw_state.h | 7 - src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 194 +- 2 files changed, 1 insertion(+), 200 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index

[Mesa-dev] [PATCH 35/64] isl: Add an ISL_DEV_IS_G4X macro

--- src/intel/isl/isl.h | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index ef86228..3bf7469 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -65,6 +65,10 @@ struct brw_image_param; (assert(ISL_DEV_GEN(__dev) ==

[Mesa-dev] [PATCH 47/64] i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen6

--- src/mesa/drivers/dri/i965/gen6_blorp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c index 5f84ab0..3af9c95 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.c +++

[Mesa-dev] [PATCH 51/64] i965/state: Use ISL for emitting image surfaces

--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 32 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 2888cc9..9270372 100644 ---

[Mesa-dev] [PATCH 16/64] isl/state: Refactor the per-gen isl_to_gen_h/valign tables

This moves the #if's around so that halign and valign have different sets of #if conditions. This also prepares us for SNB because isl_to_gen_halign is not defined at all on gen6. --- src/intel/isl/isl_surface_state.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff

[Mesa-dev] [PATCH 33/64] genxml: Make X/Y Offset field of SURFACE_STATE a uint

THe offset type has special implications that it's intended to be some form of aligned memory address. These assumptions allow it to handle the case where there is some alignment requirement on the offset and the bottom bits are used for other things. However, the offsets in the surface state

[Mesa-dev] [PATCH 20/64] isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels

--- src/intel/isl/isl_format_layout.csv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv index bcfea0f..f90fbe0 100644 --- a/src/intel/isl/isl_format_layout.csv +++ b/src/intel/isl/isl_format_layout.csv

[Mesa-dev] [PATCH 23/64] isl/state: Only set cube face enables if usage includes CUBE_BIT

It seems safe to set it all the time, but this reduces the diff between the way i965 does it and what ISL does. --- src/intel/isl/isl_surface_state.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c

[Mesa-dev] [PATCH 28/64] isl/state: Don't use designated initializers for buffer surface state

--- src/intel/isl/isl_surface_state.c | 46 +++ 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index ca13175..2026f80 100644 --- a/src/intel/isl/isl_surface_state.c +++

[Mesa-dev] [PATCH 21/64] isl/state: Set the IntegerSurfaceFormat bit on Haswell

This fixes 688 Vulkan CTS tests on Haswell. --- src/intel/isl/isl_surface_state.c | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 35902e6..b16bcbf 100644 --- a/src/intel/isl/isl_surface_state.c +++

[Mesa-dev] [PATCH 29/64] isl/state: Allow for full 31-bit buffer texture sizes

Ivy Bridge and above can handle up to 2^31 elements for RAW buffer surfaces. --- src/intel/isl/isl_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 2026f80..4c6563a 100644 ---

[Mesa-dev] [PATCH 62/64] i965: Use ISL for emitting buffer surface states

--- src/mesa/drivers/dri/i965/brw_binding_tables.c| 2 +- src/mesa/drivers/dri/i965/brw_context.h | 8 -- src/mesa/drivers/dri/i965/brw_state.h | 9 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 97 +++

[Mesa-dev] [PATCH 55/64] i965/gen8: Use the generic ISL-based path for renderbuffer surfaces

--- src/mesa/drivers/dri/i965/brw_state.h | 16 -- src/mesa/drivers/dri/i965/gen8_surface_state.c | 249 + 2 files changed, 2 insertions(+), 263 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index

[Mesa-dev] [PATCH 34/64] genxml: Add macros and #includes for gens 4-6

--- src/intel/genxml/genX_pack.h | 10 +- src/intel/genxml/gen_macros.h | 15 ++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/intel/genxml/genX_pack.h b/src/intel/genxml/genX_pack.h index 7967c29..0c25c4e 100644 --- a/src/intel/genxml/genX_pack.h +++

[Mesa-dev] [PATCH 30/64] anv, isl: Lower storage image formats in anv

ISL was being a bit too clever for its own good and lowering the format for us. This is all well and good *if* we always want to lower it. However, the GL driver selectively lowers the format depending on whether the surface is write-only or not. --- src/intel/isl/isl_surface_state.c | 8

[Mesa-dev] [PATCH 22/64] isl/state: Use the layout for computing qpitch rather than dimensions

For depth/stencil 1-D textures on SKL, we want them layed out in the old format that has been used since gen4. In order for the surface state fill-out code to handle, this it needs to distinguish based on layout rather than just dimensionality. --- src/intel/isl/isl_surface_state.c | 34

[Mesa-dev] [PATCH 44/64] i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen8-9

--- src/mesa/drivers/dri/i965/gen8_blorp.c | 99 ++ 1 file changed, 4 insertions(+), 95 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c index fcf5a53..b5c600b 100644 ---

[Mesa-dev] [PATCH 41/64] i965/miptree: Add a helper for getting the ISL clear color from a miptree

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 2 files changed, 28 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH 39/64] isl/state: Add support for OffsetX/Y in surface state

--- src/intel/isl/isl.h | 3 +++ src/intel/isl/isl_surface_state.c | 9 + 2 files changed, 12 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index a987482..4dd4a2f 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -844,6 +844,9 @@ struct

[Mesa-dev] [PATCH 05/64] i965: Remove fake W-tiled render target support

This hasn't been used since 1cfb4bc890b8 where we deleted the meta stencil blit path. --- src/mesa/drivers/dri/i965/brw_state.h| 6 -- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 25 src/mesa/drivers/dri/i965/gen8_surface_state.c | 25

[Mesa-dev] [PATCH 19/64] isl/state: Set SurfaceArray based on the surface dimension

According to the PRM, you can't set SurfaceArray for 3D or buffer textures. There doesn't seem to be a good reason not to set it when we can. On the other hand, if we don't set it we can end up getting strange results for 1-layer array textures such as textureSize() returning the wrong results.

[Mesa-dev] [PATCH 17/64] isl/state: Refactor the setup of clear colors

This commit switches clear colors to use #if's instead of a C if. This lets us properly handle SNB where the clear color field doesn't exist. --- src/intel/isl/isl_surface_state.c | 44 +++ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git

[Mesa-dev] [PATCH 32/64] genxml: Add enough XML for gens 4, 4.5, and 5 to get SURFACE_STATE

--- src/intel/genxml/Makefile.am | 3 +++ src/intel/genxml/Makefile.sources | 3 +++ src/intel/genxml/gen4.xml | 52 src/intel/genxml/gen45.xml| 56 +++ src/intel/genxml/gen5.xml | 56

[Mesa-dev] [PATCH 18/64] isl/state: Don't force-disable L2 bypass for everything

We already set the bit in the few cases where it's required by the docs so there's no need to set it all the time. This has no noticable perf impact for Dota 2 on Vulkan with the time demo I have. --- src/intel/isl/isl_surface_state.c | 5 - 1 file changed, 5 deletions(-) diff --git

[Mesa-dev] [PATCH 14/64] isl/state: Put pitch calculations together

--- src/intel/isl/isl_surface_state.c | 42 +++ 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 0ada3e4..50570aa 100644 --- a/src/intel/isl/isl_surface_state.c +++

[Mesa-dev] [PATCH 42/64] i965/miptree: Add a helper for getting the aux isl_surf from a miptree

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 70 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 ++ 2 files changed, 74 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH 02/64] i965/blorp/gen8: Use the correct max level and layer in emit_surface_states

We were adding in the base which is wrong because the values given in the miptree are relative to zero and not the base layer/level. Cc: "11.1 11.2 12.0" --- src/mesa/drivers/dri/i965/gen8_blorp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)

[Mesa-dev] [PATCH 13/64] isl/state: Put all dimension setup together and towards the top

--- src/intel/isl/isl_surface_state.c | 154 ++ 1 file changed, 74 insertions(+), 80 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 0f21e34..0ada3e4 100644 --- a/src/intel/isl/isl_surface_state.c +++

[Mesa-dev] [PATCH 07/64] i965/gen7, 8: Set SURFACE_IS_ARRAY for all non-3D texture types

There's no real reason why we shouldn't set this bit. It does affect how the sampler operates a bit but since you can have a 2D non-array view of a 2D_ARRAY texture that distinction is very weak. Also, this is what ISL will do and we would like this change to be isolated from using ISL. ---

[Mesa-dev] [PATCH 06/64] i965/gen4: Subtract 1 from buffer sizes

Cc: "11.1 11.2 12.0" --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index

[Mesa-dev] [PATCH 04/64] i965/fs: Use a default Y coordinate of 0 for TXF on gen9+

Previously, we were incrementing length but not actually putting anything in the Y coordinate. This meant that 1-D TXF operations had a garbage array index. If the surface is emitted as 1-D non-array, the coordinate gets discarded and it works fine. If it happens to be bound as an array

[Mesa-dev] [PATCH 03/64] i965/gen8: Use the qpitch from the aux_mt for AUX_QPITCH

--- src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index ee4781b..6a98d76 100644 ---

[Mesa-dev] [PATCH 37/64] isl: Add surface formats for on-MSAA CCS surfaces

--- src/intel/isl/isl.h | 16 src/intel/isl/isl_format_layout.csv | 9 + 2 files changed, 25 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 3bf7469..36038bc 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -349,6

[Mesa-dev] [PATCH 10/64] isl/state: Don't use designated initializers for the surface state

While designated initializers are nice, they also force us to put some things in the initializer and some things later. Surface state setup is complicated enough that this really hurs readability in the long run. --- src/intel/isl/isl_surface_state.c | 95 ---

[Mesa-dev] [PATCH 11/64] isl/state: Remove some unused fields

They're already zero-initialized and we have no plans of doing anything more interesting with them. --- src/intel/isl/isl_surface_state.c | 9 - 1 file changed, 9 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index ae8096f..c36ef3b

[Mesa-dev] [PATCH 12/64] isl/state: Put surface format setup at the top

--- src/intel/isl/isl_surface_state.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index c36ef3b..0f21e34 100644 --- a/src/intel/isl/isl_surface_state.c +++

[Mesa-dev] [PATCH 09/64] genxml/gen8, 9: Prefix the multisample format enum with MSFMT

This is what gen7 does and it's nice to have a prefix --- src/intel/genxml/gen8.xml | 4 ++-- src/intel/genxml/gen9.xml | 4 ++-- src/intel/isl/isl_surface_state.c | 8 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/intel/genxml/gen8.xml

[Mesa-dev] [PATCH 08/64] i965/blorp: Only set src_z for gen8+ 3D textures

Otherwise, we end up with a bogus value in the third component. On gen6-7 where we always use 2D textures, this can cause problems if the SurfaceArray bit is set in the SURFACE_STATE. --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 11 +-- 1 file changed, 9 insertions(+), 2

[Mesa-dev] [PATCH 31/64] genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7

The pack header generation scripts can't handle the case where you have two addresses in the same dword; they just take whatever is the last one. This meant that the MCS address wasn't properly getting handled. Since we don't care about append counters, we can just re-arrange the XML for now. ---

[Mesa-dev] [PATCH 01/64] i965: Drop Max3DTextureLevels to 512 on Sandy Bridge and prior

The RenderTargetViewExtent field of RENDER_SURFACE_STATE is supposed to be set to the depth of a 3-D texture when rendering. Unfortunatley, that field is only 9 bits on Sandy Bridge and prior so we can't actually bind a 3-D texturing for rendering if it has depth > 512. On Ivy Bridge, this field

[Mesa-dev] [PATCH 26/64] isl/state: Don't set SurfacePitch for gen9 1-D textures

This field is ignored by the hardware in this case and, on very large 1-D textures, it can end up being larger than the maximum allowed value. --- src/intel/isl/isl_surface_state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/isl/isl_surface_state.c

[Mesa-dev] [PATCH 00/64] i965: Start using ISL for filling out surface states

We would like to eventually start using ISL inside of the GL driver to replace the fairly sprawling layout code in brw_tex_layout.c and intel_mipmap_tree.c. However, that is a very big change that no one is ready to make yet. A smaller change, I thought, would be to start using ISL in blorp. In