On Monday, April 10, 2017 7:11:18 AM PDT Emil Velikov wrote:
> Hi all,
>
> On 10 April 2017 at 08:18, Kenneth Graunke wrote:
> > From: Daniel Vetter
> >
> > This was done because the kernel has 1 global address space, shared
> > with all render
On Monday, April 10, 2017 5:23:20 PM PDT Francisco Jerez wrote:
> The individual branches of an if/else/endif construct will be executed
> some unknown number of times between 0 and 1 relative to the parent
> block. Use some factor in between as weight while approximating the
> cost of spill/fill
This cache allows us to easily ensure that we have a unique anv_bo for
each gem handle. We'll need this in order to support multiple-import of
memory objects and semaphores.
v2 (Jason Ekstrand):
- Reject BO imports if the size doesn't match the prime fd size as
reported by lseek().
v3
On Mon, Apr 10, 2017 at 5:23 PM, Francisco Jerez
wrote:
> The individual branches of an if/else/endif construct will be executed
> some unknown number of times between 0 and 1 relative to the parent
> block. Use some factor in between as weight while approximating the
>
These calls look like leftover from fallback texture support first
being added to the st in 8f6d9e12be0be and then later being added
to core mesa in 00e203fe17cbf21.
The piglit test fp-incomplete-tex continues to work with this
change.
---
src/mesa/state_tracker/st_atom_sampler.c | 8 ++--
On 04/10/2017 06:09 PM, Timothy Arceri wrote:
On 11/04/17 03:11, Brian Paul wrote:
On 04/07/2017 09:21 PM, Timothy Arceri wrote:
This will be used to take ownership of freashly created renderbuffers,
avoiding the need to call the reference function which requires
locking.
V2: dereference any
Timothy Arceri writes:
> The key is just an unsigned int so there is never any real hashing
> done.
> ---
> src/mesa/main/hash.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/main/hash.c b/src/mesa/main/hash.c
> index
Might helper reduce cpu for some apps that use sso.
---
src/mesa/state_tracker/st_atom.h | 6 +-
src/mesa/state_tracker/st_atom_list.h| 8 ++-
src/mesa/state_tracker/st_atom_sampler.c | 94 ++--
src/mesa/state_tracker/st_program.c | 14 ++---
4 files
The key is just an unsigned int so there is never any real hashing
done.
---
src/mesa/main/hash.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/hash.c b/src/mesa/main/hash.c
index 670438a..eb25d88 100644
--- a/src/mesa/main/hash.c
+++
Quoting Dylan Baker (2017-04-10 11:50:36)
> Quoting Nirbheek Chauhan (2017-04-10 06:59:02)
> > Hello Jose,
> >
> > On Mon, Apr 10, 2017 at 5:41 PM, Jose Fonseca wrote:
> > > I've been trying to get native mingw to build. (It's still important to
> > > prototype mesademos
On 4 April 2017 at 19:11, Marek Olšák wrote:
> Why don't you set disableLinearOpt instead?
That seems like the wrong answer.
Can the hardware do mipmaps with the base level in linear aligned format,
but the other levels 1D tiled? If not why does addrlib give me that as a
The individual branches of an if/else/endif construct will be executed
some unknown number of times between 0 and 1 relative to the parent
block. Use some factor in between as weight while approximating the
cost of spill/fill instructions within a conditional if-else branch.
This favors spilling
On 11/04/17 03:11, Brian Paul wrote:
On 04/07/2017 09:21 PM, Timothy Arceri wrote:
This will be used to take ownership of freashly created renderbuffers,
avoiding the need to call the reference function which requires
locking.
V2: dereference any existing fb attachments and actually attach the
For using them with both occlusion and pipeline statistics queries.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_private.h | 4 ++--
src/amd/vulkan/radv_query.c | 22 +++---
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_query.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index cfe16a9d0e2..dc1844adb51 100644
--- a/src/amd/vulkan/radv_query.c
+++
The devil is in the shader again, otherwise this is
fairly straightforward.
The CTS contains no pipeline statistics copy to buffer
testcases, so I did a basic smoketest.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 2 +-
src/amd/vulkan/radv_private.h
The buffer sizes are specified just a few lines earlier, so don't
repeat ourselves.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_query.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_query.c
Series:
Reviewed-by: Timothy Arceri
On 11/04/17 03:23, Samuel Pitoiset wrote:
For both consistency and new bindless sampler types.
Signed-off-by: Samuel Pitoiset
---
src/compiler/glsl/builtin_functions.cpp | 11 ++-
1 file changed,
Karol told me that over IRC. Introducing ->getIsa() looks good to me.
On 04/11/2017 01:01 AM, Ilia Mirkin wrote:
I wanted to flip things over and use smxx notation...
On Apr 10, 2017 6:20 PM, "Samuel Pitoiset" > wrote:
Not
I wanted to flip things over and use smxx notation...
On Apr 10, 2017 6:20 PM, "Samuel Pitoiset"
wrote:
> Not sure why you get confused here. The chipset names are globally
> consistent inside the codegen part and we never use SMxx. Maybe add a
> comment like:
>
>
On Mon, Apr 10, 2017 at 3:13 PM, Nanley Chery wrote:
> On Mon, Apr 10, 2017 at 01:31:52PM -0700, Nanley Chery wrote:
> > Fixes 0039d0cf278 "anv/pass: Use anv_multialloc for allocating the
> anv_pass"
> >
> > Signed-off-by: Nanley Chery
> > ---
>
Hi,
I've been looking into this recently also. Unfortunately I don't think
these will get applied as is.
These changes have been submitted before but rejected because they make
existing race conditions worse. We really need to fix those first, I
really think we are going to need some
On Tue 04 Apr 2017, Kenneth Graunke wrote:
> This series imports libdrm_intel into the i965 driver, hacks and
> slashes it down to size, and greatly simplifies our relocation
> handling.
You did it! IT'S FINALLY HAPPENING!!! Thanks for taking the leap.
>
Not sure why you get confused here. The chipset names are globally
consistent inside the codegen part and we never use SMxx. Maybe add a
comment like:
#define NVISA_GK104_CHIPSET0xe0 /* SM30 */
If you really need this?
On 04/10/2017 11:41 PM, Matthew Mondazzi wrote:
Define references to
Series is:
Reviewed-by: Samuel Pitoiset
Thanks!
On 04/10/2017 04:55 PM, Boyan Ding wrote:
This is the third, and hopefully the last revision of ballot series.
This series mainly incorporates Ilia's feedback, with some fixes, more
check and code cleanup.
Please
On Mon, Apr 10, 2017 at 01:31:52PM -0700, Nanley Chery wrote:
> Fixes 0039d0cf278 "anv/pass: Use anv_multialloc for allocating the anv_pass"
>
> Signed-off-by: Nanley Chery
> ---
> src/intel/vulkan/anv_pass.c | 1 +
> 1 file changed, 1 insertion(+)
>
I rescind my
Define references to chipset did not actually use chipset, leading to
confusion. More relevant ISA constants put in place of chipset compares.
Signed-off-by: Matthew Mondazzi
---
.../drivers/nouveau/codegen/nv50_ir_driver.h | 7 ++--
Pushed the series, thanks!
Marek
On Mon, Apr 10, 2017 at 10:04 PM, Constantine Kharlamov
wrote:
> The idea is taken from radeonsi. The code mostly was already checking for null
> pixel shader, so little checks had to be added.
>
> Interestingly, acc. to testing with GTAⅣ,
Pushed, with slightly more descriptive commit msg.
-Brian
On 04/10/2017 12:31 PM, Bartosz Tomczyk wrote:
v2: fix indentation
---
src/mesa/main/readpix.c | 15 ++-
src/mesa/main/texstore.c | 15 +++
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git
Fixes 0039d0cf278 "anv/pass: Use anv_multialloc for allocating the anv_pass"
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_pass.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
index
---
src/mesa/main/arrayobj.c | 16
src/mesa/main/mtypes.h | 2 --
2 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index ab1b834b6d..39bdb2e715 100644
--- a/src/mesa/main/arrayobj.c
+++
---
src/mesa/main/fbobject.c | 1 -
src/mesa/main/mtypes.h | 1 -
src/mesa/main/renderbuffer.c | 15 +++
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index d486d01195..f85f26674d 100644
---
---
src/mesa/main/mtypes.h | 1 -
src/mesa/main/samplerobj.c | 16
2 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index d37a60d61c..5a1be17a92 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@
---
src/mesa/main/mtypes.h | 1 -
src/mesa/main/texobj.c | 19 ---
2 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 5a1be17a92..a1eabc8bf1 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@
---
src/mesa/main/mtypes.h | 2 --
src/mesa/main/pipelineobj.c | 16
src/mesa/main/shaderapi.c | 2 --
3 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 5de464cc1b..8b1577dd3f 100644
---
Bartosz Tomczyk (5):
mesa/arrayobj: use atomics for reference counting
mesa/pipelineobj: use atomics for reference counting
mesa/renderbuffer: use atomics for reference counting
mesa/samplerobj: use atomics for reference counting
mesa/texobj: use atomics for reference counting
Although I didn't see a statistically significant change in GTAⅣ benchmark, it
seem to have reduced stall for opening the door from a house to the outer world
at the first savepoint.
No changes in gpu.py tests of piglit in gbm mode.
v2: In the 1-st patch was occasionally removed empty line.
The idea is taken from radeonsi. The code mostly was already checking for null
pixel shader, so little checks had to be added.
Interestingly, acc. to testing with GTAⅣ, though binding of null shader happens
a lot at the start (then just stops), but draw_vbo() never actually sees null
ps.
v2:
Taken from radeonsi, required to remove dummy pixel shader in the next patch
Signed-off-by: Constantine Kharlamov
Reviewed-by: Marek Olšák
---
src/gallium/drivers/r600/evergreen_state.c | 1 +
src/gallium/drivers/r600/r600_pipe.h | 1 +
The idea is taken from radeonsi. The code lacks some checks for null vs,
and I'm unsure about some changes against that, so I left it in place.
Some statistics for GTAⅣ:
Average tesselation bind skip per frame: ≈350
Average geometric shaders bind skip per frame: ≈260
Skip of binding vertex ones
Please do, I don't have commits rights.
On 10.04.2017 20:44, Brian Paul wrote:
On 04/10/2017 12:35 PM, Bartosz Tomczyk wrote:
Yes, I tested with Piglit, there is no regression.
Do you need me to push this for you?
-Brian
On 10.04.2017 19:16, Brian Paul wrote:
On 04/09/2017 07:58 AM,
Quoting Nirbheek Chauhan (2017-04-10 06:59:02)
> Hello Jose,
>
> On Mon, Apr 10, 2017 at 5:41 PM, Jose Fonseca wrote:
> > I've been trying to get native mingw to build. (It's still important to
> > prototype mesademos with MSVC to ensure meson is up to the task, but long
>
On 04/10/2017 12:35 PM, Bartosz Tomczyk wrote:
Yes, I tested with Piglit, there is no regression.
Do you need me to push this for you?
-Brian
On 10.04.2017 19:16, Brian Paul wrote:
On 04/09/2017 07:58 AM, Bartosz Tomczyk wrote:
---
src/mesa/main/readpix.c | 15 ++-
Yes, I tested with Piglit, there is no regression.
On 10.04.2017 19:16, Brian Paul wrote:
On 04/09/2017 07:58 AM, Bartosz Tomczyk wrote:
---
src/mesa/main/readpix.c | 15 ++-
src/mesa/main/texstore.c | 15 +++
2 files changed, 21 insertions(+), 9 deletions(-)
v2: fix indentation
---
src/mesa/main/readpix.c | 15 ++-
src/mesa/main/texstore.c | 15 +++
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index 25823230d6..606d1e58e5 100644
--- a/src/mesa/main/readpix.c
mas...@eltechs.com writes:
> From: Maxim Maslov
The commit message needs some explanation of why we would want that
(given that 2835 is an ARM) and some performance data justifying the
change.
>
> --- src/gallium/drivers/vc4/vc4_tiling_lt.c | 93
From: Maxim Maslov
---
src/gallium/drivers/vc4/vc4_tiling_lt.c | 93 +++--
1 file changed, 90 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_tiling_lt.c
b/src/gallium/drivers/vc4/vc4_tiling_lt.c
index c9cbc65..d291262
On Mon, Apr 10, 2017 at 10:29:50AM -0700, Kenneth Graunke wrote:
> On Monday, April 10, 2017 1:31:11 AM PDT Chris Wilson wrote:
> > In general, does 10us resolution require compensation for clock_gettime()
> > overhead and checking against clock_getres()?
>
> FWIW, I copied the 10us threshold
On Monday, April 10, 2017 1:31:11 AM PDT Chris Wilson wrote:
> On Mon, Apr 10, 2017 at 10:09:17AM +0200, Daniel Vetter wrote:
> > On Mon, Apr 10, 2017 at 12:18:54AM -0700, Kenneth Graunke wrote:
> > > diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> > >
For both consistency and new bindless sampler types.
Signed-off-by: Samuel Pitoiset
---
src/compiler/glsl/builtin_functions.cpp | 65 +
1 file changed, 33 insertions(+), 32 deletions(-)
diff --git
For both consistency and new bindless sampler types.
Signed-off-by: Samuel Pitoiset
---
src/compiler/glsl/builtin_functions.cpp | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/compiler/glsl/builtin_functions.cpp
For both consistency and new bindless sampler types.
Signed-off-by: Samuel Pitoiset
---
src/compiler/glsl/builtin_functions.cpp | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/compiler/glsl/builtin_functions.cpp
On Wed, Apr 5, 2017 at 11:27 AM, Kristian Høgsberg wrote:
> On Wed, Apr 5, 2017 at 11:11 AM, Jason Ekstrand wrote:
>> On Wed, Apr 5, 2017 at 11:03 AM, Emil Velikov
>> wrote:
>>>
>>> On 5 April 2017 at 18:55, Daniel Vetter
On 04/09/2017 07:58 AM, Bartosz Tomczyk wrote:
---
src/mesa/main/readpix.c | 15 ++-
src/mesa/main/texstore.c | 15 +++
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index 25823230d6..14568de497
On 04/07/2017 09:21 PM, Timothy Arceri wrote:
This will be used to take ownership of freashly created renderbuffers,
avoiding the need to call the reference function which requires
locking.
V2: dereference any existing fb attachments and actually attach the
new rb.
v3: split out
---
.../drivers/swr/rasterizer/common/simd16intrin.h | 198 +++--
src/gallium/drivers/swr/rasterizer/core/clip.h | 6 +-
src/gallium/drivers/swr/rasterizer/core/context.h | 2 +-
.../swr/rasterizer/core/format_conversion.h| 8 +-
---
.../drivers/swr/rasterizer/jitter/JitManager.cpp | 10 ---
.../drivers/swr/rasterizer/jitter/JitManager.h | 6 -
.../drivers/swr/rasterizer/jitter/builder_misc.cpp | 31 --
.../drivers/swr/rasterizer/jitter/builder_misc.h | 5
4 files changed, 52
---
src/gallium/drivers/swr/rasterizer/archrast/archrast.cpp | 2 +-
src/gallium/drivers/swr/rasterizer/archrast/archrast.h| 2 +-
src/gallium/drivers/swr/rasterizer/archrast/eventmanager.h| 2 +-
---
src/gallium/drivers/swr/rasterizer/core/knobs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/knobs.h
b/src/gallium/drivers/swr/rasterizer/core/knobs.h
index e347558..7928f5d 100644
---
---
src/gallium/drivers/swr/rasterizer/common/simdintrin.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
b/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
index 1e3f14c..61c0c54 100644
---
---
.../drivers/swr/rasterizer/jitter/JitManager.cpp | 34 --
.../drivers/swr/rasterizer/jitter/JitManager.h | 1 -
2 files changed, 35 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
---
src/gallium/drivers/swr/rasterizer/core/api.cpp | 2 +-
src/gallium/drivers/swr/rasterizer/core/backend.cpp | 1 -
src/gallium/drivers/swr/rasterizer/core/binner.cpp | 8
3 files changed, 1 insertion(+), 10 deletions(-)
diff --git
---
.../drivers/swr/rasterizer/codegen/gen_backends.py | 25 --
.../drivers/swr/rasterizer/core/multisample.cpp| 44 +-
.../drivers/swr/rasterizer/core/multisample.h | 98 --
3 files changed, 92 insertions(+), 75 deletions(-)
diff --git
Quick patch to remove some unused template params to cut down
rasterizer compile time.
---
src/gallium/drivers/swr/rasterizer/core/binner.cpp | 8 +--
.../drivers/swr/rasterizer/core/rasterizer.cpp | 6 +-
.../drivers/swr/rasterizer/core/rasterizer.h | 67 +-
3
---
src/gallium/drivers/swr/rasterizer/core/state.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/state.h
b/src/gallium/drivers/swr/rasterizer/core/state.h
index eec68cd..535b85e 100644
---
Implement widened clipper for SIMD16.
---
.../drivers/swr/rasterizer/common/simd16intrin.h | 41 +-
src/gallium/drivers/swr/rasterizer/core/binner.cpp | 17 +-
src/gallium/drivers/swr/rasterizer/core/clip.cpp | 91 +-
src/gallium/drivers/swr/rasterizer/core/clip.h | 1027
Fix PA NextPrim for SIMD8 on SIMD16.
---
src/gallium/drivers/swr/rasterizer/core/pa_avx.cpp | 44 +++---
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/pa_avx.cpp
b/src/gallium/drivers/swr/rasterizer/core/pa_avx.cpp
index
Highlights; compile time fix, simd16 work, code cleanup.
Tim Rowley (12):
swr: [rasterizer core] Reduce templates to speed compile
swr: [rasterizer core] Multisample sample position setup change
swr: [rasterizer core] SIMD16 Frontend WIP - Clipper
swr: [rasterizer core] SIMD16 Frontend
For patches 2-3:
Reviewed-by: Marek Olšák
Marek
On Mon, Apr 10, 2017 at 11:44 AM, Constantine Kharlamov
wrote:
> If that helps, I can split this patch to two: α) Adding checks for null ps,
> and β) removing the dummy ps. I didn't do that originally,
On Sun, Apr 9, 2017 at 11:09 PM, Constantine Kharlamov
wrote:
> The idea is taken from radeonsi. The code lacks some checks for null vs,
> and I'm unsure about some changes against that, so I left it in place.
>
> Some statistics for GTAⅣ:
> Average tesselation bind skip per
For the series:
Reviewed-by: Marek Olšák
Marek
On Mon, Apr 10, 2017 at 11:49 AM, Samuel Pitoiset
wrote:
> Only the Radeon kernel driver exposed the GPU temperature and
> the shader/memory clocks, this implements the same functionality
> for the
Reviewed-by: Marek Olšák
Marek
On Fri, Apr 7, 2017 at 6:30 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> Fixes a bug in
> KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters.
> ---
>
Other than my comment on patch 3, the series is:
Reviewed-by: Marek Olšák
Marek
On Thu, Apr 6, 2017 at 12:07 AM, Samuel Pitoiset
wrote:
> For bindless.
>
> Signed-off-by: Samuel Pitoiset
> ---
>
On Thu, Apr 6, 2017 at 12:07 AM, Samuel Pitoiset
wrote:
> For bindless.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/gallium/drivers/radeonsi/si_descriptors.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff
This makes it much easier to throw together a bit of dynamic state. It
also automatically handles flushing so you don't accidentally forget.
---
src/intel/blorp/blorp_genX_exec.h | 114 +-
1 file changed, 50 insertions(+), 64 deletions(-)
diff --git
Reviewed-by: Marek Olšák
Marek
On Fri, Apr 7, 2017 at 6:44 PM, Samuel Pitoiset
wrote:
> To silent the following compiler warning:
>
> common/ac_llvm_build.c: In function ‘ac_build_image_opcode’:
> common/ac_llvm_build.c:1080:3: warning: ‘name’
Hi Nicolai,
I think there is a simpler way to do this. Instead of going through
update_shaders, we can just set some bit in a user data SGPR e.g.
SI_SGPR_VS_STATE_BITS[1] and the vertex shader can clear gl_BaseVertex
based on that bit. There is no performance concern due to additional
v2: Check if each channel is masked in TGSI_OPCODE_BALLOT (Ilia Mirkin)
Signed-off-by: Boyan Ding
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 31 ++
1 file changed, 31 insertions(+)
diff --git
readInvocationARB() and readFirstInvocationARB() need SHFL.IDX
instruction which is introduced in Kepler.
Reviewed-by: Ilia Mirkin
Signed-off-by: Boyan Ding
---
docs/features.txt | 2 +-
docs/relnotes/17.1.0.html
Implementation of readFirstInvocationARB() on nvidia hardware needs a
ballotARB(true) used to decide the first active thread. This expressed
in gm107 asm as (supposing output is $r0):
vote any $r0 0x1 0x1
To model the always true input, which corresponds to the second 0x1
above, we make
GF100's ISA encoding has a weird form of predicate destination where its
3 bits are split across whole the instruction. Use a dedicated setPDSTL
function instead of original defId which is incorrect in this case.
v2: (Ilia Mirkin)
Change API of setPDSTL() to handle cases of no output
Fix setting
v2: Add name strings in nv50_ir_print.cpp (Ilia Mirkin)
Signed-off-by: Boyan Ding
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 5 +
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 5 +
Reviewed-by: Ilia Mirkin
Signed-off-by: Boyan Ding
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 27 ++
1 file changed, 27 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
v2: (Samuel Pitoiset)
Add an assertion to check if the target is Kepler
Make sure that asImm() is not NULL
v3: (Ilia Mirkin)
Check the range of immediate value of OP_SHFL
Use the new setPDSTL API
Signed-off-by: Boyan Ding
---
v2: Make sure that asImm() is not NULL (Samuel Pitoiset)
v3: Check the range of immediate in OP_SHFL (Ilia Mirkin)
Signed-off-by: Boyan Ding
---
.../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 56 ++
1 file changed, 56 insertions(+)
diff --git
v2: Emit the original hard-coded 0x1c03 when OP_SHFL is used in gm107's
lowering (Samuel Pitoiset)
Signed-off-by: Boyan Ding
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 23 ++
.../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 15
This is the third, and hopefully the last revision of ballot series.
This series mainly incorporates Ilia's feedback, with some fixes, more
check and code cleanup.
Please review.
Boyan Ding (9):
gm107/ir: Emit third src 'bound' and optional predicate output of SHFL
nvc0/ir: Properly handle a
Hi all,
On 10 April 2017 at 08:18, Kenneth Graunke wrote:
> From: Daniel Vetter
>
> This was done because the kernel has 1 global address space, shared
> with all render clients, for gtt mmap offsets, and that address space
> was only 32bit on
https://bugs.freedesktop.org/show_bug.cgi?id=100613
Vedran Miletić changed:
What|Removed |Added
CC||ved...@miletic.net
This prevents potential segfaults in case the buffer was merged and the
mem pointer is then no longer valid
Signed-off-by: Carlos Rafael Giani
---
gst-decoder.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/gst-decoder.c b/gst-decoder.c
The QoS and max-lateness settings are copied from GstVideoSink, since here,
the appsink subclass specifically handles video
Signed-off-by: Carlos Rafael Giani
---
gst-video-appsink.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Hello Jose,
On Mon, Apr 10, 2017 at 5:41 PM, Jose Fonseca wrote:
> I've been trying to get native mingw to build. (It's still important to
> prototype mesademos with MSVC to ensure meson is up to the task, but long
> term, I think I'll push for dropping MSVC support from
On 04/10/2017 02:33 PM, Ilia Mirkin wrote:
I assume Pascal is the same as Maxwell. Using tic, it gets 16...
Makes sense.
Reviewed-by: Samuel Pitoiset
On Apr 10, 2017 5:32 AM, "Samuel Pitoiset" >
I assume Pascal is the same as Maxwell. Using tic, it gets 16...
On Apr 10, 2017 5:32 AM, "Samuel Pitoiset"
wrote:
> How about Pascal?
>
> On 04/08/2017 09:10 PM, Ilia Mirkin wrote:
>
>> We currently don't pass the low byte of the address via the surface
>> info, so
On 10 April 2017 at 11:15, Juan A. Suarez Romero wrote:
> On Fri, 2017-04-07 at 19:38 +0100, Emil Velikov wrote:
>> On 7 April 2017 at 12:30, Juan A. Suarez Romero wrote:
>> > Both scripts does not use a file with the commits to ignore. So if we
>> >
On Fri, Apr 07, 2017 at 10:42:21PM -0700, Jason Ekstrand wrote:
> This is mostly a re-send of previous patches. The two things that have
> changed over the last version is that the first patch is now actually
> correct for gen6. Prior to sending the original version, I tested it only
> with
On 08/04/17 23:07, Jose Fonseca wrote:
On 08/04/17 00:24, Dylan Baker wrote:
Quoting Jose Fonseca (2017-03-30 15:19:31)
Cool. BTW, another alternative (for things like LLVM) would be to
chain build systems (ie, have a wrap that builds LLVM invoking CMake)
Jose
I have no idea whether
https://bugs.freedesktop.org/show_bug.cgi?id=100613
İsmail Dönmez changed:
What|Removed |Added
CC||ism...@i10z.com
--
On Fri, 2017-04-07 at 19:38 +0100, Emil Velikov wrote:
> On 7 April 2017 at 12:30, Juan A. Suarez Romero wrote:
> > Both scripts does not use a file with the commits to ignore. So if we
> > have handled one of the suggested commits and decided we won't pick it,
> > the
Only the Radeon kernel driver exposed the GPU temperature and
the shader/memory clocks, this implements the same functionality
for the AMDGPU kernel driver.
These queries will return 0 if the DRM version is less than 3.10,
I don't explicitely check the version here because the query
codepath is
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