[Mesa-dev] [PATCH] st/mesa: fix assert to be simpler

From: Dave Airlie I just noticed a warning with a non-debug build, but really this could all be one line, and I'm not even 100% the assert makes sense here. --- src/mesa/state_tracker/st_texture.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] st/dri: Add support for PIPE_FORMAT_RGBX8888_UNORM

On Mon, Jun 19, 2017 at 11:21 PM, Lepton Wu wrote: > The original dri2_format_to_pipe_format function just misses case branch > for __DRI_IMAGE_FORMAT_XBGR. I discovered this when debugging one google > map crash inside emulator. > > Signed-off-by: Lepton Wu

Re: [Mesa-dev] [PATCH] [RFC] r600g: do not pick TGSI input registers at random

This was discussed on IRC, there was much confusion, and overall there was a belief like the bug in some place other. A few minutes ago I was writing a follow-up in mail because I'll have trouble replying today. And… for writing a reply I found the actual bug, and lol, it is funny! Here's the

Re: [Mesa-dev] [RFC PATCH] dri3: Sync after buffer swaps with glXSwapBuffers

On 06/20/2017 05:09 AM, Michel Dänzer wrote: On 20/06/17 03:00 AM, Thomas Hellstrom wrote: On 06/19/2017 07:44 PM, Thomas Hellstrom wrote: On 06/19/2017 07:26 PM, Eric Anholt wrote: Thomas Hellstrom writes: Applications calling glXSwapBuffers should be able to expect

[Mesa-dev] [PATCH 3/4] radv: compile fragment shader first.

From: Dave Airlie This reorders things as we need something from the fs for the vs key. Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_pipeline.c | 54 +- 1 file changed, 27 insertions(+), 27 deletions(-)

[Mesa-dev] [PATCH 4/4] radv: handle primitive id input into fragment shader with no geom shader

From: Dave Airlie Fixes: dEQP-VK.pipeline.framebuffer_attachment.no_attachments dEQP-VK.pipeline.framebuffer_attachment.no_attachments_ms Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 26 +---

[Mesa-dev] [PATCH 1/4] radv: set use_prim_id for tess shaders correctly.

From: Dave Airlie Just noticed in passing. Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index

[Mesa-dev] [PATCH 2/4] radv: set prim_id for geometry shaders

From: Dave Airlie Noticed in passing. Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 5 +++-- src/amd/common/ac_nir_to_llvm.h | 1 + src/amd/vulkan/si_cmd_buffer.c | 6 ++ 3 files changed, 10 insertions(+), 2 deletions(-) diff

Re: [Mesa-dev] [RFC PATCH] dri3: Sync after buffer swaps with glXSwapBuffers

On 20/06/17 03:00 AM, Thomas Hellstrom wrote: > On 06/19/2017 07:44 PM, Thomas Hellstrom wrote: >> On 06/19/2017 07:26 PM, Eric Anholt wrote: >>> Thomas Hellstrom writes: >>> Applications calling glXSwapBuffers should be able to expect that any X rendering

Re: [Mesa-dev] [PATCH v2 2/3] nir: Add a lowering pass for UYVY textures

Kristian, Thanks for the review comments. By my tests, UYVY buffer can be sampled and rendered correctly. So there is no swap of U/V channel here. -Original Message- From: Lin, Johnson Sent: Tuesday, June 20, 2017 9:43 AM To: mesa-dev@lists.freedesktop.org Cc: Lin, Johnson

Re: [Mesa-dev] [PATCH 03/16] mesa: rework ParameterList to allow packing

On 20/06/17 11:50, Timothy Arceri wrote: Currently everything is padded to 4 elements. Making the list more flexible will allow us to do uniform packing. This change requires us to remove the existing packing in _mesa_add_typed_unnamed_constant() in order to avoid regressions. This packing will

[Mesa-dev] [PATCH 15/16] mesa/st: handle indirect indexing of asm programs for backends that pack uniforms

Currently asm programs don't support packing and are always padded to 4. --- src/mesa/state_tracker/st_mesa_to_tgsi.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c

[Mesa-dev] [PATCH 14/16] mesa/st: hack const index

This is wrong fix me, just set to 4 to reduce piglit failures for now. --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 8cb6b16..22112c5

[Mesa-dev] [PATCH 16/16] radeonsi: enable uniform packing

--- src/gallium/drivers/radeonsi/si_shader.c | 4 ++-- src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 10 ++ src/mesa/state_tracker/st_context.c | 2 ++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c

[Mesa-dev] [PATCH 11/16] mesa/st: adjust packed const buffer index for indirect indexing

The extra mul should end up const folded away in the backend. --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 25 + 1 file changed, 25 insertions(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index

[Mesa-dev] [PATCH 13/16] gallivm: relax assert() to support uniform packing

For uniform packing we multiply the const buffer index by its componets in the st rather than in the backend. --- src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c

[Mesa-dev] [PATCH 12/16] mesa/st: make sure the const buffer is large enough for packed uniforms

--- src/mesa/state_tracker/st_atom_constbuf.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_atom_constbuf.c b/src/mesa/state_tracker/st_atom_constbuf.c index 7f17546..eb8f6b3 100644 --- a/src/mesa/state_tracker/st_atom_constbuf.c +++

[Mesa-dev] [PATCH 09/16] mesa/st: get immediate size from param list

--- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +- src/mesa/state_tracker/st_mesa_to_tgsi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 885fd7d..1bd55e4 100644 ---

[Mesa-dev] [PATCH 06/16] mesa: add packing support for setting uniform handles

--- src/mesa/main/uniform_query.cpp | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp index fb31826..b5ff012 100644 --- a/src/mesa/main/uniform_query.cpp +++ b/src/mesa/main/uniform_query.cpp @@

[Mesa-dev] [PATCH 10/16] mesa/st: set correct constant buffer index when uniform packing enabled

--- src/mesa/state_tracker/st_atifs_to_tgsi.c | 7 +-- src/mesa/state_tracker/st_atifs_to_tgsi.h | 1 + src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 5 +++-- src/mesa/state_tracker/st_mesa_to_tgsi.c | 5 +++-- src/mesa/state_tracker/st_program.c| 2 +- 5 files changed, 13

[Mesa-dev] [PATCH 03/16] mesa: rework ParameterList to allow packing

Currently everything is padded to 4 elements. Making the list more flexible will allow us to do uniform packing. This change requires us to remove the existing packing in _mesa_add_typed_unnamed_constant() in order to avoid regressions. This packing will no longer be required once we add full

[Mesa-dev] [PATCH 04/16] mesa: create copy uniform to storage helpers

These will be used in the following patch to allow copying directly to the param list when packing is enabled. --- src/mesa/main/uniform_query.cpp | 154 1 file changed, 91 insertions(+), 63 deletions(-) diff --git a/src/mesa/main/uniform_query.cpp

[Mesa-dev] [PATCH 05/16] mesa: add packing support for setting uniforms

--- src/mesa/main/uniform_query.cpp | 73 ++--- 1 file changed, 54 insertions(+), 19 deletions(-) diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp index 75d9df4..fb31826 100644 --- a/src/mesa/main/uniform_query.cpp +++

[Mesa-dev] [PATCH 08/16] mesa: add uniform packing support to _mesa_add_typed_unnamed_constant()

--- src/mesa/program/prog_parameter.c | 53 +- src/mesa/program/prog_parameter.h | 14 +--- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 5 +-- 3 files changed, 43 insertions(+), 29 deletions(-) diff --git a/src/mesa/program/prog_parameter.c

[Mesa-dev] [PATCH 07/16] mesa/st: allow for uniform packing when adding uniforms to param list

--- src/mesa/program/ir_to_mesa.cpp| 45 +++--- src/mesa/program/ir_to_mesa.h | 3 +- src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 +- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +- 4 files changed, 39 insertions(+), 13 deletions(-) diff

[Mesa-dev] [PATCH 02/16] mesa: rework _mesa_add_parameter() to only add a single param

This is more inline with what the functions name suggests it should do, and makes the code much easier to follow. This will also make adding uniform packing support much simpler. --- src/compiler/glsl/shader_cache.cpp | 4 +-- src/mesa/program/ir_to_mesa.cpp| 19 ++---

[Mesa-dev] [PATCH 01/16] mesa: add PackedDriverUniformStorage const

Will be used to determine whether to take packing code paths or not. --- src/mesa/main/mtypes.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 65f638b..ff9a814 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@

[Mesa-dev] RFC uniform packing for gallium

I've been working on this on and off and wanted to get some feedback on the approach I've taken before putting to much time in fixing the remaining bugs. There are around 150 piglit tests still failing. The main goal of this series is to reduce the cpu overhead cause by

[Mesa-dev] [PATCH 1/2] gallium/vbuf: add some const qualifiers

Helps understandability a bit. --- src/gallium/auxiliary/util/u_vbuf.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/gallium/auxiliary/util/u_vbuf.c b/src/gallium/auxiliary/util/u_vbuf.c index 8361e64..b342f34 100644 ---

[Mesa-dev] [PATCH 2/2] gallium/vbuf: avoid segfault when we get invalid glDrawRangeElements()

A common user error is to call glDrawRangeElements() with the 'end' argument being one too large. If we use the vbuf module to translate some vertex attributes this error can cause us to read past the end of the mapped hardware buffer, resulting in a crash. This patch adjusts the vertex count to

[Mesa-dev] [PATCH v2 3/3] i965/i915: Add UYVY as the supported format

Trigger the correct sampler options for it. Similar with YUYV --- src/intel/compiler/brw_compiler.h| 1 + src/intel/compiler/brw_nir.c | 1 + src/mesa/drivers/dri/i915/intel_screen.c | 7 +-- src/mesa/drivers/dri/i965/brw_wm.c | 7 +++

[Mesa-dev] [PATCH v2 1/3] dri: Add UYVY as available format

UYVY is diffrent with YUYV in byte order. YUYV is already declared in dri_interface.h, this CL add the difinitions for UYVY. Drivers can add UYVY as supported format --- include/GL/internal/dri_interface.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH v2 2/3] nir: Add a lowering pass for UYVY textures

Similar with support for YUYV but with byte order difference in sampler --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_lower_tex.c | 16 2 files changed, 17 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index

[Mesa-dev] [PATCH] st/dri: Add support for PIPE_FORMAT_RGBX8888_UNORM

The original dri2_format_to_pipe_format function just misses case branch for __DRI_IMAGE_FORMAT_XBGR. I discovered this when debugging one google map crash inside emulator. Signed-off-by: Lepton Wu --- src/gallium/state_trackers/dri/dri2.c | 3 +++ 1 file changed, 3

Re: [Mesa-dev] [PATCH 08/13] anv: Adjust params of color buffer transitioning functions

On Mon, Jun 19, 2017 at 4:57 PM, Nanley Chery wrote: > On Mon, Jun 19, 2017 at 04:33:29PM -0700, Jason Ekstrand wrote: > > On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery > > wrote: > > > > > Splitting out these fields will make the color buffer

Re: [Mesa-dev] [PATCH 13/13] anv/gpu_memcpy: Rename the gpu_memcpy function

I'd mildly prefer streamout_memcpy to streamout_cpy. On Tue, Jun 13, 2017 at 11:42 AM, Nanley Chery wrote: > A GPU memcpy function could alternatively be implemented using MI_* > commands. Provide more detail into how this one operates in case another > memcpy function is

Re: [Mesa-dev] [PATCH 05/13] anv: Add and use color auxiliary buffer helpers

On Mon, Jun 19, 2017 at 4:46 PM, Nanley Chery wrote: > On Mon, Jun 19, 2017 at 04:16:32PM -0700, Jason Ekstrand wrote: > > On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery > > wrote: > > > > > v2: > > > - Check for aux levels in layer helper (Jason

Re: [Mesa-dev] [PATCH 1/2] RFC i965: Bypass a couple of libraries for syscall on x84_64

On Monday, 2017-06-19 12:22:07 -0700, Chad Versace wrote: > The other reason for removing all uses of drmIoctl() is, imo, it's > excessive to jump through the PLT into a shared object for a mere ioctl > wrapper. Agreed, but doesn't my suggestion of moving drmIoctl() to the drm header as either a

Re: [Mesa-dev] [PATCH 08/13] anv: Adjust params of color buffer transitioning functions

On Mon, Jun 19, 2017 at 04:33:29PM -0700, Jason Ekstrand wrote: > On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery > wrote: > > > Splitting out these fields will make the color buffer transitioning > > function simpler when it gains more features. > > > > Signed-off-by:

Re: [Mesa-dev] [PATCH 05/13] anv: Add and use color auxiliary buffer helpers

On Mon, Jun 19, 2017 at 04:16:32PM -0700, Jason Ekstrand wrote: > On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery > wrote: > > > v2: > > - Check for aux levels in layer helper (Jason Ekstrand) > > - Don't assert aux is present, return 0 if it isn't. > > - Use the helpers. >

Re: [Mesa-dev] [PATCH 08/13] anv: Adjust params of color buffer transitioning functions

On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery wrote: > Splitting out these fields will make the color buffer transitioning > function simpler when it gains more features. > > Signed-off-by: Nanley Chery > --- > src/intel/vulkan/anv_blorp.c

Re: [Mesa-dev] [PATCH v2 02/10] i965: Track initial CPU domain for mappings

On Monday, June 19, 2017 3:55:01 AM PDT Chris Wilson wrote: > If we need to force a cache domain transition (e.g. a buffer was in the > CPU domain and we want to access it via WC) then we need to trigger a > clflush. This overrides the use of MAP_ASYNC as we call into the kernel > to change

Re: [Mesa-dev] [PATCH 07/13] anv/blorp: Remove 3D subresource transition workaround

On Wed, Jun 14, 2017 at 3:06 PM, Nanley Chery wrote: > On Wed, Jun 14, 2017 at 09:32:22AM +0200, Iago Toral wrote: > > On Tue, 2017-06-13 at 11:41 -0700, Nanley Chery wrote: > > > For 3D image subresources undergoing a layout transition via > > > PipelineBarrier, we

Re: [Mesa-dev] [PATCH 05/13] anv: Add and use color auxiliary buffer helpers

On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery wrote: > v2: > - Check for aux levels in layer helper (Jason Ekstrand) > - Don't assert aux is present, return 0 if it isn't. > - Use the helpers. > > Signed-off-by: Nanley Chery > --- >

Re: [Mesa-dev] [PATCH 03/13] intel/isl: Limit CCS to one subresource on gen7

On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery wrote: > Signed-off-by: Nanley Chery > --- > src/intel/isl/isl.c | 9 +++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c > index

Re: [Mesa-dev] [PATCH 02/13] intel/blorp: Assert on gen7 fast-cleared subresource

On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery wrote: > Signed-off-by: Nanley Chery > --- > src/intel/blorp/blorp_clear.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c

Re: [Mesa-dev] [PATCH 01/13] intel/blorp: Assert on subresource in surface_info_init

General comment: "Subresource" is not a term that we've historically used outside of Vulkan. Maybe better to just say "intel/blorp: Assert that levels and layers are in range" On Tue, Jun 13, 2017 at 11:41 AM, Nanley Chery wrote: > Signed-off-by: Nanley Chery

Re: [Mesa-dev] [PATCH V3] i965/cnl: Add l3 configuration for Cannonlake

Anuj Phogat writes: > From: Ben Widawsky > > V2 (Anuj): > Squash the changes in one patch rebase on master. > Address the review comments made by Francisco Jerez. > Do the URB allocation per slice (not per bank). > > V3 (Anuj): > Update the

Re: [Mesa-dev] [PATCH V2 2/2] i965: Add a variable for size increment per bank in get_l3_way_size()

Anuj Phogat writes: > On Mon, Jun 19, 2017 at 2:18 PM, Francisco Jerez > wrote: >> Anuj Phogat writes: >> >>> Adding min_size_increment_per_bank variable better explains the >>> computation of L3 way size in the function.

Re: [Mesa-dev] [PATCH 00/13] anv: Prep-work for layout-based CCS resolves

On Thu, Jun 15, 2017 at 11:28:14AM +0200, Iago Toral wrote: > On Wed, 2017-06-14 at 10:15 +0200, Iago Toral wrote: > > I dropped a minor suggestion in patch 7 (feel free to ignore) and a > > style issue in patch 8, otherwise: > > > > Patches 1-8 are: > > Reviewed-by: Iago Toral Quiroga

Re: [Mesa-dev] [PATCH 2/4] i965: Use I915_EXEC_NO_RELOC

Quoting Jason Ekstrand (2017-06-19 22:00:45) > On Mon, Jun 19, 2017 at 12:53 PM, Chris Wilson > wrote: > > Quoting Kenneth Graunke (2017-06-19 20:28:31) > > On Monday, June 19, 2017 3:06:48 AM PDT Chris Wilson wrote: > > > -   if (target != batch->bo) >

Re: [Mesa-dev] [PATCH 12/18] i965: Convert CC state on gen4-5 to genxml.

On Monday, June 19, 2017 11:13:05 AM PDT Rafael Antognolli wrote: > On Sat, Jun 17, 2017 at 11:31:51AM -0700, Kenneth Graunke wrote: > > On Friday, June 16, 2017 4:31:25 PM PDT Rafael Antognolli wrote: > > > Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the > > > color calc

[Mesa-dev] [PATCH V3] i965/cnl: Add l3 configuration for Cannonlake

From: Ben Widawsky V2 (Anuj): Squash the changes in one patch rebase on master. Address the review comments made by Francisco Jerez. Do the URB allocation per slice (not per bank). V3 (Anuj): Update the comment. Format the table as other l3 config tables.

Re: [Mesa-dev] [PATCH V2 2/2] i965: Add a variable for size increment per bank in get_l3_way_size()

On Mon, Jun 19, 2017 at 2:18 PM, Francisco Jerez wrote: > Anuj Phogat writes: > >> Adding min_size_increment_per_bank variable better explains the >> computation of L3 way size in the function. >> >> V2: Use const variable for

Re: [Mesa-dev] [PATCH] i965/cnl: Add l3 configuration for Cannonlake

Anuj Phogat writes: > From: Ben Widawsky > > V2 (Anuj): > Squash the changes in one patch rebase on master. > Address the review comments made by Francisco Jerez. You seem to have missed half of my review comments, I'll repeat them below for

Re: [Mesa-dev] [PATCH 1/2] glsl: allow inputs in interface blocks in interpolateAt*

On 06/19/2017 04:45 AM, Nicolai Hähnle wrote: > On 18.06.2017 21:18, Ian Romanick wrote: >> On 06/16/2017 01:37 PM, Nicolai Hähnle wrote: >>> From: Nicolai Hähnle >>> >>> Since interface blocks are simply considered groupings of input >>> variables, >>> this is allowed.

Re: [Mesa-dev] [PATCH mesa] mesa/format_info: use designated initialiser list

On 06/19/2017 04:01 AM, Eric Engestrom wrote: > Also, make that table const, since no-one is supposed to modify it anyway. I certainly like this, but I'm not sure we can use designated initializers in common Mesa code due to MSVC. Brian? > Signed-off-by: Eric Engestrom

Re: [Mesa-dev] [PATCH] i965: Resolve framebuffers before signaling the fence

Quoting Chad Versace (2017-06-19 19:42:16) > On Mon 12 Jun 2017, Chris Wilson wrote: > > brw_emit_mi_flush(brw); > > > > switch (fence->type) { > > @@ -335,6 +363,8 @@ brw_gl_fence_sync(struct gl_context *ctx, struct > > gl_sync_object *_sync, > > struct brw_context *brw =

[Mesa-dev] [PATCH] i965: Remove spurious mutex frobbing around call to intel_miptree_blit

From: Ian Romanick These locks were added in 2f28a0dc, but I don't see anything in the intel_miptree_blit path that should make this necessary. Signed-off-by: Ian Romanick Cc: Kristian Høgsberg ---

Re: [Mesa-dev] [PATCH V2 2/2] i965: Add a variable for size increment per bank in get_l3_way_size()

Anuj Phogat writes: > Adding min_size_increment_per_bank variable better explains the > computation of L3 way size in the function. > > V2: Use const variable for min_size_increment_per_bank. > > Signed-off-by: Anuj Phogat > Cc: Francisco Jerez

Re: [Mesa-dev] [PATCH V2 1/2] i965: Fix broxton 2x6 l3 config

Anuj Phogat writes: > The new table added in this patch matches with the table > in gfxspecs. We were programming the wrong values earlier. > > V2: Update the comment. > > Signed-off-by: Anuj Phogat > Cc: Francisco Jerez >

[Mesa-dev] [AppVeyor] mesa master #4674 completed

Build mesa 4674 completed Commit bf5ca4f0b2 by Lionel Landwerlin on 4/24/2017 2:12 AM: i965: perf: use gen_device_info rather then brw_context\n\nSigned-off-by: Lionel Landwerlin \nReviewed-by: Kenneth Graunke

Re: [Mesa-dev] [PATCH 1/2] radeonsi: keep track of the sampler state for texture handles

On Mon, Jun 19, 2017 at 7:29 PM, Samuel Pitoiset wrote: > Needed for updating all resident texture descriptors when > dirty_tex_counter changes. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/radeonsi/si_descriptors.c | 12

Re: [Mesa-dev] [PATCH 1/2] radeonsi: keep track of the sampler state for texture handles

On Mon, Jun 19, 2017 at 10:06 PM, Marek Olšák wrote: > On Mon, Jun 19, 2017 at 7:29 PM, Samuel Pitoiset > wrote: >> Needed for updating all resident texture descriptors when >> dirty_tex_counter changes. >> >> Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH v1 2/7] etnaviv: Add return statement to etna_amode so compiler is happy

On Mon, Jun 19, 2017 at 12:52 PM, Chad Versace wrote: > On Fri 16 Jun 2017, Christian Gmeiner wrote: >> 2017-06-16 14:54 GMT+02:00 Emil Velikov : >> > On 15 June 2017 at 21:47, Robert Foss wrote: >> >> From: Tomeu

Re: [Mesa-dev] [PATCH 2/4] i965: Use I915_EXEC_NO_RELOC

On Mon, Jun 19, 2017 at 12:53 PM, Chris Wilson wrote: > Quoting Kenneth Graunke (2017-06-19 20:28:31) > > On Monday, June 19, 2017 3:06:48 AM PDT Chris Wilson wrote: > > > - if (target != batch->bo) > > > - add_exec_bo(batch, target); > > > + if (target !=

Re: [Mesa-dev] [PATCH 1/2] radeonsi: keep track of the sampler state for texture handles

On 06/19/2017 10:13 PM, Marek Olšák wrote: On Mon, Jun 19, 2017 at 10:06 PM, Marek Olšák wrote: On Mon, Jun 19, 2017 at 7:29 PM, Samuel Pitoiset wrote: Needed for updating all resident texture descriptors when dirty_tex_counter changes.

[Mesa-dev] [AppVeyor] mesa master #4673 failed

Build mesa 4673 failed Commit b539f6958e by Topi Pohjolainen on 1/11/2017 2:15 PM: i965/wm: Use stored hiz surface instead of creating copy\n\nNow the last user of intel_miptree_get_aux_isl_surf() is gone.\n\nReviewed-by: Jason Ekstrand

Re: [Mesa-dev] [PATCH 1/2] RFC i965: Bypass a couple of libraries for syscall on x84_64

On 20 June 2017 at 05:22, Chad Versace wrote: > On Mon 19 Jun 2017, Eric Engestrom wrote: >> On Monday, 2017-06-19 09:41:13 -0700, Jason Ekstrand wrote: >> > On Mon, Jun 19, 2017 at 7:43 AM, Chris Wilson >> > wrote: >> > > > > Just a cosmetic

[Mesa-dev] [PATCH] i965/cnl: Add l3 configuration for Cannonlake

From: Ben Widawsky V2 (Anuj): Squash the changes in one patch rebase on master. Address the review comments made by Francisco Jerez. Do the URB allocation per slice (not per bank). Signed-off-by: Ben Widawsky Signed-off-by: Anuj Phogat

[Mesa-dev] [PATCH V2 2/2] i965: Add a variable for size increment per bank in get_l3_way_size()

Adding min_size_increment_per_bank variable better explains the computation of L3 way size in the function. V2: Use const variable for min_size_increment_per_bank. Signed-off-by: Anuj Phogat Cc: Francisco Jerez --- src/intel/common/gen_l3_config.c

[Mesa-dev] [PATCH V2 1/2] i965: Fix broxton 2x6 l3 config

The new table added in this patch matches with the table in gfxspecs. We were programming the wrong values earlier. V2: Update the comment. Signed-off-by: Anuj Phogat Cc: Francisco Jerez Cc: "17.1" ---

Re: [Mesa-dev] [PATCH 2/2] radeonsi: support indirect indexing in INTERP_* opcodes

Reviewed-by: Marek Olšák Marek On Fri, Jun 16, 2017 at 10:37 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > The hardware doesn't support it, so we just interpolate all array elements > and then use indirect indexing on

Re: [Mesa-dev] [PATCH 2/4] i965: Use I915_EXEC_NO_RELOC

Quoting Kenneth Graunke (2017-06-19 20:28:31) > On Monday, June 19, 2017 3:06:48 AM PDT Chris Wilson wrote: > > - if (target != batch->bo) > > - add_exec_bo(batch, target); > > + if (target != batch->bo) { > > + unsigned int index = add_exec_bo(batch, target); > > + struct

Re: [Mesa-dev] [PATCH v1 2/7] etnaviv: Add return statement to etna_amode so compiler is happy

On Fri 16 Jun 2017, Christian Gmeiner wrote: > 2017-06-16 14:54 GMT+02:00 Emil Velikov : > > On 15 June 2017 at 21:47, Robert Foss wrote: > >> From: Tomeu Vizoso > >> > >> Signed-off-by: Robert Foss

Re: [Mesa-dev] [PATCH 4/4] egl/dri2: add image extension to swrast_core_extensions

On Thu 15 Jun 2017, Gurchetan Singh wrote: > Emil, would you be fine with leaving the image extension in dri2.c but still > adding it as a drisw extension?  That solution would look like: > > [1]https://patchwork.freedesktop.org/patch/154807/   Observations: -

Re: [Mesa-dev] [PATCH 1/1] gallium/hud: use double values for all graphs

On Sat, Jun 17, 2017 at 4:57 PM, Christoph Haag wrote: > This specifically helps the fps graph. It calculates the fps like this: > (uint64_t)info->frames * 100 / (double)(now - info->last_time); > The timings when query_new_value() are called will vary, so fps

Re: [Mesa-dev] [PATCH] radeonsi: use the correct LLVMTargetMachineRef in si_build_shader_variant

Reviewed-by: Marek Olšák Marek On Mon, Jun 19, 2017 at 1:40 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > si_build_shader_variant can actually be called directly from one of > normal-priority compiler threads. In that

Re: [Mesa-dev] [PATCH 2/4] i965: Use I915_EXEC_NO_RELOC

On Monday, June 19, 2017 3:06:48 AM PDT Chris Wilson wrote: > If we correctly fill the batch with the right relocation value, and that > matches the expected location of the object, we can then tell the kernel > it can forgo checking each individual relocation by only checking > whether the object

Re: [Mesa-dev] [PATCH 1/2] RFC i965: Bypass a couple of libraries for syscall on x84_64

On Mon 19 Jun 2017, Eric Engestrom wrote: > On Monday, 2017-06-19 09:41:13 -0700, Jason Ekstrand wrote: > > On Mon, Jun 19, 2017 at 7:43 AM, Chris Wilson > > wrote: > > > > > Just a cosmetic improvement, but quite straightforward. > > > > I think it's a bit hard to call

Re: [Mesa-dev] [PATCH 18/18] i965: Convert WM_STATE to genxml on gen4-5.

On Mon, Jun 19, 2017 at 11:17 AM, Rafael Antognolli wrote: > On Mon, Jun 19, 2017 at 09:46:30AM -0700, Kristian Høgsberg wrote: >> On Fri, Jun 16, 2017 at 4:31 PM, Rafael Antognolli >> wrote: >> > The code doesn't get exactly a lot

Re: [Mesa-dev] [PATCH] anv: Fix L3 cache programming on Bay Trail

On Mon, Jun 19, 2017 at 11:21 AM, Francisco Jerez wrote: > Jonas Kulla writes: > > > Valid values for URBAllocation start at 32, so substract that > > before programming the register. > > > > This was missed when porting from the GL driver. > >

[Mesa-dev] [Bug 101498] Graphical glitches when updating window content on screen

https://bugs.freedesktop.org/show_bug.cgi?id=101498 --- Comment #1 from Darius Spitznagel --- (In reply to Apurv from comment #0) > This issue has been encountered on the following distributions: > 1. Fedora 25 - Gnome (Wayland) >kernel: Linux x86_64 4.8.6 >

[Mesa-dev] [PATCH] winsys/amdgpu: fix a deadlock when waiting for submission_in_progress

From: Marek Olšák First this happens: 1) amdgpu_cs_flush (lock bo_fence_lock) -> amdgpu_add_fence_dependency -> os_wait_until_zero (wait for submission_in_progress) - WAITING 2) amdgpu_bo_create -> pb_cache_reclaim_buffer (lock pb_cache::mutex) ->

Re: [Mesa-dev] [PATCH v2 00/13] i965: Add performance query OA support on Gen 8 & 9

On Friday, June 16, 2017 8:32:22 AM PDT Lionel Landwerlin wrote: > Hi, > > Here is a v2 following some comments by Ken. Some patches already have > a rb-by/ack-by. > > Here is the list that needs looking at : 1, 2, 3, 4, 5 & 8. > > The list will probably filter some of the big patches, you can

Re: [Mesa-dev] [PATCH] i965: Resolve framebuffers before signaling the fence

On Mon 12 Jun 2017, Chris Wilson wrote: > From KHR_fence_sync: > > When the condition of the sync object is satisfied by the fence > command, the sync is signaled by the associated client API context, > causing any eglClientWaitSyncKHR commands (see below) blocking on >to unblock. The

Re: [Mesa-dev] [PATCH] anv: Fix L3 cache programming on Bay Trail

Jonas Kulla writes: > Valid values for URBAllocation start at 32, so substract that > before programming the register. > > This was missed when porting from the GL driver. Reviewed-by: Francisco Jerez > --- > src/intel/vulkan/genX_cmd_buffer.c | 2

Re: [Mesa-dev] egl/android: fence_fd being forced to -1

On Thu 15 Jun 2017, Eric Engestrom wrote: > On Thursday, 2017-06-15 16:17:20 -0400, Rob Clark wrote: > > On Thu, Jun 15, 2017 at 1:17 PM, Tapani Pälli > > wrote: > > > On 06/15/2017 07:57 PM, Rob Clark wrote: > > > > > > On Thu, Jun 15, 2017 at 12:04 PM, Tapani Pälli

Re: [Mesa-dev] [RFC PATCH] dri3: Sync after buffer swaps with glXSwapBuffers

On 06/19/2017 07:26 PM, Eric Anholt wrote: Thomas Hellstrom writes: Applications calling glXSwapBuffers should be able to expect that any X rendering submitted after the call to glXSwapBuffers returns should be ordered with respect to the glXSwapBuffers call. (For

Re: [Mesa-dev] [PATCH 18/18] i965: Convert WM_STATE to genxml on gen4-5.

On Mon, Jun 19, 2017 at 09:46:30AM -0700, Kristian Høgsberg wrote: > On Fri, Jun 16, 2017 at 4:31 PM, Rafael Antognolli > wrote: > > The code doesn't get exactly a lot simpler but at least it is in a single > > place, and we delete more than we add. > > Another good

Re: [Mesa-dev] [PATCH 12/18] i965: Convert CC state on gen4-5 to genxml.

On Sat, Jun 17, 2017 at 11:31:51AM -0700, Kenneth Graunke wrote: > On Friday, June 16, 2017 4:31:25 PM PDT Rafael Antognolli wrote: > > Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the > > color calc struct, and then manually update the rest. > > > > Signed-off-by: Rafael

Re: [Mesa-dev] [RFC PATCH] dri3: Sync after buffer swaps with glXSwapBuffers

On 06/19/2017 07:44 PM, Thomas Hellstrom wrote: On 06/19/2017 07:26 PM, Eric Anholt wrote: Thomas Hellstrom writes: Applications calling glXSwapBuffers should be able to expect that any X rendering submitted after the call to glXSwapBuffers returns should be ordered

[Mesa-dev] [PATCH] anv: Fix L3 cache programming on Bay Trail

Valid values for URBAllocation start at 32, so substract that before programming the register. This was missed when porting from the GL driver. --- src/intel/vulkan/genX_cmd_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c

Re: [Mesa-dev] [PATCH 1/2] RFC i965: Bypass a couple of libraries for syscall on x84_64

On Monday, 2017-06-19 09:41:13 -0700, Jason Ekstrand wrote: > On Mon, Jun 19, 2017 at 7:43 AM, Chris Wilson > wrote: > > > > Just a cosmetic improvement, but quite straightforward. > > I think it's a bit hard to call replacing a standard library function with > inline

[Mesa-dev] [PATCH 1/2] radeonsi: keep track of the sampler state for texture handles

Needed for updating all resident texture descriptors when dirty_tex_counter changes. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/radeonsi/si_descriptors.c | 12 +++- src/gallium/drivers/radeonsi/si_pipe.h| 1 + 2 files changed, 8

[Mesa-dev] [PATCH 2/2] radeonsi: update all resident texture descriptors when needed

To avoid useless DCC fetches when DCC is disabled, descriptors have to be updated in order to reflect this change. This is quite similar to how we update descriptors of bound textures. As a side effect, this should also prevent VM faults when bindless textures are invalidated, because the VA in

Re: [Mesa-dev] [RFC PATCH] dri3: Sync after buffer swaps with glXSwapBuffers

Thomas Hellstrom writes: > Applications calling glXSwapBuffers should be able to expect that any X > rendering submitted after the call to glXSwapBuffers returns should be ordered > with respect to the glXSwapBuffers call. (For example piglit reading out from > a window).

Re: [Mesa-dev] [PATCH 18/18] i965: Convert WM_STATE to genxml on gen4-5.

On Fri, Jun 16, 2017 at 4:31 PM, Rafael Antognolli wrote: > The code doesn't get exactly a lot simpler but at least it is in a single > place, and we delete more than we add. Another good point is that you get rid of struct brw_wm_unit_state which was a third

Re: [Mesa-dev] [PATCH 00/30] i965: Add support for I915_FORMAT_MOD_Y_TILED_CCS

On Mon, Jun 19, 2017 at 5:49 AM, Eero Tamminen wrote: > Hi, > > I run this on few GEN9 machines and SynMark v7 DeferredAA test improved > ~3%, so it seems multisample fast-clears do help. :-) > Thanks! I'll add that to the commit message on patch 5. --Jason > >

Re: [Mesa-dev] [PATCH 1/2] RFC i965: Bypass a couple of libraries for syscall on x84_64

On Mon, Jun 19, 2017 at 7:43 AM, Chris Wilson wrote: > Quoting Eric Engestrom (2017-06-19 15:30:46) > > On Monday, 2017-06-19 13:02:11 +0100, Chris Wilson wrote: > > > Quoting Emil Velikov (2017-06-19 12:43:42) > > > > Hi Chris, > > > > > > > > On 19 June 2017 at 12:32,

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