[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #21 from Thomas Crider --- Can confirm @Samuel Pitoiset v2 of that llvm patch fixes the face issue! Just got around to testing it today, working well -- You are receiving this mail because: You are the QA Contact for the bug. You a

[Mesa-dev] [PATCH 0/5] anv: Add a NIR cache

This patch series adds a simple NIR shader cache that sits right after spirv_to_nir and brw_preprocess_nir and before linking. This should help alleviate some of the added overhead of link-time optimization since most of the NIR-level optimization is now cached prior to linking. I have no numbers

[Mesa-dev] [PATCH 5/5] anv/pipeline: Cache the pre-lowered NIR

This adds a second level of caching for the pre-lowered NIR that's only based off of the shader module, entrypoint and specialization constants. This is enough for spirv_to_nir as well as our first round of lowering and optimization. Caching at this level should allow for faster shader recompiles

[Mesa-dev] [PATCH 2/5] anv/pipeline: Hash shader modules and spec constants separately

The stuff hashed by anv_pipeline_hash_shader is exactly the inputs to anv_shader_compile_to_nir so it can be used for NIR caching. --- src/intel/vulkan/anv_pipeline.c | 54 - 1 file changed, 39 insertions(+), 15 deletions(-) diff --git a/src/intel/vulkan/anv_pipeli

[Mesa-dev] [PATCH 1/5] anv/pipeline: Move wpos and input attachment lowering to lower_nir

This lets us make anv_pipeline_compile_to_nir take a device instead of a pipeline. --- src/intel/vulkan/anv_pipeline.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index be05c11f45d..4e3ae

[Mesa-dev] [PATCH 3/5] compiler/types: Serialize/deserialize subpass input types correctly

They have glsl_sampler_dim enum values of 8 and 9 which don't work when you & them with 0x7. Fortunately, we have plenty of bits. --- src/compiler/glsl_types.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp index

[Mesa-dev] [PATCH 4/5] anv/pipeline_cache: Add support for caching NIR

--- src/intel/vulkan/anv_pipeline_cache.c | 100 ++ src/intel/vulkan/anv_private.h| 18 + 2 files changed, 118 insertions(+) diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c index 3efa427279d..2add9e06b20 100644 --- a

[Mesa-dev] [PATCH] radv: Allow physical device interfaces to be included in device extensions

According to the Vulkan spec: "Vulkan 1.0 initially required all new physical-device-level extension functionality to be structured within an instance extension. In order to avoid using an instance extension, which often requires loader support, physical-device-level extension functionality may

[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object

https://bugs.freedesktop.org/show_bug.cgi?id=105731 Marcel Heinz changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|FIXED

[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object

https://bugs.freedesktop.org/show_bug.cgi?id=105731 Marcel Heinz changed: What|Removed |Added Attachment #142005|updated reproduced code |updated reproducer code descripti

[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object

https://bugs.freedesktop.org/show_bug.cgi?id=105731 --- Comment #5 from Marcel Heinz --- Created attachment 142005 --> https://bugs.freedesktop.org/attachment.cgi?id=142005&action=edit updated reproduced code -- You are receiving this mail because: You are the assignee for the bug.___

[Mesa-dev] [Bug 107765] [regression] Batman Arkham City crashes with DXVK under wine

https://bugs.freedesktop.org/show_bug.cgi?id=107765 --- Comment #5 from farmboy0+freedesk...@googlemail.com --- With the patch applied to mesa git wine crashes now with: Unhandled exception: assertion failed in 32-bit code (0xf7f99b09). Register dump: CS:0023 SS:002b DS:002b ES:002b FS:0063 GS:00

[Mesa-dev] [PATCH v2 25/32] intel/isl: Add a max_miptail_levels field to isl_tile_info

--- src/intel/isl/isl.c | 5 + src/intel/isl/isl.h | 7 +++ 2 files changed, 12 insertions(+) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 4a8380ad540..3657b11ee00 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -181,6 +181,7 @@ isl_tiling_get_info(enum isl_t

[Mesa-dev] [PATCH v2 32/32] anv/image: Wrap an error return in vk_error

--- src/intel/vulkan/anv_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 93f42dc98f9..17727695001 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -362,7 +362,7 @@ make_surf

[Mesa-dev] [PATCH v2 27/32] intel/isl: Add units to view dimensions in isl_surf_get_uncompressed_surf

--- src/intel/isl/isl.c | 27 ++- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index c86390bf851..88de1407375 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2648,13 +2648,13 @@ isl_surf_get_uncompr

[Mesa-dev] [PATCH v2 30/32] intel/isl: Start using miptails

This commit adds the code for choosing where to start the miptail and enables miptails by default unless the client driver passes info->min_miptail_start_level >= info->levels. --- src/intel/isl/isl.c | 165 ++-- 1 file changed, 161 insertions(+), 4 deletion

[Mesa-dev] [PATCH v2 29/32] intel/isl: Disallow CCS on 3D surfaces with miptails

--- src/intel/isl/isl.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index df4fb94a6fe..2513d2e73d1 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2006,6 +2006,25 @@ isl_surf_get_ccs_surf(const struct isl_device

[Mesa-dev] [PATCH v2 26/32] intel/isl: Add support for computing offsets with miptails

Unfortunately, there is no nice way to calculate miptail offsets in closed form. Instead, we just copy the tables from the PRM directly verbatim. --- src/intel/isl/isl.c | 217 +++- 1 file changed, 213 insertions(+), 4 deletions(-) diff --git a/src/intel/i

[Mesa-dev] [PATCH v2 31/32] anv: Enable support for Yf and Ys tiled images

--- src/intel/vulkan/anv_device.c | 6 -- src/intel/vulkan/anv_image.c | 12 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 6a24d1086d8..7f7778fd81d 100644 --- a/src/intel/vulkan/anv_device.c ++

[Mesa-dev] [PATCH v2 28/32] intel/isl: Support miptails in isl_surf_get_uncompressed_surf

--- src/intel/isl/isl.c | 45 +++-- 1 file changed, 35 insertions(+), 10 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 88de1407375..df4fb94a6fe 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2657,11 +2657,22 @@ is

[Mesa-dev] [PATCH v2 24/32] intel/isl: Add initial data-structure support for miptails

This commit just adds a miptail start field to isl_surf and wires it up in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code. We also add a minimum miptail LOD so that client drivers have a knob to control the miptails a bit. --- src/intel/isl/isl.c| 1 + src/intel/isl/isl.h

[Mesa-dev] [PATCH v2 22/32] intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl_emit_depth_stencil.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 9cf5a476687..b07da781be8 100644 --- a/src/int

[Mesa-dev] [PATCH v2 21/32] intel/isl: Support Yf/Ys tiling in surf_fill_state

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl_surface_state.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 26cb2a87c55..abd4767acd7 100644 --- a/src/intel/isl/isl_surfa

[Mesa-dev] [PATCH v2 20/32] intel/isl: Don't compute image tiling data for Yf/Ys tiling

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl_storage_image.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/isl/isl_storage_image.c b/src/intel/isl/isl_storage_image.c index d9c45505a14..93805bb98ea 100644 --- a/src/intel/isl/isl_storage_image.c +++ b/src/intel

[Mesa-dev] [PATCH v2 19/32] intel/isl: Support Ys and Yf in isl_surf_get_uncompressed_surf

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 47 - 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index b8af8ad1176..3d0741bc207 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl

[Mesa-dev] [PATCH v2 23/32] intel/isl: Allow Yf and Ys tiling

They are both implemented in ISL now. Instead of disabling them in ISL, we disable them in the two dirvers. Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl_gen7.c | 8 src/intel/vulkan/anv_image.c | 3 +++ src/mesa/drivers/dri/i965/intel_mipmap

[Mesa-dev] [PATCH v2 18/32] intel/blorp: Use isl_surf_get_uncompressed_surf

Reviewed-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 41 ++-- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index dd43b8643b9..170c2e66106 100644 --- a/src/intel/blorp/blorp_b

[Mesa-dev] [PATCH v2 17/32] intel/blorp: Adjust the compressed copy rectangle before convert_to_single_slice

It doesn't matter for the actual copy rectangle and this makes the asserts a bit nicer as we don't need to bother with the intratile offsets because there aren't any yet. --- src/intel/blorp/blorp_blit.c | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --

[Mesa-dev] [PATCH v2 14/32] intel/isl: Fill out the correct phys_total_extent for Ys/Yf

With these tilings, everything is aligned to a tile and the tiled surface size calculations will handle the array stride for us. We need to provide an accurate 4D size so that 3D and multisampled images get tiled correctly. Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 51

[Mesa-dev] [PATCH v2 15/32] intel/isl: Support Yf/Ys in isl_surf_get_image_offset_sa

All that's really needed here is to handle the array offsetting by using an Z or array offset instead of the Y offset. Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 45 ++--- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/src/int

[Mesa-dev] [PATCH v2 16/32] intel/isl: Pull the uncompressed surface view code from anv

This adds a helper isl_surf_get_uncompressed_surf for creating a surface which provides an uncompressed view into a compressed surface. The code is basically a direct port of the uncompressed surface code from the Vulkan driver which, in turn, was a port from BLORP. Reviewed-by: Topi Pohjolainen

[Mesa-dev] [PATCH v2 12/32] intel/isl: Disallow Yf and Ys for 1D depth surfaces

--- src/intel/isl/isl_gen7.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index f6f7e1ba7dc..fe420e4fbd8 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -217,6 +217,15 @@ isl_gen6_filter_tiling(const struct

[Mesa-dev] [PATCH v2 13/32] intel/isl: Use the depth field of phys_level0_sa for GEN4_2D 3D surfaces

This makes things a tiny bit stickier in isl_calc_phys_total_extent_el but will be worth it when we enable Yf and Ys. Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 18 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++-- 2 files cha

[Mesa-dev] [PATCH v2 09/32] intel/isl: Implement correct tile size calculations for Ys/Yf

The tile size calculations use a clever bit of math to make them short and simple. We add unit tests to assert that they identically match the tables in the PRM. --- src/intel/Makefile.isl.am | 9 +- src/intel/isl/isl.c | 66 ++- src/intel/isl/meson.bu

[Mesa-dev] [PATCH v2 11/32] intel/isl: Use ISL_DIM_LAYOUT_GEN9_1D for Yf/Ys

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 21d2babdb56..58091795a26 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -696,8 +696,10 @@ isl_surf_choose_dim

[Mesa-dev] [PATCH v2 07/32] intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_GEN9_Yf/s

The Yf and Ys tilings change a bit between gen9 and gen10 so we have to be able to distinguish between them. --- src/intel/isl/isl.c | 12 ++-- src/intel/isl/isl.h | 16 src/intel/isl/isl_drm.c | 4 ++-- src/intel/isl/isl_gen7.c

[Mesa-dev] [PATCH v2 06/32] intel/isl: Expose isl_tiling_get_info

While we're moving things around, we also add dim and sample count parameters. They are not used yet but the layout of Yf and Ys tiles are dependent on these parameters. Reviewed-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 5 +++-- src/intel/isl/isl.c|

[Mesa-dev] [PATCH v2 10/32] intel/isl: Use the tile size for computing standard Y alignments

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl_gen9.c | 85 +--- 1 file changed, 9 insertions(+), 76 deletions(-) diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c index 8e460430a1c..f9d391ab67d 100644 --- a/src/intel/isl/isl_gen9.c +++ b/s

[Mesa-dev] [PATCH v2 08/32] intel/isl: Add gen10 variants of Yf and Ys tiling

--- src/intel/isl/isl.c | 9 +++-- src/intel/isl/isl.h | 12 ++-- src/intel/isl/isl_drm.c | 2 ++ src/intel/isl/isl_gen7.c | 8 +++- src/intel/isl/isl_surface_state.c | 2 ++ 5 files changed, 28 insertions(+), 5 deletions(-) diff

[Mesa-dev] [PATCH v2 05/32] intel/isl: Use a 4D physical total extent for size calculations

With Yf and Ys tiling, everything is actually four dimensional because we can have multiple depth or multisampled array slices in the same tile. This commit just enhances the calculations so they can handle it. Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 73 +

[Mesa-dev] [PATCH v2 04/32] intel/isl: Make tile logical extents four dimensional

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 36 src/intel/isl/isl.h | 2 +- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index a53fbf3da02..6bc96e86cb5 100644 --- a/src/intel/isl/isl.c

[Mesa-dev] [PATCH v2 03/32] intel/isl: Make the offset helpers four dimensional

We need to do this in order to handle Yf and Ys tiling because they use a four-dimensional tile instead of laying everything out in two dimensions. Reviewed-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 8 ++- src/intel/isl/isl.c | 52 +++

[Mesa-dev] [PATCH v2 00/32] intel/isl: Add support for Yf and Ys texturing

This series adds support for the Yf and Ys formats. I've had it kicking around for a while but got bogged down debugging a CNL miptail issue. I decided yesterday to give it a rebase and I'm sending it out again. This time, Ys actually works thanks to anv's ability to enforce 64K alignments of bu

[Mesa-dev] [PATCH v2 02/32] intel/blorp: Use isl_surf_get_image_offset_B_tile_el in ccs_ambiguate

Reviewed-by: Topi Pohjolainen --- src/intel/blorp/blorp_clear.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 5b575dccc22..dd974df35d2 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp

[Mesa-dev] [PATCH v2 01/32] intel/isl: Add a isl_surf_get_image_offset_B_tile_el helper

Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 45 - src/intel/isl/isl.h | 20 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 359293cfcb2..ffcede1ef61 100644

Re: [Mesa-dev] [PATCH 1/7] intel/ir: Don't allow allocating zero registers

Patches 1 through 5 and 7 are Reviewed-by: Ian Romanick Patch 6 is Acked-by: Ian Romanick Someone more familiar with those bits should look at patch 6. On 10/11/2018 02:32 PM, Jason Ekstrand wrote: > This simple check helps catch bugs early that can end up propagating > into later stages of

[Mesa-dev] [PATCH v5 5/5] radeonsi: Enable adaptive_sync by default for radeon

It's better to let most applications make use of adaptive sync by default. Problematic applications can be placed on the blacklist or the user can manually disable the feature. Signed-off-by: Nicholas Kazlauskas --- src/gallium/drivers/radeonsi/driinfo_radeonsi.h | 4 1 file changed, 4 inse

[Mesa-dev] [PATCH v5 4/5] loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property

The DDX driver can be notified of adaptive sync suitability by flagging the application's window with the _VARIABLE_REFRESH property. This property is set on the first swap the application performs when adaptive_sync is set to true in the drirc. It's performed here instead of when the loader is i

[Mesa-dev] [PATCH v5 3/5] drirc: Initial blacklist for adaptive sync

Applications that don't present at a predictable rate (ie. not games) shouldn't have adapative sync enabled. This list covers some of the common desktop compositors, web browsers and video players. Signed-off-by: Nicholas Kazlauskas --- src/util/00-mesa-defaults.conf | 82 +++

[Mesa-dev] [PATCH v5 0/5] Mesa integration for DRM variable refresh rate API

These patches are part of a proposed new interface for supporting variable refresh rate via DRM properties. It adds a new option for supporting adaptive sync to drirc along with the implementation of notifying the window manager/DDX of the support via a window property. The option is enabled b

[Mesa-dev] [PATCH v5 1/5] util: Get program name based on path when possible

Some programs start with the path and command line arguments in argv[0] (program_invocation_name). Chromium is an example of an application using mesa that does this. This tries to query the real path for the symbolic link /proc/self/exe to find the program name instead. It only uses the realpath

[Mesa-dev] [PATCH v5 2/5] util: Add adaptive_sync driconf option

This option lets the user decide whether mesa should notify the window manager / DDX driver that the current application is adaptive sync capable. It's off by default. Signed-off-by: Nicholas Kazlauskas --- src/util/xmlpool/t_options.h | 5 + 1 file changed, 5 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH 1/3] appveyor: Update to MSVC 2017.

That's what we (and I suppose most people out there) are using now. --- appveyor.yml | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/appveyor.yml b/appveyor.yml index 73be3c57df8..66f8354bd66 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -35,9 +35,9 @@ clone_dept

[Mesa-dev] [PATCH 3/3] appveyor: Cache pip's cache files.

It should speed up the Python packages installation. --- appveyor.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/appveyor.yml b/appveyor.yml index a4e942c14ca..ccb84fd3403 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -33,7 +33,9 @@ branches: # - https://www.appveyor.com/blog/2014/06

[Mesa-dev] [PATCH 2/3] appveyor: Update to newer Mako/winflexbison versions.

As that's what most people are bound to use. --- appveyor.yml | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/appveyor.yml b/appveyor.yml index 66f8354bd66..a4e942c14ca 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -34,7 +34,7 @@ branches: clone_depth: 100 cache:

[Mesa-dev] [PATCH] radv: drop old DXVK GPU hangs workaround by removing amdgpu-skip-threshold

Tested with Hellblade and LLVM 6, 7 and master, no hangs so far. Maybe some NIR changes fixed the issue as a side effect. This should reduce code size a little bit. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff -

[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #20 from Samuel Pitoiset --- Faces issue fixed with the possible patch reported here https://bugs.llvm.org/show_bug.cgi?id=37744#c2 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact fo

[Mesa-dev] [Bug 108113] [vulkancts] r32g32b32 transfer operations not implemented

https://bugs.freedesktop.org/show_bug.cgi?id=108113 Samuel Pitoiset changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH] anv/android: we need git_sha1.h in include paths

On Thu, 11 Oct 2018 at 18:35, Tapani Pälli wrote: > On 10/11/18 2:22 PM, Eric Engestrom wrote: > > On Thursday, 2018-10-11 08:16:52 +0300, Tapani Pälli wrote: > >> ping ... this fixes Android build as anv_device.c started to include > >> "git_sha1.h" but build does not currently pass the path to t

Re: [Mesa-dev] [PATCH libdrm] xf86drmHash: remove redundant zero init

On Fri, 12 Oct 2018 at 00:18, Rob Clark wrote: > > From: Rob Clark > > drmMalloc() is already calloc() > > Signed-off-by: Rob Clark For the patch Reviewed-by: Emil Velikov > --- > Small micro-optimization that I noticed while doing some perf work.. > I should probably look at promoting amdgpu'

Re: [Mesa-dev] [PATCH v4 5/5] loader/dri3: Enable adaptive sync via _VARIABLE_REFRESH property

On 10/12/2018 05:25 AM, Michel Dänzer wrote: On 2018-10-11 6:43 p.m., Nicholas Kazlauskas wrote: The DDX driver can be notified of adaptive sync suitability by flagging the application's window with the _VARIABLE_REFRESH property. This property is set on the first swap the application performs

Re: [Mesa-dev] [PATCH] radv: do not support blitting surfaces for R32G32B32 formats

Reviewed-by: Bas Nieuwenhuizen On Fri, Oct 12, 2018 at 2:03 PM Samuel Pitoiset wrote: > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113 > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_formats.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/src/amd/

[Mesa-dev] [PATCH] glsl/linker: validate attribute aliasing before optimizations

Patch does a 'dry run' of assign_attribute_or_color_locations before optimizations to catch cases where we have aliasing of unused attributes which is forbidden by the GLSL ES 3.x specifications. We need to run this pass before unused attributes may be removed and with attribute binding informatio

[Mesa-dev] [PATCH] radv: do not support blitting surfaces for R32G32B32 formats

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113 Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_formats.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index a7aa819e2b..59bc46d2fc 100644 --- a/src/amd

Re: [Mesa-dev] [PATCH libdrm] xf86drmHash: remove redundant zero init

On Thursday, 2018-10-11 19:18:10 -0400, mesa-dev-boun...@lists.freedesktop.org wrote: > From: Rob Clark > > drmMalloc() is already calloc() Sounds very much like an implementation detail, but everything relies on it already, so... Reviewed-by: Eric Engestrom > > Signed-off-by: Rob Clark >

[Mesa-dev] [Bug 107765] [regression] Batman Arkham City crashes with DXVK under wine

https://bugs.freedesktop.org/show_bug.cgi?id=107765 --- Comment #4 from Samuel Pitoiset --- Does this branch help ? https://cgit.freedesktop.org/~hakzsam/mesa/log/?h=radv_r32g32b32_btoi -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.

Re: [Mesa-dev] [PATCH v4 5/5] loader/dri3: Enable adaptive sync via _VARIABLE_REFRESH property

On 2018-10-11 6:43 p.m., Nicholas Kazlauskas wrote: > The DDX driver can be notified of adaptive sync suitability by > flagging the application's window with the _VARIABLE_REFRESH property. > > This property is set on the first swap the application performs > when adaptive_sync_enable is set to tr

Re: [Mesa-dev] [PATCH] loader/dri3: Also wait for front buffer fence if we triggered it

On 2018-10-11 10:40 p.m., Mike Lothian wrote: > I'm still seeing weird graphical corruptions in chrome and sometimes when > playing video > > It's especially noticeable when in inbox.google.com > > I might be suffering from a different issue however If reverting aefac10fecc9 "loader/dri3: Only w

Re: [Mesa-dev] [PATCH] i965: consider a 'base level' when calculating width0, height0, depth0

Hi, Thanks for your advices. I will be on vacation from 13.10.2018 till 20.10.2018 so I will try to do it after vacation. Thanks, Andrii. On Thu, Oct 11, 2018 at 6:10 PM Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Thu, Oct 11, 2018 at 03:12:08PM +0300, andrey simiklit wrote: >

Re: [Mesa-dev] [PATCH] r600/sb: Fix constant-logical-operand warning.

On Fri, 12 Oct 2018 at 07:16, Vinson Lee wrote: > > sb/sb_bc_parser.cpp:620:27: warning: use of logical '&&' with constant > operand [-Wconstant-logical-operand] > if (cf->bc.op_ptr->flags && FF_GDS) > ^ ~~ > sb/sb_bc_parser.cpp:620:27: note: use '&'