https://bugs.freedesktop.org/show_bug.cgi?id=108933
--- Comment #2 from network...@rkmail.ru ---
Created attachment 142739
--> https://bugs.freedesktop.org/attachment.cgi?id=142739=edit
valgrind log
(In reply to iive from comment #1)
> 1. See if changing your locale has effect on the crash.
On 6/12/18 8:37, apinheiro wrote:
> On 5/12/18 16:55, Samuel Iglesias Gonsálvez wrote:
>> The remove_extra_rounding_modes() optimization will remove duplicated
>> rounding mode changes.
>>
>> Signed-off-by: Samuel Iglesias Gonsálvez
>> ---
>> src/intel/compiler/brw_fs.cpp | 9 +++--
>> 1
On 5/12/18 16:55, Samuel Iglesias Gonsálvez wrote:
> The remove_extra_rounding_modes() optimization will remove duplicated
> rounding mode changes.
>
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/intel/compiler/brw_fs.cpp | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
https://bugs.freedesktop.org/show_bug.cgi?id=107991
--- Comment #18 from e88z4 ---
Hi Everyone,
I can confirm that this bug is still affecting amdgpu driver. I ran yuzu-canary
built playing Super Mario Odyssey. The bug can be reproduced very consistent at
the beginning of the game when Mario
On Wed, Dec 5, 2018 at 7:05 PM Jordan Justen
wrote:
> On 2018-12-05 15:44:18, Jason Ekstrand wrote:
> > On Wed, Dec 5, 2018 at 5:32 PM Jordan Justen
> > wrote:
> > > -Mailing Patches
> > > +Submitting Patches
> > >
> > >
> > > -Patches should be sent to the mesa-dev mailing list for review:
>
https://bugs.freedesktop.org/show_bug.cgi?id=108933
--- Comment #1 from i...@yahoo.com ---
Mesa developers need to be able to reproduce the problem and they are not going
to install UT to debug this. So we'll have to do a bit more investigating on
this one.
There are few things for you to try:
On 2018-12-05 15:44:18, Jason Ekstrand wrote:
> On Wed, Dec 5, 2018 at 5:32 PM Jordan Justen
> wrote:
> > -Mailing Patches
> > +Submitting Patches
> >
> >
> > -Patches should be sent to the mesa-dev mailing list for review:
> > +Patches may be submitted to the Mesa project by
> > +email or with
These look good to me. I don't remember whether or not that kind of
initializer makes MSCV happy, but meh.
Reviewed-by: Ian Romanick
On 12/05/2018 01:13 PM, Jason Ekstrand wrote:
> They occur when building with clang:
>
> [1/40] Compiling C object
>
On Wed, Dec 5, 2018 at 5:32 PM Jordan Justen
wrote:
> This documents a process for using GitLab Merge Requests as an second
> way to submit code changes for Mesa. Only one of the two methods is
> allowed for each patch series.
>
> We will *not* require all patches to be emailed. Some code
This documents a process for using GitLab Merge Requests as an second
way to submit code changes for Mesa. Only one of the two methods is
allowed for each patch series.
We will *not* require all patches to be emailed. Some code changes may
be reviewed and merged without any discussion on the
This ends up refactoring visit_load_buffer() a little.
Fixes: 7e7ee826982 ('ac: add support for 16bit buffer loads')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108114
Signed-off-by: Rhys Perry
---
Unfortunately I was not able to test this patch on a Polaris due to hardware
issues. It
The sixth release candidate for Mesa 18.3.0 is now available.
With no more bugs blocking the release, this will be the final release
candidate and Mesa 18.3.0 final is expected tomorrow around 18:00 GMT.
Alex Smith (1):
radv: Flush before vkCmdWriteTimestamp() if needed
Bas Nieuwenhuizen
They occur when building with clang:
[1/40] Compiling C object
'src/compiler/nir/s...piler@nir@@nir@sta/.._spirv_vtn_glsl450.c.o'.
../src/compiler/spirv/vtn_glsl450.c:845:39: warning: implicit conversion from
enumeration type 'SpvOp' (aka 'enum SpvOp_') to different enumeration type
'enum
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nouveau_buffer.c | 20 +++---
src/gallium/drivers/nouveau/nouveau_context.c | 33 -
src/gallium/drivers/nouveau/nouveau_context.h | 17 ++---
src/gallium/drivers/nouveau/nouveau_fence.h | 5 +-
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 4 ++--
src/gallium/drivers/nouveau/nv50/nv50_screen.h | 1 -
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 ++--
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 -
4 files changed, 4 insertions(+), 6
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nouveau_context.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nouveau_context.h
b/src/gallium/drivers/nouveau/nouveau_context.h
index c3bbb11bd60..38c19790ec3 100644
---
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 +
.../drivers/nouveau/codegen/nv50_ir_print.cpp | 67 ---
.../drivers/nouveau/codegen/nv50_ir_util.h| 1 +
3 files changed, 46 insertions(+), 23 deletions(-)
diff --git
prepareation for fixing our multi context issues.
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 ++--
src/gallium/drivers/nouveau/nv30/nv30_draw.c | 4 ++--
src/gallium/drivers/nouveau/nv50/nv50_compute.c | 4 ++--
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nouveau_buffer.c | 37 +++
src/gallium/drivers/nouveau/nouveau_buffer.h | 2 +-
src/gallium/drivers/nouveau/nouveau_fence.c | 96 +--
src/gallium/drivers/nouveau/nouveau_fence.h | 38 ++--
Currently only fully implemented for nvc0.
General approach is to make a more stricter use of the *_context object and
give each contexts its own pushbuffer, nouveau_client and fence list. This
allows us to do some screen operations with the context pushbuf as well (like
resizing the text area or
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/Makefile.sources | 1 +
src/gallium/drivers/nouveau/meson.build | 1 +
src/gallium/drivers/nouveau/nouveau_context.c | 19 +++
src/gallium/drivers/nouveau/nouveau_screen.c | 18 --
4 files
On 12/5/18 7:24 PM, Juan A. Suarez Romero wrote:
On Wed, 2018-12-05 at 09:52 +, Alex Smith wrote:
As done for vkCmdBeginQuery() already. Prevents timestamps from being
overwritten by previous vkCmdResetQueryPool() calls if the shader path
was used to do the reset.
Bugzilla:
I had a look, and this series is
Reviewed-by: Connor Abbott
I think I already reviewed at least part of your 1-bit-boolean series,
and had some feedback, but I'm done reviewing for today :)
On Fri, Nov 30, 2018 at 12:37 AM Jason Ekstrand wrote:
>
> This is mostly a re-send of my earlier series
All the current lowerings produce their result using a floating-point
multiply or add, so denorms should already be flushed (e.g.
nir_op_frcp), or they never produce a denorm (e.g. nir_op_ftrunc), so
I don't think this is necessary.
On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez
wrote:
On Mon, 3 Dec 2018 at 23:38, Matt Turner wrote:
>
> On Mon, Dec 3, 2018 at 8:12 AM Emil Velikov wrote:
> >
> > On Thu, 29 Nov 2018 at 23:54, Matt Turner wrote:
> > >
> > > This extension is not properly tested (testing for
> > > GL_ARB_fragment_shader_interlock is not sufficient), and since
On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez
wrote:
>
> According to VK_KHR_shader_float_controls:
>
> "Denormalized values obtained via unpacking an integer into a vector
> of values with smaller bit width and interpreting those values as
> floating-point numbers must: be flushed
On Wed, 2018-12-05 at 09:52 +, Alex Smith wrote:
> As done for vkCmdBeginQuery() already. Prevents timestamps from being
> overwritten by previous vkCmdResetQueryPool() calls if the shader path
> was used to do the reset.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108925
>
Why is this needed? In general, we shouldn't be relying on
optimization ordering for correctness. It probably just means one of
the optimizations is wrong, and you're working around that.
On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez
wrote:
>
> This would do constant folding and also
On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez
wrote:
>
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/compiler/nir/nir.h | 15 +++
> src/compiler/nir/nir_constant_expressions.py | 46 +---
> src/compiler/spirv/vtn_alu.c
This is not acceptable, since this will disable the optimization even
when it would otherwise be allowed. Either we need to mark everything
as precise if one of these execution modes are enabled, or we need to
disable this optimization only if the appropriate preserve-NaN-and-Inf
mode is set.
On
I sent a series last week which does almost everything Connor mentioned...
On December 5, 2018 12:12:50 Connor Abbott wrote:
This won't work, since this optimization in nir_opt_algebraic will undo it:
# For any float comparison operation, "cmp", if you have "a == a && a cmp b"
# then the "a
This won't work, since this optimization in nir_opt_algebraic will undo it:
# For any float comparison operation, "cmp", if you have "a == a && a cmp b"
# then the "a == a" is redundant because it's equivalent to "a is not NaN"
# and, if a is a NaN then the second comparison will fail anyway.
for
https://bugs.freedesktop.org/show_bug.cgi?id=108116
--- Comment #2 from Samuel Pitoiset ---
Created attachment 142734
--> https://bugs.freedesktop.org/attachment.cgi?id=142734=edit
deqp list v2
$ export RADV_DEBUG=nohiz,nodcc,nofastclears,zerovram
$ ./deqp-vk
https://bugs.freedesktop.org/show_bug.cgi?id=108116
--- Comment #1 from Samuel Pitoiset ---
Created attachment 142733
--> https://bugs.freedesktop.org/attachment.cgi?id=142733=edit
deqp list
$ ./deqp-vk
--deqp-caselist-file=/home/hakzsam/programming/cts_runner/pass_or_fail
Writing test log
On Wed, Dec 05, 2018 at 04:55:19PM +0100, Samuel Iglesias Gonsálvez wrote:
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/compiler/nir/nir_opt_constant_folding.c | 74 +++--
> 1 file changed, 68 insertions(+), 6 deletions(-)
>
> diff --git
On Tue, Dec 4, 2018 at 1:17 AM Iago Toral Quiroga wrote:
> ---
> src/compiler/spirv/vtn_glsl450.c | 36 +---
> 1 file changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/src/compiler/spirv/vtn_glsl450.c
> b/src/compiler/spirv/vtn_glsl450.c
> index
Given that other places call nir_eval_const_opcode(), and they'll be
broken unless they also flush denorms, it's probably a good idea to
move all this into nir_eval_const_opcode() itself.
On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez
wrote:
>
> Signed-off-by: Samuel Iglesias Gonsálvez
For the python bits:
Reviewed-by: Dylan Baker
Quoting Connor Abbott (2018-12-05 04:20:30)
> Before this commit, there were two copies of the algorithm: one in C,
> that we would use to figure out what bit-size to give the replacement
> expression, and one in Python, that emulated the C one and
https://bugs.freedesktop.org/show_bug.cgi?id=108742
--- Comment #2 from Samuel Pitoiset ---
Did you bisect?
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You are the QA Contact for the bug.
You are the assignee for the bug.___
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So my compiler doesn't want to show me warnings? That's something I
would need to fix up. Anyways,
Reviewed-by: Samuel Pitoiset
On 12/5/18 4:44 PM, Eric Engestrom wrote:
Added in 824cfc1ee5e0aba15b676 "radv: rework the TC-compat HTILE
hardware bug with COND_EXEC", but it is unused.
Hi Emil,
Yeah, that looks correct, Thanks!
On 12/5/18 4:22 PM, Emil Velikov wrote:
Hi guys
On Wed, 5 Dec 2018 at 10:49, Bas Nieuwenhuizen wrote:
Reviewed-by: Bas Nieuwenhuizen
On Wed, Dec 5, 2018 at 11:43 AM Samuel Pitoiset
wrote:
In case we are unlucky if the low part is 0x.
From: Kirill Burtsev
Currently we distinguish if the drawable is a window or pixmap by
checking xcb_present_select_input throws an error or not.
Yet, we don't always free the error state returned by xcb.
Cc: Kirill Burtsev
Cc: Boyan Ding
Fixes: 6bd9ba7d074 ("loader: Add dri3 helper")
https://bugs.freedesktop.org/show_bug.cgi?id=108914
--- Comment #16 from tempel.jul...@gmail.com ---
Looking fine now with mesa-git, thanks again!
--
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h | 15 +++
src/compiler/nir/nir_constant_expressions.py | 46 +---
src/compiler/spirv/vtn_alu.c | 16 ++-
3 files changed, 71 insertions(+), 6 deletions(-)
diff --git
This way, we can implement its support later if SPIR-V supports it.
Right now, the RTZ, RTNE support in SPIR-V in FPRoundingMode only
applies to f2f16 conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 22 +-
1 file changed, 21
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 32e0817ce02..18dcd92219c 100644
--- a/src/intel/compiler/brw_fs.cpp
+++
The denorm mode is set in the control register, no need to do something else.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index e745cc15fc5..21c3d371a63 100644
---
If we have (inf - inf) we should return NaN, not 0.0. Same for
(NaN - NaN) case.
Fixes tests in Vulkan CTS that produce such kind subtractions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opt_algebraic.py | 2 --
1 file changed, 2 deletions(-)
diff --git
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_lower_double_ops.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/compiler/nir/nir_lower_double_ops.c
b/src/compiler/nir/nir_lower_double_ops.c
index b3543bc6963..97b825d2fdb 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opt_constant_folding.c | 74 +++--
1 file changed, 68 insertions(+), 6 deletions(-)
diff --git a/src/compiler/nir/nir_opt_constant_folding.c
b/src/compiler/nir/nir_opt_constant_folding.c
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 0115648cbb0..69588f56968 100644
---
It adds round-towards-zero and round-to-nearest-even opcodes for
floating point conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 2 +-
src/compiler/nir/nir_opcodes_c.py | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
If x < 0 -> atan2(x, x) = -3*pi/4.
If x > 0 -> atan2(x, x) = pi/4.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index
If we have fsin or fcos trigonometric operations with constant values as inputs,
we will multiply the result by 0.7 in brw_nir_apply_trig_workarounds,
making the result wrong. Running nir_opt_constant_folding before, we will
calculate correctly the result for these trignometric ops.
Until now, it was using the floating point version of fmin, instead
of the double version.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_opcodes.py
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/shader_enums.h | 14 ++
src/compiler/shader_info.h| 3 +++
src/compiler/spirv/spirv_to_nir.c | 26 ++
3 files changed, 43 insertions(+)
diff --git a/src/compiler/shader_enums.h
We were returning 3*pi/4 when we should return 0.0 according to IEEE 754.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index d55e51adcbb..cadf9288ad9 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_extensions.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index 9ca42d998ef..d572df3c342 100644
--- a/src/intel/vulkan/anv_extensions.py
+++
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4 ---
src/intel/compiler/brw_eu_emit.c| 36 -
src/intel/compiler/brw_fs_generator.cpp | 13 +++--
src/intel/compiler/brw_fs_nir.cpp | 18 +++--
4 files
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_device.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 17b73c115cd..af07c7c831e 100644
--- a/src/intel/vulkan/anv_device.c
The remove_extra_rounding_modes() optimization will remove duplicated
rounding mode changes.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4
src/intel/compiler/brw_eu_defines.h | 10 ++
src/intel/compiler/brw_eu_emit.c| 26 +
src/intel/compiler/brw_fs_generator.cpp | 8 +++-
We need this function to emit code that setups the control register later with
the defined execution mode for the shader.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.h | 1 +
src/intel/compiler/brw_fs_visitor.cpp | 52 +++
2 files
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/half_float.c | 74 +++
src/util/half_float.h | 7
2 files changed, 81 insertions(+)
diff --git a/src/util/half_float.c b/src/util/half_float.c
index 63aec5c5c14..5fdcb20045b 100644
---
This would do constant folding and also flush to zero denorms operands before
the nir_opt_algebraic is executed.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_nir.c
According to VK_KHR_shader_float_controls:
"Denormalized values obtained via unpacking an integer into a vector
of values with smaller bit width and interpreting those values as
floating-point numbers must: be flushed to zero, unless the entry point
is declared with the code:DenormPreserve
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/Makefile.sources | 2 +
src/util/double.c | 197 ++
src/util/double.h | 46 +
src/util/meson.build | 2 +
4 files changed, 247 insertions(+)
create mode 100644
This reverts commit c4ab1bdcc9710e3c7cc7115d3be9c69b7e7712ef. We need
to check the arguments looking for NaNs, because they can introduce
failures in tests for FOrd*, specially when running
VK_KHR_shader_float_control tests in CTS.
Signed-off-by: Samuel Iglesias Gonsálvez
---
This corresponds to commit 17da9f8231f78cf519b4958c2229463a63ead9e2 on GitHub.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv.core.grammar.json | 316 +++--
src/compiler/spirv/spirv.h | 84 +++---
2 files changed, 281 insertions(+), 119
Hello,
This patch series implements the support for
VK_KHR_shader_float_controls for Intel platforms (Broadwell and
later).
This extension enables efficient use of floating-point computations
through the ability to query and override the implementation's default
behavior for rounding modes,
Reviewed-by: Bas Nieuwenhuizen
On Wed, Dec 5, 2018 at 4:44 PM Eric Engestrom wrote:
>
> Added in 824cfc1ee5e0aba15b676 "radv: rework the TC-compat HTILE
> hardware bug with COND_EXEC", but it is unused.
>
> Signed-off-by: Eric Engestrom
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 1 -
> 1 file
Added in 824cfc1ee5e0aba15b676 "radv: rework the TC-compat HTILE
hardware bug with COND_EXEC", but it is unused.
Signed-off-by: Eric Engestrom
---
src/amd/vulkan/radv_cmd_buffer.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c
On Tue, 4 Dec 2018 at 18:51, Kristian H. Kristensen wrote:
>
> A couple of simple fixes for building on Android with autotools.
Reviewed-by: Emil Velikov
-Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
Hi guys
On Wed, 5 Dec 2018 at 10:49, Bas Nieuwenhuizen wrote:
>
> Reviewed-by: Bas Nieuwenhuizen
> On Wed, Dec 5, 2018 at 11:43 AM Samuel Pitoiset
> wrote:
> >
> > In case we are unlucky if the low part is 0x.
> >
> > Fixes: 5d6a560a29 ("radv: do not use the availability bit for
nvm, I somehow didn't notice that "if (atom->dType != TYPE_F32)" check...
On Wed, Dec 5, 2018 at 3:43 PM Karol Herbst wrote:
>
> but uhm, how would that work if you assert(atom->subOp ==
> NV50_IR_SUBOP_ATOM_ADD); inside handleSharedATOMGM107? I thought
> that's only needed for fadd, not for all
but uhm, how would that work if you assert(atom->subOp ==
NV50_IR_SUBOP_ATOM_ADD); inside handleSharedATOMGM107? I thought
that's only needed for fadd, not for all atoms
On Wed, Dec 5, 2018 at 3:17 PM Ilia Mirkin wrote:
>
> On Wed, Dec 5, 2018 at 4:59 AM Karol Herbst wrote:
> >
> > On Wed, Dec
On Wed, Dec 5, 2018 at 4:59 AM Karol Herbst wrote:
>
> On Wed, Dec 5, 2018 at 6:30 AM Ilia Mirkin wrote:
> >
> > Signed-off-by: Ilia Mirkin
> > ---
> > .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 49 +++
> > .../nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 +
> > 2 files
Rb me. Now you can review my comparison patches.
On December 5, 2018 06:20:49 Connor Abbott wrote:
Before this commit, there were two copies of the algorithm: one in C,
that we would use to figure out what bit-size to give the replacement
expression, and one in Python, that emulated the C
https://bugs.freedesktop.org/show_bug.cgi?id=108952
Bug ID: 108952
Summary: mesa-git broke cinnamon, temporary downgrade fix
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Rb
On December 5, 2018 07:26:22 Samuel Pitoiset wrote:
Required for VK_KHR_shader_atomic_int64.
Signed-off-by: Samuel Pitoiset
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
Required for VK_KHR_shader_atomic_int64.
Signed-off-by: Samuel Pitoiset
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index
On Wed, Dec 5, 2018 at 2:14 PM Samuel Pitoiset
wrote:
>
> Nothing to do, the compiler already handles that.
>
> All new dEQP.VK.ubo.* and dEQP.VK.ssbo.* pass, except some
> 16-bit tests that are quite related to fdo bug #108114.
>
> Signed-off-by: Samuel Pitoiset
> ---
>
On Wed, Dec 05, 2018 at 02:04:16PM +0100, Iago Toral wrote:
> On Wed, 2018-12-05 at 14:58 +0200, Pohjolainen, Topi wrote:
> > On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote:
> > > Source0 and Destination extract the floating-point precision
> > > automatically
> > > from the
Nothing to do, the compiler already handles that.
All new dEQP.VK.ubo.* and dEQP.VK.ssbo.* pass, except some
16-bit tests that are quite related to fdo bug #108114.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 6 ++
src/amd/vulkan/radv_extensions.py | 1 +
2 files
Reviewed-by: Topi Pohjolainen
On Tue, Dec 04, 2018 at 08:16:51AM +0100, Iago Toral Quiroga wrote:
> ---
> src/intel/compiler/brw_eu_emit.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c
> b/src/intel/compiler/brw_eu_emit.c
> index
On Wed, 2018-12-05 at 14:58 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote:
> > Source0 and Destination extract the floating-point precision
> > automatically
> > from the SrcType and DstType instruction fields respectively when
> > they are
>
On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote:
> Source0 and Destination extract the floating-point precision automatically
> from the SrcType and DstType instruction fields respectively when they are
> set to types :F or :HF. For Source1 and Source2 operands, we use the new
>
On Tue, Dec 04, 2018 at 08:16:48AM +0100, Iago Toral Quiroga wrote:
> The original SrcType is a 3-bit field that takes a subset of the types
> supported for the hardware for 3-source instructions. Since gen8,
> when the half-float type was added, 3-source floating point operations
> can use use
Before this commit, there were two copies of the algorithm: one in C,
that we would use to figure out what bit-size to give the replacement
expression, and one in Python, that emulated the C one and tried to
prove that the C algorithm would never fail to correctly assign
bit-sizes. That seemed
On 12/5/18 2:00 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:51 PM Tapani Pälli wrote:
On 12/5/18 1:44 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:15 PM Tapani
On Wed, Dec 5, 2018 at 12:51 PM Tapani Pälli wrote:
>
>
>
> On 12/5/18 1:44 PM, Bas Nieuwenhuizen wrote:
> > On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
> >>
> >>
> >>
> >> On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
> >>> On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli
> >>> wrote:
>
On 4.12.2018 23.52, Dylan Baker wrote:
> This little series is aimed at fixing problems reported by fedora and debian
> when using meson, there's a couple of patches in here for fixing ppc64
> detection
> (tested without llvm), and a couple for gnu hurd (not tested).
>
> Dylan Baker (5):
>
On 12/5/18 1:44 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli wrote:
On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
On Fri, Sep 7, 2018 at 12:54 AM Kevin
https://bugs.freedesktop.org/show_bug.cgi?id=108949
--- Comment #2 from mais...@archlinux.us ---
Interesting. No, haven't tried with an LLVM that recent. I'll post when I have
results.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the
On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
>
>
>
> On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
> > On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli wrote:
> >>
> >>
> >>
> >> On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
> >>> On Fri, Sep 7, 2018 at 12:54 AM Kevin Strasser
> >>> wrote:
>
On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli wrote:
On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
On Fri, Sep 7, 2018 at 12:54 AM Kevin Strasser wrote:
Android P and earlier expect that the surface supports storage images, and
so many of the
https://bugs.freedesktop.org/show_bug.cgi?id=108949
--- Comment #1 from Connor Abbott ---
This should be fixed by
https://github.com/llvm-mirror/llvm/commit/e3924b1c15606bb5bf98392e0c20e731b4965311
which was just committed 5 days ago. You'll need to build LLVM and Mesa master
to try it out.
--
On Wed, Dec 05, 2018 at 12:26:06PM +0100, Iago Toral wrote:
> On Wed, 2018-12-05 at 13:20 +0200, Pohjolainen, Topi wrote:
> > On Wed, Dec 05, 2018 at 11:53:44AM +0100, Iago Toral wrote:
> > > On Wed, 2018-12-05 at 11:39 +0200, Pohjolainen, Topi wrote:
> > > > I remember people preferring to order
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