Re: [Mesa-dev] [PATCH 2/2] ac/radv/radeonsi: refactor max simd waves into common code.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Mon, Apr 23, 2018 at 2:17 AM, Dave Airlie <airl...@gmail.com> wrote: > From: Dave Airlie <airl...@redhat.com> > > --- > src/amd/common/ac_gpu_info.h | 16 &

Re: [Mesa-dev] [PATCH 2/2] ac/radv/radeonsi: refactor harvest config register getters.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Mon, Apr 23, 2018 at 2:43 AM, Dave Airlie <airl...@gmail.com> wrote: > From: Dave Airlie <airl...@redhat.com> > > This refactors the code out to share it between radv and radeonsi. > --- &

Re: [Mesa-dev] [PATCH] nir: Do not use progress for unreachable code in return lowering.

On Mon, Apr 23, 2018 at 2:20 AM, Timothy Arceri <tarc...@itsqueeze.com> wrote: > > > On 23/04/18 03:26, Bas Nieuwenhuizen wrote: >> >> We seems to use progress for two cases: > > > seems -> seem > >> 1) When we lowered some returns. >> 2)

[Mesa-dev] [PATCH] nir: Do not use progress for unreachable code in return lowering.

We seems to use progress for two cases: 1) When we lowered some returns. 2) When we remove unreachable code. If just case 2 happens we assert as state->return_flag has not been allocated yet, but we are still trying to do insert all predicates based on it. This splits the concerns. We only use

Re: [Mesa-dev] 16-bit comparisons in NIR

On Fri, Apr 20, 2018 at 5:16 PM, Jason Ekstrand wrote: > On Fri, Apr 20, 2018 at 5:16 AM, Nicolai Hähnle wrote: >> >> On 20.04.2018 10:21, Iago Toral wrote: >>> >>> Hi, >>> >>> while developing support for Vulkan shaderInt16 on Anvil I came across >>> a

Re: [Mesa-dev] [PATCH] radv/winsys: allow to submit up to 4 IBs for chips without chaining

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Fri, Apr 20, 2018 at 2:21 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > The SI family doesn't support chaining which means the maximum > size in dwords per CS is limited. When that limit was reached >

[Mesa-dev] [PATCH] radv: Mark GTT memory as device local.

Otherwise a lot of games complain about not having enough memory, and it is sort of local so this seems reasonable to me. CC: 18.0 --- src/amd/vulkan/radv_device.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] travis: radv needs LLVM 4.0

No clue about travis, but from RADV side Acked-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Thanks! On Thu, Apr 19, 2018 at 4:18 PM, Juan A. Suarez Romero <jasua...@igalia.com> wrote: > This is a backport for 18.0 from 6ce400782c ("travis: radeonsi and radv > nee

Re: [Mesa-dev] [PATCH 1/5] radv: implement fast color clear for DCC with MSAA

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Tue, Apr 17, 2018 at 4:05 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > When DCC is enabled with MSAA textures, CMASK should be > cleared to 0x. > > Signed-off-by: Samue

Re: [Mesa-dev] [PATCH] radv: dump the SHA1 of SPIRV in the hang report

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Wed, Apr 18, 2018 at 6:53 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Might be useful for debugging purposes, especially when we > want to replace a shader on the fly. > > Signed-off-by: Samue

[Mesa-dev] [PATCH] radv: Add bound checking workaround for dynamic buffers.

I have seen a few applications and games do the dynamic buffer bounds incorrectly, this make it easier to work around, e.g. for debugging. --- src/amd/vulkan/radv_cmd_buffer.c | 4 +++- src/amd/vulkan/radv_debug.h | 1 + src/amd/vulkan/radv_device.c | 1 + 3 files changed, 5

[Mesa-dev] [PATCH] radv: Add Vega M support.

--- src/amd/vulkan/radv_device.c | 5 - src/amd/vulkan/radv_pipeline.c | 3 ++- src/amd/vulkan/radv_shader.c | 1 + src/amd/vulkan/si_cmd_buffer.c | 4 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

Re: [Mesa-dev] [PATCH 1/7] ac/surface: handle DCC subresource fast clear restriction on VI

On Wed, Apr 18, 2018 at 2:11 PM, Marek Olšák <mar...@gmail.com> wrote: > On Wed, Apr 18, 2018 at 4:44 PM, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> > wrote: >> >> IIRC if level N is unaligned then num_dcc_levels <= N+1, so level N+1 >> is not DCC compress

Re: [Mesa-dev] [PATCH 1/7] ac/surface: handle DCC subresource fast clear restriction on VI

IIRC if level N is unaligned then num_dcc_levels <= N+1, so level N+1 is not DCC compressed? On Wed, Apr 18, 2018 at 12:53 PM, Marek Olšák wrote: > On Wed, Apr 18, 2018 at 5:54 AM, Nicolai Hähnle wrote: >> >> On 17.04.2018 02:41, Marek Olšák wrote: >>> >>>

Re: [Mesa-dev] [PATCH 2/2] radv: make sure to sync after resolving using the compute path

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Tue, Apr 17, 2018 at 3:08 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > This fixes some random CTS failures: > > dEQP-VK.renderpass.multisample.*. > > Performing a fast-clear eliminate is still usel

Re: [Mesa-dev] [Mesa-stable] [PATCH] ac/nir: Make the GFX9 buffer size fix apply to image loads/atomics too.

On Mon, Apr 16, 2018 at 1:17 PM, Juan A. Suarez Romero <jasua...@igalia.com> wrote: > On Mon, 2018-04-16 at 00:09 +0200, Bas Nieuwenhuizen wrote: >> No clue how I missed those ... >> >> Fixes: 4503ff760c "ac/nir: Add workaround for GFX9 buffer views." >

Re: [Mesa-dev] [PATCH 01/10] radv: disable prediction only if it has been enabled

Reviewed-by: Bas Niuwenhuizen for the series. Thanks for the cleanup. On Fri, Apr 13, 2018 at 7:14 PM, Samuel Pitoiset wrote: > When decompressing DCC we don't enable it, so it's useless > to disable it. This reduces the number of prediction

[Mesa-dev] [PATCH] ac/nir: Make the GFX9 buffer size fix apply to image loads/atomics too.

No clue how I missed those ... Fixes: 4503ff760c "ac/nir: Add workaround for GFX9 buffer views." CC: Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105320 --- src/amd/common/ac_nir_to_llvm.c | 39 +++-- 1 file changed, 22

Re: [Mesa-dev] [PATCH 08/10] spirv: Add support for VK_EXT_descriptor_indexing uniform indexing caps.

On Fri, Apr 13, 2018 at 8:06 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > > > On 04/12/2018 01:44 AM, Bas Nieuwenhuizen wrote: >> >> --- >> src/compiler/shader_info.h| 1 + >> src/compiler/spirv/spirv_to_nir.c | 6 ++ >> 2 fi

Re: [Mesa-dev] [PATCH v3 7/7] radv: enable subgroup capabilities

Okay, this series is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Please split out the patch Jason commented on and give me a link to a branch and I'll merge. On Tue, Apr 10, 2018 at 4:37 PM, Daniel Schürmann <daniel.schuerm...@campus.tu-berlin.de> wrote: > --- &g

Re: [Mesa-dev] [PATCH] radv: Implement VK_EXT_vertex_attribute_divisor.

Test test to the list. On Thu, Apr 12, 2018 at 9:28 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Looks good to me, do you have tests? > > Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > > > On 04/12/2018 01:45 AM, Bas Nieuwenhuizen wrote: >&

[Mesa-dev] [PATCH crucible 2/2] Add VK_EXT_vertex_attribute_divisor test.

From: Bas Nieuwenhuizen <ba...@chromium.org> --- Makefile.am | 2 + .../vertex_attribute_divisor.c| 216 ++ 2 files changed, 218 insertions(+) create mode 100644 src/tests/func/vertex_attribute_d

Re: [Mesa-dev] [PATCH] radv: always select the CS resolve path for integer formats

On Thu, Apr 12, 2018 at 1:20 PM, Samuel Pitoiset wrote: > Both fixed resolve and FS resolve methods don't support integer > formats, even if destination image is DCC compressed. > > No CTS changes on Vega, but this helps fixing some tests > when DCC is enabled for MSAA

[Mesa-dev] [PATCH 10/10] radv: Enable VK_EXT_descriptor_indexing.

This adds everything except non-uniform indexing, which needs a bit more work and testing. --- src/amd/vulkan/radv_device.c | 39 +++ src/amd/vulkan/radv_extensions.py | 1 + src/amd/vulkan/radv_shader.c | 2 ++ 3 files changed, 42 insertions(+) diff --git

[Mesa-dev] [PATCH] radv: Implement VK_EXT_vertex_attribute_divisor.

Pretty straight forward, just pass the divisors through the shader key and then do a LLVM divide. --- src/amd/vulkan/radv_device.c | 6 ++ src/amd/vulkan/radv_extensions.py | 1 + src/amd/vulkan/radv_nir_to_llvm.c | 26 +++--- src/amd/vulkan/radv_pipeline.c| 26

[Mesa-dev] [PATCH 08/10] spirv: Add support for VK_EXT_descriptor_indexing uniform indexing caps.

--- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index ababe520b2d..c8128fea01b 100644 --- a/src/compiler/shader_info.h +++ b/src/compiler/shader_info.h

[Mesa-dev] [PATCH 05/10] radv: Fix GetDescriptorSetLayoutSupport.

The continue means we do alignment differently than during creation, making the buffer smaller than expected. --- src/amd/vulkan/radv_descriptor_set.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index

[Mesa-dev] [PATCH 09/10] spirv: Add support for runtime descriptor array cap.

--- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 4 2 files changed, 5 insertions(+) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index c8128fea01b..4a0a843c796 100644 --- a/src/compiler/shader_info.h +++ b/src/compiler/shader_info.h

[Mesa-dev] [PATCH 06/10] radv: Add support for variable descriptor set layouts.

--- src/amd/vulkan/radv_descriptor_set.c | 30 +++- src/amd/vulkan/radv_descriptor_set.h | 1 + 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 7a3a611dd68..9b35451c497

[Mesa-dev] [PATCH 07/10] radv: Support allocating variable size descriptor sets.

--- src/amd/vulkan/radv_descriptor_set.c | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 9b35451c497..55b4aaa388c 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++

[Mesa-dev] [PATCH 01/10] spirv: Update spirv.h to 12f8de9f04327336b699b1b80aa390ae7f9ddbf4

--- src/compiler/spirv/spirv.core.grammar.json | 169 - src/compiler/spirv/spirv.h | 18 +++ 2 files changed, 183 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/spirv.core.grammar.json b/src/compiler/spirv/spirv.core.grammar.json index

[Mesa-dev] [PATCH 03/10] radv: Don't store buffer references in the descriptor set.

--- src/amd/vulkan/radv_cmd_buffer.c | 4 -- src/amd/vulkan/radv_debug.c | 3 - src/amd/vulkan/radv_descriptor_set.c | 82 +--- src/amd/vulkan/radv_descriptor_set.h | 4 -- src/amd/vulkan/radv_private.h| 2 - 5 files changed, 13 insertions(+), 82

[Mesa-dev] [PATCH 04/10] radv: Use sorted bindings for set layout creation.

Previously we did not care about havin the set storage in order, but for variable descriptor count we want the highest binding at the end of the storage. --- src/amd/vulkan/radv_descriptor_set.c | 43 ++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 02/10] radv: Keep a global BO list for VkMemory.

With update after bind we can't attach bo's to the command buffer from the descriptor set anymore, so we have to have a global BO list. I am somewhat surprised this works really well even though we have implicit synchronization in the WSI based on the bo list associations and with the new

[Mesa-dev] [PATCH 00/10] radv VK_EXT_descriptor_indexing, part 1

This adds support for VK_EXT_descriptor_indexing except for the non-uniform indexing, which should be sent shortly. Please review! Bas Nieuwenhuizen (10): spirv: Update spirv.h to 12f8de9f04327336b699b1b80aa390ae7f9ddbf4 radv: Keep a global BO list for VkMemory. radv: Don't store buffer

Re: [Mesa-dev] [Mesa-stable] [PATCH] ac/nir: Add workaround for GFX9 buffer views.

his is the latest > release for 17.3 series. Can we please get this in 17.3? This has been submitted upstream laready for 2 weeks and this backport has been available for a week and fixes one of the major games from Feral on Vega: commit 4503ff760c794c3bb15b978a47c530037d564

Re: [Mesa-dev] [PATCH 1/3] radv: add radv_init_dcc_control_reg() helper

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Wed, Apr 11, 2018 at 2:09 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > And add some comments. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- >

Re: [Mesa-dev] [PATCH] ac/nir: Add workaround for GFX9 buffer views.

On Wed, Apr 4, 2018 at 10:19 PM, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote: > On GFX9 whether the buffer size is interpreted as elements or bytes > depends on whether IDXEN is enabled in the instruction. If the index > is a constant zero, LLVM optimizes IDXEN to 0. &

Re: [Mesa-dev] [PATCH] vulkan: fix build issue on android (both anv/radv)

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Wed, Apr 11, 2018 at 9:29 AM, Tapani Pälli <tapani.pa...@intel.com> wrote: > Fixes linking errors against: > >anv_GetPhysicalDeviceImageFormatProperties2KHR >radv_GetPhysicalDeviceImageFormatPrope

[Mesa-dev] [PATCH] ac/surface: Allow S swizzle for displayable surfaces.

For dcn1 && < 64 bpp displayable surfaces, addrlib only accepts S swizzles. At the same time addrlib prefers D swizzles is allowed, so we can just allow S swizzles as fallback. Fixes: b64b712558 "ac/surface/gfx9: request desired micro tile mode explicitly" --- src/amd/common/ac_surface.c | 7

Re: [Mesa-dev] [PATCH 1/4] ac/surface: don't set the display flag for obviously unsupported cases (v2)

What is the addrlib assertion we are hitting? On Tue, Apr 10, 2018 at 11:44 AM, Michel Dänzer wrote: > On 2018-04-06 07:12 PM, Marek Olšák wrote: >> From: Marek Olšák >> >> This enables the tile swizzle for some cases of the displayable micro mode, >>

[Mesa-dev] [PATCH] radv: Enable RB+ on Raven.

--- src/amd/vulkan/radv_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4fc7392e65e..22e8f1e7a78 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -293,7 +293,8 @@

Re: [Mesa-dev] [PATCH] radv: fix picking the method for resolve subpass

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Tue, Apr 10, 2018 at 4:00 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > The source and destination image parameters were swapped. > > No CTS changes on Polaris10, but I suspect this might >

Re: [Mesa-dev] [PATCH] radv: add shader BOs to the list at pipeline bind time

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Tue, Apr 10, 2018 at 2:09 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Otherwise, the shader BOs are not added to the list on SI because > prefetching isn't supported. Calling radv_cs_add_buffer() in the &

Re: [Mesa-dev] [PATCH] radv: move save/restore operations close to the slow clears

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> I'm wondering though, doesn't this result in more saves/restores, as we now do it for each part of a subpass clear separately? On Mon, Apr 9, 2018 at 11:10 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > This remov

[Mesa-dev] [PATCH] ac/nir: Use an array instead of hashtable for SSA defs.

Saves about 2% of compile time for F1 2017, as well as reduce code size of an optimized libvulkan_radeon.so by about 1 KiB. This still keeps the hashtable, as we also stored blocks in there. --- src/amd/common/ac_nir_to_llvm.c | 22 +- 1 file changed, 13 insertions(+), 9

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

...@gmail.com> wrote: >>> >>> On Sun, Apr 8, 2018 at 5:54 PM, Bas Nieuwenhuizen >>> <b...@basnieuwenhuizen.nl> wrote: >>> > On Sun, Apr 8, 2018 at 11:40 PM, Rob Clark <robdcl...@gmail.com> wrote: >>> >> On Sun, Apr 8, 20

[Mesa-dev] [PATCH 2/2] radv: Always reset draw user SGPRs after secondary command buffer.

As we sometimes reset them to -1, -1 does not mean that they are not written by the secondary command buffer. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." --- src/amd/vulkan/radv_cmd_buffer.c | 17 +++-- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git

[Mesa-dev] [PATCH 1/2] radv: Don't set instance count using predication.

The packet can sometimes be skipped, but we still think the change takes effect. This just makes the packet always take effect. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 --- src/amd/vulkan/radv_cmd_buffer.c | 2 +-

Re: [Mesa-dev] [PATCH] radv: Reset start instance/vertex when changing pipeline.

Okay, this needs more work, looks like almost everything got reset somewhere else already, and num_instances wasn't but should not be needed. On Mon, Apr 9, 2018 at 4:37 PM, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote: > Fixes: ad11fc3571 "radv: don't emit unneede

[Mesa-dev] [PATCH] radv: Reset start instance/vertex when changing pipeline.

Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 --- src/amd/vulkan/radv_cmd_buffer.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index

Re: [Mesa-dev] [PATCH] radv: fix prefetching of vertex shader and VBOs on SI

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Mon, Apr 9, 2018 at 2:38 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Forgot one check... Too many mistakes for a simple change. > > Fixes: f1d7c16e85 ("radv: fix prefetching compute shaders

[Mesa-dev] [PATCH] radv: Enable RB+ where possible.

According to Marek, not enabling it on Stoney has a significant negative performance impact. (And I guess this might impact performance on Raven as well) The register settings are pretty much copied from radeonsi. I did not put this in the pipeline as that would make the pipeline more dependent

Re: [Mesa-dev] [PATCH v2 4/4] radv: implement VK_AMD_shader_core_properties

On Mon, Apr 9, 2018 at 10:12 AM, Samuel Pitoiset wrote: > Simple extension that only returns information for AMD hw. > > v2: - update computation of computeUnitsPerShaderArray > > Signed-off-by: Samuel Pitoiset > --- >

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

On Sun, Apr 8, 2018 at 11:40 PM, Rob Clark <robdcl...@gmail.com> wrote: > On Sun, Apr 8, 2018 at 5:20 PM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >>>>>>>>>> + >>>>>>>>>> + /** The mode of the underlying

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

On Sun, Apr 8, 2018 at 10:43 PM, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote: > On Sun, Apr 8, 2018 at 10:23 PM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> On Tue, Apr 3, 2018 at 8:32 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: >>>

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

+ + /** The mode of the underlying variable */ + nir_variable_mode mode; >>> >>> In fact, it seems like deref->mode is unused outside of nir_print and >>> nir_validate.. for logical addressing we can get the mode from the >>> deref_var->var at the

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

On Sun, Apr 8, 2018 at 10:23 PM, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote: > On Tue, Apr 3, 2018 at 8:32 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: >> This commit adds a new instruction type to NIR for handling derefs. >> Nothing uses it yet but this adds

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

On Sun, Apr 8, 2018 at 6:06 PM, Rob Clark <robdcl...@gmail.com> wrote: > On Sun, Apr 8, 2018 at 11:15 AM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> On Sun, Apr 8, 2018 at 3:29 PM, Rob Clark <robdcl...@gmail.com> wrote: >>> On Sun, Apr 8, 20

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

On Tue, Apr 3, 2018 at 8:32 PM, Jason Ekstrand wrote: > This commit adds a new instruction type to NIR for handling derefs. > Nothing uses it yet but this adds the data structure as well as all of > the code to validate, print, clone, and [de]serialize them. > --- >

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

On Sun, Apr 8, 2018 at 3:29 PM, Rob Clark <robdcl...@gmail.com> wrote: > On Sun, Apr 8, 2018 at 8:58 AM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> On Sun, Apr 8, 2018 at 1:38 PM, Rob Clark <robdcl...@gmail.com> wrote: >>> On Tue, Apr

Re: [Mesa-dev] [PATCH v3 002/104] nir: Add a deref instruction type

On Sun, Apr 8, 2018 at 1:38 PM, Rob Clark wrote: > On Tue, Apr 3, 2018 at 2:32 PM, Jason Ekstrand wrote: >> This commit adds a new instruction type to NIR for handling derefs. >> Nothing uses it yet but this adds the data structure as well as all of >>

Re: [Mesa-dev] [PATCH 4/4] radv: implement VK_AMD_shader_core_properties

On Fri, Apr 6, 2018 at 2:28 PM, Samuel Pitoiset wrote: > Simple extension that only returns information for AMD hw. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 71 > +++

Re: [Mesa-dev] [PATCH 0/8] radv: some cleanups & preliminary work for DCC MSAA

Thanks. The series is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Fri, Apr 6, 2018 at 7:34 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Hi, > > This small series is a preliminary work before doing some > improvements in the DCC/CMASK/FMAS

[Mesa-dev] [PATCH] radv: Enable RB+ where possible.

According to Marek, not enabling it on Stoney has a significant negative performance impact. (And I guess this might impact performance on Raven as well) The register settings are pretty much copied from radeonsi. I did not put this in the pipeline as that would make the pipeline more dependent

Re: [Mesa-dev] [PATCH 3/4] radv: rename radv_cmd_buffer_update_vertex_descriptors()

On Thu, Apr 5, 2018 at 11:42 AM, Samuel Pitoiset wrote: > ... to radv_flush_vertex_buffers(). > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff

Re: [Mesa-dev] [PATCH] radv: enable the Polaris small primitive filter control

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Thu, Apr 5, 2018 at 10:27 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Enable it directly in the preamble, but do not enable line > on Polaris10/11/12 because there is a hw bug. > > There is pos

Re: [Mesa-dev] [PATCH] radv: only enable PERFECT_ZPASS_COUNTS for precision occlusion queries

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Thu, Apr 5, 2018 at 10:27 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > This unnecessary when the precision bit flag is not set, and this > might hurt performance. The Vulkan explain

Re: [Mesa-dev] [PATCH] radv: disable TC-compat HTILE on Tonga and Iceland

On Thu, Apr 5, 2018 at 10:32 AM, Samuel Pitoiset wrote: > Ported from RadeonSI. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_image.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/src/amd/vulkan/radv_image.c

[Mesa-dev] [PATCH] ac/nir: Add workaround for GFX9 buffer views.

On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct

Re: [Mesa-dev] [PATCH 3/3] radv: implement a fast prefetch path for the vertex stage

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Wed, Apr 4, 2018 at 12:12 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > This allows to start draws as soon as possible. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com&

Re: [Mesa-dev] [PATCH 2/2] radv: don't use the SPI barrier management bug workaround

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Wed, Apr 4, 2018 at 10:55 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Ported from RadeonSI. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > s

Re: [Mesa-dev] [PATCH] radv: do not always disable dual quad mode when chip has RbPlus

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Thu, Mar 29, 2018 at 2:51 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > For GFX9+ only, RadeonSI does this too. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > sr

Re: [Mesa-dev] [PATCH] radv: enable VK_EXT_shader_viewport_index_layer

Has someone grown tests for this since the time I sent patches for enabling this to the list? Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Mon, Apr 2, 2018 at 6:17 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > The driver already supports expo

Re: [Mesa-dev] [PATCH 1/4] radv: put more fields in radv_blend_state

Series is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Thu, Mar 29, 2018 at 3:24 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Some will be used for further optimizations (ie. out-of-order rast). > > Signed-off-by: Samuel Pitoiset <s

Re: [Mesa-dev] [PATCH] radv: Unset ZRANGE_PRECISION when depth was zeroed

00, James Legg wrote: >> On Thu, 2018-03-22 at 02:36 +0100, Bas Nieuwenhuizen wrote: >> > On Thu, Mar 8, 2018 at 12:59 PM, James Legg <jl...@feralinteractive.com> >> > wrote: >> > > This avoids bug 105396 somehow. I suspect it is a VI and GFX9 hardware >&

Re: [Mesa-dev] [PATCH 1/2] radv: add support for VK_EXT_sampler_filter_minmax

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Sun, Mar 25, 2018 at 8:15 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > The driver only supports the required formats for now. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gma

Re: [Mesa-dev] [PATCH] radv: only enable one channel when exporting prim id

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Tue, Mar 20, 2018 at 10:07 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > It's a 32-bit integer like the layer. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > src/

Re: [Mesa-dev] [PATCH 1/4] ac/surface: set AddrSurfInfoIn.format = ADDR_FMT_8, add assertions

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Tue, 27 Mar 2018, 10:08 Samuel Pitoiset, <samuel.pitoi...@gmail.com> wrote: > Tested-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > > On 03/27/2018 02:39 AM, Marek Olšák wrote: > > From:

Re: [Mesa-dev] [PATCH 1/2] radv: add support for Vega12

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Thu, Mar 22, 2018 at 4:41 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Based on RadeonSI. Untested. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > s

Re: [Mesa-dev] [PATCH] radv: disable binning state in some situations

I'd rather we figure out a story of when it is faster. I tried a lot of stuff with the currently available games, and getting it consistently faster was difficult. So if you have a raven ridge, feel free to try something, but I'm not really a fan of copying it blindly without understanding it.

Re: [Mesa-dev] [ANNOUNCE] mesa 18.0.0-rc5

isl: Don't use surface format R32_FLOAT for typed atomic integer > operations > intel/compiler: Memory fence commit must always be enabled for gen10+ > > Bas Nieuwenhuizen (6): > radv: Always lower indirect derefs after nir_lower_global_vars_to_local. > vul

Re: [Mesa-dev] [PATCH] radv: Unset ZRANGE_PRECISION when depth was zeroed

ists.freedesktop.org> > CC: Dave Airlie <airl...@redhat.com> > CC: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> > CC: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > src/amd/vulkan/radv_cmd_buffer.c | 52 > +--- >

Re: [Mesa-dev] [PATCH 3/3] radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Wed, Mar 21, 2018 at 9:30 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > The hardware only supports 32-bit depth surfaces, but we can > enable TC-compat HTILE for 16-bit depth surfa

Re: [Mesa-dev] [PATCH] radv: optimize path when depth clamp is disabled

On Tue, Mar 20, 2018 at 3:11 PM, Samuel Pitoiset wrote: > Ported from AMVDVLK. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_pipeline.c | 14 ++ > 1 file changed, 14 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH] st/mesa: add compiler/nir/ prefix for nir includes

is compiler/nir/nir.h the preferred way? I checked src/amd and we are using "nir/nir.h" all the time. On Tue, Mar 20, 2018 at 12:41 PM, Emil Velikov wrote: > From: Emil Velikov > > Stay consistent with the rest of the codebase, effectively

Re: [Mesa-dev] [PATCH] radv: enable VK_AMD_negative_viewport_height

The reason they cannot be enabled at the same time is because the behavior was different. I see nothing about using the AMD behavior in this patch? Also since IIRC maintenance1 is core in vulkan 1.1 we cannot reasonably expose the AMD ext if the instance was created with vulkan >= 1.1 On Mon, Mar

Re: [Mesa-dev] [PATCH] radv: enable VK_EXT_depth_range_unrestricted

I think we still need to support image->image copies with depth outside the range [0,1]. There was no explicit restriction on that, but before enabling this it is impossible to get an image with depth not in [0,1] so we did not have to care. But the gfx path uses the depth HW with no depth bound

Re: [Mesa-dev] [PATCH] radv/multiview: mark layer_input if we have input attachments.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Mon, Mar 19, 2018 at 4:42 AM, Dave Airlie <airl...@gmail.com> wrote: > From: Dave Airlie <airl...@redhat.com> > > This fixes: > dEQP-VK.multiview.input_attachments* > --- > src/amd/vulkan/radv_shad

Re: [Mesa-dev] [PATCH] radv: lower constant initializers on output variables earlier

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Mon, Mar 19, 2018 at 5:30 AM, Dave Airlie <airl...@gmail.com> wrote: > From: Dave Airlie <airl...@redhat.com> > > If a shader only writes to an output via a constant initializer we > n

Re: [Mesa-dev] [FLAG-DAY-PREP 0/9] nir: accessors for deref vars

FWIW Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Thu, Mar 15, 2018 at 3:27 PM, Rob Clark <robdcl...@gmail.com> wrote: > Since a fair bit of access to nir_deref_var's is just to chase down the > nir_variable for an intrinsic (or texture/sa

Re: [Mesa-dev] [PATCH 1/7] radv: only display options that are enabled

One comment on patch 7, and the LLVM dump ordering issue we debugged earlier (where we should dump before compiling), otherwise the series is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Wed, Mar 14, 2018 at 12:27 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wro

Re: [Mesa-dev] [PATCH 7/7] radv: dump LLVM IR when AMD_shader_info is used

On Wed, Mar 14, 2018 at 12:27 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_shader.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/amd/vulkan/radv_shader.c

Re: [Mesa-dev] [RFC] nir: Add a deref instruction type

On Thu, Mar 15, 2018 at 6:33 AM, Jason Ekstrand wrote: > This commit adds a new instruction type to NIR for handling derefs. > Nothing uses it yet but this adds the data structure as well as all of > the code to validate, print, clone, and [de]serialize them. > > Cc: Rob

Re: [Mesa-dev] [PATCH 2/6] spirv/radv: add AMD_gcn_shader capability, remove current extensions

On Thu, Mar 15, 2018 at 10:46 AM, Daniel Schürmann <daniel.schuerm...@campus.tu-berlin.de> wrote: > With AMD_gcn_shader renamed to gcn_shader, this patch is > > Reviewed-by: Daniel Schürmann Note that the mailaddress is mangled a bit. Reviewed-by: Bas Nieuwenhuizen <b...@b

Re: [Mesa-dev] [PATCH 0/2] nir: Move the si vote lowering to common code

Thanks a lot! Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Sat, Mar 10, 2018 at 7:42 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Sat, Mar 10, 2018 at 10:18 AM, Jason Ekstrand <ja...@jlekstrand.net> > wrote: >> >> This

Re: [Mesa-dev] [PATCH 6/6] ac/nir: rename radeon_llvm_reg_index_soa() to ac_llvm_reg_index_soa()

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> for the series. On Tue, Mar 13, 2018 at 3:06 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > src/amd/common/ac_nir_to_llvm.c |

Re: [Mesa-dev] [PATCH 0/9] move all RADV related shader code outside of ac/nir

Thanks, 1-8 are Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Patch 9 is Acked-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Mon, Mar 12, 2018 at 3:52 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > > > On 03/12/2018 03:25 PM, Samuel Pitois

Re: [Mesa-dev] [PATCH 0/9] move all RADV related shader code outside of ac/nir

On Mon, Mar 12, 2018 at 2:50 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > > > On 03/12/2018 02:48 PM, Bas Nieuwenhuizen wrote: >> >> On Mon, Mar 12, 2018 at 2:48 PM, Samuel Pitoiset >> <samuel.pitoi...@gmail.com> wrote: >>> >>>

Re: [Mesa-dev] [PATCH 0/9] move all RADV related shader code outside of ac/nir

On Mon, Mar 12, 2018 at 2:48 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > > > On 03/12/2018 02:24 PM, Bas Nieuwenhuizen wrote: >> >> Hi Samuel, >> >> Can we put the code into a separate file, instead of into radv_shader.c? > > > If

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