you're aware I know little about this code).
Anyway, with the explanation it sounds reasonable to me, and since it seemed
like nobody was actually opposed to it:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
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On Sun, Feb 08, 2015 at 02:48:02PM -0800, Matt Turner wrote:
On Sun, Feb 8, 2015 at 1:59 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
Certain platforms support the ability to sample from a texture, and write
it out
to the file RT - thus saving a costly send instructions (and before
On Fri, Feb 20, 2015 at 03:34:21AM -0800, Kenneth Graunke wrote:
On Thursday, February 19, 2015 10:48:08 PM Ben Widawsky wrote:
When under dispatch_width=16 the previous code would allocate 2 registers
for
the payload when only one is needed. This manifested itself through bugs on
SKL
On Thu, Feb 19, 2015 at 11:25:56PM -0800, Jordan Justen wrote:
On 2015-02-19 21:40:37, Ben Widawsky wrote:
On Thu, Feb 19, 2015 at 03:42:05PM -0800, Jordan Justen wrote:
For fragment programs, we pull this mask from the payload header. The same
mask doesn't exist for compute shaders, so
approach.
Fixes the following piglit test:
bin/arb_pipeline_statistics_query-geom -auto
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210
Tested-by: Mark Janes mark.a.ja...@intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
___
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issuing the atomic operation.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Cc: Francisco Jerez curroje...@riseup.net
Just add to the commit message that this is needed specifically because compute
is invoked as SIMD16 (and perhaps reference the other
...@whitecape.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa
On Wed, Feb 18, 2015 at 07:13:54PM +, Neil Roberts wrote:
Ben Widawsky b...@bwidawsk.net writes:
I promise to look at this again in more detail tomorrow when I am more
awake, but meanwhile, I'd be very much in favor of just setting
mt-qpith for all miptree layout types.
I'm
On Tue, Feb 17, 2015 at 11:41:01AM -0800, Ian Romanick wrote:
On 02/13/2015 11:02 PM, Ben Widawsky wrote:
This was originally part of a single patch which added the extension, and
implemented it for i965 classic. For information about the evolution of the
patch, please see the subsequent
have to fall back though.
Cc: Kenneth Graunke kenn...@whitecape.org
Cc: Kristian Høgsberg k...@bitplanet.net
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
I have no had time to benchmark this very much, nor run piglit on it. I am just
sending it out before it bitrots too much further
into the switch statement (Jordan)
- Jordan: Add compute shader support
v5:
- Fixed relnote styles (Ilia)
Cc: Ian Romanick i...@freedesktop.org
Cc: Ilia Mirkin imir...@alum.mit.edu
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
docs/relnotes/10.6.0.html| 4 +
src/mesa
On Tue, Feb 17, 2015 at 04:59:37PM -0800, Matt Turner wrote:
On Tue, Feb 17, 2015 at 4:44 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
With scalar VS, it so happens that many vertex shaders will line up in a
such a
way that two SIMD8 instructions can be collapsed into 1 SIMD16
On Tue, Feb 17, 2015 at 06:14:14PM -0800, Ian Romanick wrote:
On 02/17/2015 04:21 PM, Ben Widawsky wrote:
On Tue, Feb 17, 2015 at 11:41:01AM -0800, Ian Romanick wrote:
On 02/13/2015 11:02 PM, Ben Widawsky wrote:
This was originally part of a single patch which added the extension
the previous change will fix cases that write atomics, such as
atomicCounterIncrement, and this change will fix cases than only read
atomics, such as atomicCounter.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Cc: Francisco Jerez curroje...@riseup.net
couldn't find wins on
BSW, and that makes me worry that we missed something - since I was really
expecting to see something. I'll defer to you on that however.
The idea makes sense to me.
Acked-by: Ben Widawsky b...@bwidawsk.net
[snip]
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On Tue, Feb 17, 2015 at 02:03:36PM +, Neil Roberts wrote:
According to the bspec since Skylake the qpitch value in the surface
formats should be measured in pixels rather than rows for 1D textures.
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 30
+++---
1
On Tue, Feb 17, 2015 at 11:37:44AM -0800, Ian Romanick wrote:
On 02/13/2015 11:02 PM, Ben Widawsky wrote:
From: Jordan Justen jordan.l.jus...@intel.com
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/main/context.h | 11
On Mon, Feb 16, 2015 at 09:24:34AM -0800, Jason Ekstrand wrote:
On Feb 16, 2015 7:46 AM, Francisco Jerez curroje...@riseup.net wrote:
Jason Ekstrand ja...@jlekstrand.net writes:
On Feb 15, 2015 11:55 PM, Ben Widawsky benjamin.widaw...@intel.com
wrote:
The short version: we need
.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87258
Cc: Kristian Høgsberg k...@bitplanet.net
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src
) {
+ fprintf(file, %4d: , ip++);
+ dump_instruction(inst, file);
+ }
}
if (file != stderr) {
Both are:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
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into the switch statement (Jordan)
Cc: Ian Romanick i...@freedesktop.org
Cc: Ilia Mirkin imir...@alum.mit.edu
Signed-off-by: Ben Widawsky b...@bwidawsk.net
i965/cs: Add CS pipeline_stats support (squash)
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
docs/relnotes/10.6.0.html
From: Jordan Justen jordan.l.jus...@intel.com
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/main/context.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/mesa/main/context.h b/src/mesa/main/context.h
index
)
Add checks for desktop gl (Ilia)
Fail for any callers for now (Ilia)
Update QueryCounterBits for new tokens (Ilia)
Jordan: Use _mesa_has_compute_shaders
Cc: Jordan Justen jljus...@gmail.com
Cc: Ilia Mirkin imir...@alum.mit.edu
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
.../glapi/gen
On Wed, Feb 11, 2015 at 05:08:33AM -0800, Kenneth Graunke wrote:
On Tuesday, February 10, 2015 05:22:45 PM Ben Widawsky wrote:
Since we can be in this code with SIMD4x2, the execsize will be 4, and so
the
register width must be = 4. If you use a vec8, the width is 8, and we'll
assert
glslparsertest/glsl2/condition-07.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert
Cc: Neil Roberts n...@linux.intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 ++--
1 file changed, 2 insertions(+), 2
of iterating in reverse through blocks and
insts, since the last block/inst is the only thing which can benefit.
Rebased on top of Ken's patching modifying is_last_send
Cc: Kenneth Graunke kenn...@whitecape.org
Cc: Jason Ekstrand jason.ekstr...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
On Wed, Jan 14, 2015 at 10:34:52AM -0800, Jason Ekstrand wrote:
On Tue, Jan 13, 2015 at 11:37 PM, Ben Widawsky benjamin.widaw...@intel.com
wrote:
This patch will use a new calculation to determine if a surface can be
blitted
from or to. Previously, the total_height member was used
.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Both are:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
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On Wed, Jan 14, 2015 at 10:42:01AM -0800, Jason Ekstrand wrote:
On Tue, Jan 13, 2015 at 11:37 PM, Ben Widawsky benjamin.widaw...@intel.com
wrote:
The blit engine is limited to 32Kx32K transfer. In cases where we have to
fall
back to the blitter, and when trying to blit a slice of a 2d
On Mon, Feb 02, 2015 at 11:37:26PM -0500, Ilia Mirkin wrote:
On Mon, Dec 8, 2014 at 9:50 PM, Ben Widawsky b...@bwidawsk.net wrote:
Thanks. All the requests look good, and I'll post it in v3.
What happened to this patch? It was pretty close... should be easy to
add gallium support for it too
On Thu, Jan 15, 2015 at 11:33:22AM -0800, Kenneth Graunke wrote:
On Thursday, January 15, 2015 08:56:23 AM Ben Widawsky wrote:
On Thu, Jan 15, 2015 at 01:41:14AM -0800, Kenneth Graunke wrote:
There's some debate about whether we should use Meta or BLORP,
but either should run circles
On Tue, Jan 13, 2015 at 11:37:50PM -0800, Ben Widawsky wrote:
This patch will use a new calculation to determine if a surface can be blitted
from or to. Previously, the total_height member was used. Total_height in
the
case of 2d, 3d, and cube map arrays is the height of each slice/layer/face
raw stall optimization, the improvement
is even more stark on Braswell.
Jordan was extremely helpful in creating this patch. Consider him co-author.
References: http://patchwork.freedesktop.org/patch/38909/
Cc: Jordan Justen jordan.l.jus...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
allocate
a linear BO for huge buffers. The next patch changes that.
v2: Fix NDEBUG warning
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_blit.c | 107 -
1 file changed, 105 insertions(+), 2 deletions(-)
diff --git a/src/mesa
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_blit.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index e919528..9500bd7 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
An upcoming patch is going to introduce some code here, and having this code
organized as the patch does makes it a bit easier to read later.
There should be no functional change here.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_blit.c | 28
On Mon, Jan 12, 2015 at 02:02:34PM +0200, Ville Syrjälä wrote:
On Sun, Jan 11, 2015 at 07:14:57PM -0800, Ben Widawsky wrote:
On Sun, Jan 11, 2015 at 07:05:21PM -0800, Kenneth Graunke wrote:
On Sunday, January 11, 2015 05:46:09 PM Ben Widawsky wrote:
On Sun, Jan 11, 2015 at 04:05:25PM
On Sun, Jan 11, 2015 at 07:05:21PM -0800, Kenneth Graunke wrote:
On Sunday, January 11, 2015 05:46:09 PM Ben Widawsky wrote:
On Sun, Jan 11, 2015 at 04:05:25PM -0800, Kenneth Graunke wrote:
On Sunday, January 11, 2015 01:49:41 PM Ben Widawsky wrote:
On Sat, Jan 10, 2015 at 06:44:49PM
asked you
to look at ;-) and FWIW, Jordan has numbers on BSW B-step with my kernel patch
which we can use for the commit):
Signed-off-by: Ben Widawsky b...@bwidawsk.net
I haven't looked at Broadwell docs, so I'll let someone else take care of that.
I don't know if I agree with Chris that we should
On Sun, Jan 11, 2015 at 04:05:25PM -0800, Kenneth Graunke wrote:
On Sunday, January 11, 2015 01:49:41 PM Ben Widawsky wrote:
On Sat, Jan 10, 2015 at 06:44:49PM -0800, Kenneth Graunke wrote:
This is an important optimization for avoiding read-after-write (RAW)
stalls in the HiZ buffer
On Sun, Jan 11, 2015 at 06:53:32PM -0800, Kenneth Graunke wrote:
[snip]
Jesse had suggested setting it in broadwell_init_clock_gating on January 5th,
and Valtteri tried it on January 7th. He found no noticeable difference.
I tried it again, and confirmed his result: there was zero
On Wed, Nov 12, 2014 at 11:17:55AM -0800, Kenneth Graunke wrote:
According to the documentation, we need to do a CS stall on every fourth
PIPE_CONTROL command to avoid GPU hangs. The kernel does a CS stall
between batches, so we only need to count the PIPE_CONTROLs in our batches.
v2: Get
-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
--
Ben Widawsky, Intel Open Source Technology Center
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)
- Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian)
- Core mesa parts moved into a prep patch (Ilia)
Cc: Ian Romanick i...@freedesktop.org
Cc: Ilia Mirkin imir...@alum.mit.edu
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
docs/relnotes/10.5.0.html
Cc: Ilia Mirkin imir...@alum.mit.edu
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
.../glapi/gen/ARB_pipeline_statistics_query.xml| 24 +++
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml | 3 +
src/mesa/main/config.h
On Tue, Dec 23, 2014 at 10:38:36AM -0800, Matt Turner wrote:
On Mon, Dec 22, 2014 at 7:29 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
The fancy DW * DW = QW that was enabled earlier in the series for the fs
does
not work for the vec4 paths. vec4 paths use ALIGN16 mode, which
On Tue, Dec 23, 2014 at 10:45:27AM -0800, Matt Turner wrote:
On Mon, Dec 22, 2014 at 7:29 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
This patch addresses the errata on GEN8+ which disallows the mul/mach macro
to
have a modifier on src1. This was previously listed as a FINISHME
On Mon, Dec 22, 2014 at 07:29:30PM -0800, Ben Widawsky wrote:
I couldn't find any other callers which have a DW operand in a mul.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
It would be good if someone else can take a look
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 6
if you change the module parameter in
a running system, and then it's
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Checking introduces a synchronization point between the CPU and GPU:
even though we submit very few GPU commands, the GPU might be busy doing
other work, which could cause us
that match other
generations), I see no change. I am however optimistic that the series will
prevent future failures.
(BDW does add 1 new pass, but I am not sure if it's real):
spec/ARB_texture_multisample/texelFetch fs sampler2DMSArray 4
98x1x9-98x129x9:fail pass
Ben Widawsky (19):
i965/vec4
As it turns out, I have other uses for this tiny convenience function. Simple
extraction for use by others. Matt was right for not liking the macro in the
initial patch.
While doing this, add it to a few easy to spot users of this functionality.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
on GEN8 as
well.
Cc: Kenneth Graunke kenn...@whitecape.org
Cc: Matt Turner matts...@gmail.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965
was.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 77 ++---
1 file changed, 72 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 1fc5a2f
to determine that the argument
passed in is within the correct boundary, however, it was using UQ as the upper
limit instead of Q.
To my knowledge you can only hit this case with the branch I am currently
working on, so it doesn't fix any known issues.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
must exist.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index a04149c..76d3248 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
This is the analogous patch to i965/fs: Extract dword multiplies. Like that
patch, we'll do the internal users separately to aid bisection.
Because that patch was requested by Jason, this was is also indirectly requested
by him.
Cc: Jason Ekstrand jason.ekstr...@intel.com
Signed-off-by: Ben
As it turns out, we were over-thinking the cause of the hang on
Cherryview. It's simply errata for Cherryview.
commit 88fea85f09e2252035bec66ab26c375b45b000f5
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Fri Nov 21 10:47:41 2014 -0800
i965/vec4/gen8: Handle the MUL dest hazard
I couldn't find any other callers which have a DW operand in a mul.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
It would be good if someone else can take a look
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src
this case, we do have
some ability to fix it up, and so we try to do that. Some cases we cannot fix
things and so we must assert. Finding it at visitor time does make things a bit
easier to debug and fix.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 44
This is the vec4 analogous patch to i965/fs: Add users of emit_mul_dw
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
It would be good if someone else can take a look
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
If we have any case where both operands can fit in 16b, a plain old mul with no
mach should be sufficient.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src
patches, this actually applies to the whole MUL/MACH macro
operation, but it's easier to just catch it at MACH, since that is the only
thing we use MACH for.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp | 2 +-
src/mesa/drivers/dri/i965
for
imul_high. This fixes failing tests on IVB, and doesn't seem to hurt the same
tests on HSW.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 52
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers
separately for easier bisection.
Cc: Jason Ekstrand jason.ekstr...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 106 +++
src/mesa/drivers/dri/i965/brw_fs.h | 4 +
src/mesa/drivers/dri/i965
There are currently 2 users of this functionality. I have 2 more users coming
up, and having a simple function makes the results much cleaner. The existing
interface semantics was proposed by Matt.
Cc: Matt Turner matts...@gmail.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa
. Any other usage is for the
high results from the MUL/MACH macro
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86822
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 28 +++-
1 file changed, 19 insertions(+), 9
it requires the accumulator write flag, which can hinder optimization passes.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_defines.h| 2 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 12 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 73
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 76f..49d92bb 100644
This patch addresses the errata on GEN8+ which disallows the mul/mach macro to
have a modifier on src1. This was previously listed as a FINISHME.
Assertions for these cases will be added shortly.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
.
This assertion applies to mul too as mentioned above. It is harder to detect mul
when used in the macro operation, so that is left for now.
Accumulator is an implicit source and thus cannot be an explicit source
operand.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965
wrote equivalent code using the QW type.
Cc: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++-
src/mesa/drivers/dri/i965/brw_eu.h | 21 +
src/mesa/drivers/dri/i965
On Mon, Dec 15, 2014 at 01:28:52PM -0800, Ian Romanick wrote:
On 12/14/2014 04:39 PM, Ben Widawsky wrote:
On Fri, Dec 12, 2014 at 11:15:42PM -0800, Kenneth Graunke wrote:
Chris Wilson noted that repeated calls to CheckQuery() would call
drm_intel_bo_references(brw-batch.bo, query-bo
), I don't see
anything wrong here, so it's:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
I do hope to see some perf improvements.
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(and perhaps commit message updated to explain), this
is
Reviewed-by: Ben Widawsky b...@bwidawsk.net
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-by: Ben Widawsky b...@bwidawsk.net
Need a bit more time to review 5
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We support MOCS on both gen8 and gen9, so the message seems meaningless. Remove
it to avoid confusion.
Trivial.
Cc: Kristian Høgsberg k...@bitplanet.net
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/gen8_misc_state.c | 3 ---
1 file changed, 3 deletions(-)
diff
The odds of having this patch make a difference on Gen8+ are probably very low.
Only compile tested.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_blit.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri
the workaround more understandable, and more future-proof.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
Let's assume that this IVB specific feature exists on BYT too, since it's very
much like IVB
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965
As far as I can tell, this restriction is always needed.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index efe63b5..25bf37b
...@whitecape.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4ae700c..efe63b5 100644
On Tue, Dec 09, 2014 at 04:14:14PM -0800, Matt Turner wrote:
On Tue, Dec 9, 2014 at 4:02 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
Let's assume that this IVB specific feature exists on BYT too, since it's
very
much like IVB
To clarify, the feature does *not* exist on Haswell
On Tue, Dec 09, 2014 at 04:03:00PM -0800, Ben Widawsky wrote:
Quoting the workaround already there:
This field must be set to VALIGN_4 for all tiled Y Render Target surfaces.
This patch simply asserts we return Y tiled, instead of X or Y. It has no
effect
on the code since the only caller
On Tue, Dec 02, 2014 at 11:07:34PM -0800, Ian Romanick wrote:
Since there will be a v3 anyway, nits below...
On 12/02/2014 06:33 PM, Ben Widawsky wrote:
This patch implements ARB_pipeline_statistics_query. This addition to GL
does
not add a new API. Instead, it adds new tokens
On Thu, Dec 04, 2014 at 10:02:24PM -0800, Kristian Høgsberg wrote:
fs_generator no longer knows what stage it's generating code for, so
we have to set the debug name of the shader from the call site.
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
---
On Fri, Dec 05, 2014 at 01:36:52PM -0800, Matt Turner wrote:
On Fri, Dec 5, 2014 at 1:34 PM, Ben Widawsky b...@bwidawsk.net wrote:
I do wonder the original motivation for the debug_flag member. Seems totally
superfluous.
Because brw_fs_generator is used by the fs and by blorp, and you want
DEBUG_OPTIMIZER (1 27)
-#define DEBUG_NO_ANNOTATION (1 28)
+#define DEBUG_ANNOTATION (1 28)
#define DEBUG_NO8 (1 29)
#ifdef HAVE_ANDROID_PLATFORM
I never had an opinion, but I completely agree. With or without my suggestion
above:
Reviewed-by: Ben
don't really see the need to have 2-4 as separate patches, but as you
like).
1-4:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp| 2 +-
src/mesa/drivers/dri/i965/brw_fs.h | 2
On Fri, Dec 05, 2014 at 06:56:27PM -0800, Matt Turner wrote:
On Fri, Dec 5, 2014 at 6:18 PM, Vinson Lee v...@freedesktop.org wrote:
This patch fixes this build error with GCC = 4.6.
CXXtest_vf_float_conversions.o
test_vf_float_conversions.cpp: In function ‘unsigned int f2u(float)’:
On Fri, Dec 05, 2014 at 08:57:27PM -0800, Ian Romanick wrote:
On 12/05/2014 05:23 PM, Ben Widawsky wrote:
On Fri, Dec 05, 2014 at 05:08:40PM -0800, Matt Turner wrote:
---
Eric was against making this the default when I first suggested a flag.
Have opinions changed since then? I rarely use
.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84777 (with many dupes)
Cc: 10.4 mesa-sta...@lists.freedesktop.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 5 -
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 3 ++-
2 files
On Thu, Dec 04, 2014 at 05:08:21PM -0800, Matt Turner wrote:
On Thu, Dec 4, 2014 at 3:37 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
The GS has an interesting use for mul. It's essentially used as a fancy mov
(in
fact, I am not sure why a mov isn't used). The documentation
On Thu, Dec 04, 2014 at 07:48:06PM -0800, Ben Widawsky wrote:
On Thu, Dec 04, 2014 at 05:08:21PM -0800, Matt Turner wrote:
On Thu, Dec 4, 2014 at 3:37 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
The GS has an interesting use for mul. It's essentially used as a fancy
mov
SKL moves the GS threadcount to dw8 from dw7, and no longer does the divide by 2
thing.
Only compile test.
Cc: Kristian Høgsberg k...@bitplanet.net
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/gen8_gs_state.c | 29 ++---
1 file changed, 18
On Wed, Dec 03, 2014 at 04:47:18PM -0800, Matt Turner wrote:
---
The number of times I've wondered why piglit/gbm wasn't working...
src/egl/drivers/dri2/egl_dri2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index
On Wed, Dec 03, 2014 at 11:27:55PM -0800, Ben Widawsky wrote:
On Wed, Dec 03, 2014 at 04:47:18PM -0800, Matt Turner wrote:
---
The number of times I've wondered why piglit/gbm wasn't working...
src/egl/drivers/dri2/egl_dri2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src
On Tue, Dec 02, 2014 at 04:17:35PM +, Neil Roberts wrote:
Ok, I've written a somewhat contrived test case here:
https://github.com/bpeel/glthing/tree/time-attribs
(Make sure to use the time-attribs branch)
The example draws a 1000 single-pixel points each with a separate draw
call.
(Ilia)
- Add a fallthrough comment (Ilia)
- Only divide PS invocations by 4 on HSW+ (Ben)
Cc: Ilia Mirkin imir...@alum.mit.edu
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
.../glapi/gen/ARB_pipeline_statistics_query.xml| 24
src/mesa/drivers/dri/i965/gen6_queryobj.c | 121
On Tue, Dec 02, 2014 at 10:47:37PM -0500, Ilia Mirkin wrote:
On Tue, Dec 2, 2014 at 9:33 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
This patch implements ARB_pipeline_statistics_query. This addition to GL
does
not add a new API. Instead, it adds new tokens to the existing query
An easy one :D
Reviewed-by: Ben Widawsky b...@bwidawsk.net
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