The existing backend code assumed that if VARYING_SLOT_CLIP_DIST0
was written, then VARYING_SLOT_CLIP_DIST1 would be as well. That's
true with the current lowering, but not necessary if there are 4 or
fewer clip distances. Separate out the checks to allow this.
The new NIR-based lowering will tr
I'll want the variables in the next patch.
---
src/compiler/nir/nir_lower_clip.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/src/compiler/nir/nir_lower_clip.c
b/src/compiler/nir/nir_lower_clip.c
index ced6d31c117..2299f746305 100644
--- a/src/comp
The way nir_lower_clip_vs() works with store_output intrinsics makes a
ton of assumptions about the driver_location field.
In i965, I'd rather do this lowering early and work with variables.
ir3 and vc4 could probably do that as well, but I'm not sure exactly
what paths would need updating, so for
---
src/compiler/nir/nir_lower_clip.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/compiler/nir/nir_lower_clip.c
b/src/compiler/nir/nir_lower_clip.c
index 7081295a500..013645101f2 100644
--- a/src/compiler/nir/nir_lower_clip.c
+++ b/src/compiler/nir/nir_lower_clip
On Wednesday, November 7, 2018 1:45:59 PM PST Jason Ekstrand wrote:
> On Wed, Nov 7, 2018 at 12:20 PM Kenneth Graunke
> wrote:
>
> > On Saturday, October 20, 2018 10:55:44 AM PST Jason Ekstrand wrote:
> > > @@ -553,14 +552,18 @@
> > fs_visitor::optimize_frontfacin
On Wednesday, October 31, 2018 5:12:40 PM PST Aditya Swarup wrote:
> For Intel platforms, we support external textures only for EGLImages
> created with EGL_EXT_image_dma_buf_import. This restriction seems to
> be Intel specific and not present for other platforms.
>
> While running SKQP test - un
the condition. Normally I wouldn't mind, but I'm a bit
paranoid about float equality in assertions. It's probably fine,
though, since we ensured fabsf is 1.0f earlier...
Patches 5-9 are:
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed messa
= iter.raw_value;
> - } else if (strcmp(iter.name, "Insntruction Base Address Modify
> Enable") == 0) {
> + } else if (strcmp(iter.name, "Instruction Base Address Modify Enable")
> == 0) {
> instruction_modify = it
On Monday, November 5, 2018 5:02:49 AM PST Sergii Romantsov wrote:
> Message that may show the culprit of assert now will
> be dumped before that for debug purposes.
>
> CC: Kenneth Graunke
> CC: Lionel G Landwerlin
> Signed-off-by: Sergii Romantsov
> ---
> s
This will let us make multiple genX_*.c files, without copy and pasting
all this boilerplate.
---
src/mesa/drivers/dri/i965/Makefile.sources| 10 ++
src/mesa/drivers/dri/i965/genX_boilerplate.h | 160 ++
src/mesa/drivers/dri/i965/genX_state_upload.c | 129 +-
src/
Clearer name.
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
src/mesa/drivers/dri/i965/brw_pipe_control.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 122ac260703.
This implements virtually all documented PIPE_CONTROL restrictions
in a centralized helper. You now simply ask for the operations you
want, and the pipe control "brain" will figure out exactly what pipe
controls to emit to make that happen without tanking your system.
The hope is that this will f
While this does add a bunch of boilerplate, it also protects us against
the hardware moving bits, or changing their meaning. For something as
finnicky as PIPE_CONTROL, the extra safety seems worth it.
We turn PIPE_CONTROL_* into an bitfield of arbitrary flags, and then
pack them appropriately.
--
There are some cases where the VS is the only stage enabled, it uses the
entire URB, and the URB is large enough that placing later stages after
the VS exceeds the number of bits for "URB Starting Address".
For example, on Icelake GT2, "varying-packing-simple mat2x4 array" from
Piglit is getting a
On Wednesday, October 31, 2018 11:15:28 AM PDT Rafael Antognolli wrote:
> On Tue, Oct 30, 2018 at 04:32:54PM -0700, Kenneth Graunke wrote:
> > On Monday, October 29, 2018 10:19:54 AM PDT Rafael Antognolli wrote:
> > Do we need any stalling when whacking CS_CHICKEN1...?
>
>
line.c | 1 -
> 3 files changed, 5 insertions(+), 20 deletions(-)
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
it will be disabled
> by a previous 3DPRIMITIVE, which should be fine too.
>
> Signed-off-by: Rafael Antognolli
> Cc: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/genX_state_upload.c | 47 +++
> 1 file changed, 47 insertions(+)
>
> diff --git a/src/mesa/
tlab.freedesktop.org/rantogno/piglit/commits/review/context_preemption_v2
>
> Cc: Kenneth Graunke
>
> Rafael Antognolli (3):
> intel/genxml: Add register for object preemption.
> i965/gen10+: Enable object level preemption.
> i965/gen9: Add workarounds for object pre
On Friday, October 26, 2018 1:06:52 AM PDT andrey simiklit wrote:
> Hi,
>
> Could you please help me with a push. I don't have a right for it :-)
>
> Thanks,
> Andrii.
Thanks for fixing these up!
While we're here, there are several other variables where we track the
last known state of the GPU,
Apparently, we're supposed to look at the texture object's built-in
sampler object's sRGB decode setting in order to decide whether to
decode/downsample/re-encode, or simply downsample as-is. Previously,
I had always done the decoding/encoding.
Fixes SKQP's Skia_Unit_Tests.SRGBMipMaps test.
---
rMaskEnable = GEN_GEN >= 8;
>
> - ps.SamplerCount =
> - DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
> + /* WA_1606682166:
> +* "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
> +* Disable th
e - Payloads - SIMD8 Payload [BDW+])
> that vertex shaders could consult.
>
> CC: Jason Ekstrand
> CC: Kenneth Graunke
> CC: Anuj Phogat
> Signed-off-by: Topi Pohjolainen
> ---
> src/intel/blorp/blorp_genX_exec.h | 6 ++
> src/intel/vulkan/genX_pipelin
We use cross-thread constants to only upload one copy of the uniforms
on Haswell and later. We only duplicate things on Ivybridge. The
comment suggests that we duplicate data everywhere, which is inaccurate.
The second FINISHME is about a new mechanism we could use, if we wanted
to, but we aren'
t; +
> /* If we can't alter the depth stencil config and multiple layers are
> * involved, the HiZ op will fail. This is because the op requires that a
> * new config is emitted for each additional layer.
Series is:
Reviewed-by: Kenneth Graunke
signature.asc
Description: Thi
ARB programs won't have one of these, and we don't use it anyway.
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index c15bd7e511b..dcde95cd60
This will let me use it in the ARB program code as well.
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 66 +--
src/mesa/state_tracker/st_nir.h | 4 ++
2 files changed, 41 insertions(+), 29 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/
In the non-SSO case, where multiple shader stages are linked together,
we were recording garbage pipe_stream_output_info structures for all
but the last enabled geometry-processing stage.
Specifically, we were using the gl_transform_feedback_info from
shader_program->last_vert_prog (the stage whos
On Friday, October 19, 2018 3:04:45 PM PDT Marek Olšák wrote:
> On Mon, Oct 15, 2018 at 6:35 PM Kenneth Graunke
> wrote:
>
> > From: Jason Ekstrand
> >
> > They're not required to be the same as the access flag on the image
> > unit. For hardware that d
nsertions(+), 9 deletions(-)
Thanks for fixing this! Looks like everything's properly in bytes now.
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.f
On Monday, October 22, 2018 2:57:10 AM PDT Lionel Landwerlin wrote:
> Could you maybe update src/intel/tools/aubinator_viewer_decoder.cpp
> (function handle_state_base_address) ?
>
> Either way :
>
> Reviewed-by: Lionel Landwerlin
Oops, good call, thanks!
Pushed a v2 that updates both.
sign
STATE_BASE_ADDRESS only modifies various bases if the "modify" bit is
set. Otherwise, we want to keep the existing base address.
Iris uses this for updating Surface State Base Address while leaving the
others as-is.
---
src/intel/common/gen_batch_decoder.c | 24 +---
1 file c
On Friday, October 19, 2018 10:17:29 AM PDT Matt Turner wrote:
> On Thu, Oct 18, 2018 at 6:06 PM Kenneth Graunke wrote:
> >
> > This warning detects non-void functions with a missing return statement,
> > return statements with a value in void functions, and functions wit
Usually when making a new file, people copy some random other file
to get the copyright header comments. Unfortunately, some of them
are commented in a decades-old style, are word wrapped poorly, or
worse, have a few subtle variations in the text. While we've tried
to clean those up, we're not go
On Thursday, October 11, 2018 12:12:38 PM PDT Kenneth Graunke wrote:
> On Thursday, October 11, 2018 11:58:40 AM PDT Kenneth Graunke wrote:
> > On Tuesday, October 2, 2018 9:16:01 AM PDT asimiklit.w...@gmail.com wrote:
> > > From: Andrii Simiklit
> > >
> > >
This warning detects non-void functions with a missing return statement,
return statements with a value in void functions, and functions with an
bogus return type that ends up defaulting to int. It's already enabled
by default with -Wall. Generally, these are fairly serious bugs in the
code, whic
This warning detects non-void functions with a missing return statement,
return statements with a value in void functions, and functions with an
bogus return type that ends up defaulting to int. It's already enabled
by default with -Wall. Generally, these are fairly serious bugs in the
code, whic
See commit c0c46ca461f136a0ae1ed69da6c874e850aeeb53 in the Linux kernel,
where José Roberto de Souza added this new PCI ID there.
---
include/pci_ids/i965_pci_ids.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_id
From: Jason Ekstrand
They're not required to be the same as the access flag on the image
unit. For hardware that does shader image lowering based on the
qualifier (Intel), it may be required for state setup.
---
src/gallium/include/pipe/p_state.h | 1 +
src/mesa/state_tracker/st_atom_image
We probably don't need to iterate, fprintf, and abort in release mode.
---
src/intel/compiler/brw_fs_validate.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_validate.cpp
b/src/intel/compiler/brw_fs_validate.cpp
index 676942c19c0..75a794fd794 100644
--- a/src/i
My recent prog_to_nir patch started making new sampler uniforms, which
apparently increased the number of parameters. We used to poke at the
one parameter directly, making it important that there was only one,
but we haven't done that in a while. It should be safe to just delete
the assertion.
F
From: Dave Airlie
If GLSL has already done the lowering, we'd rather not crash in this pass.
Reviewed-by: Kenneth Graunke
---
src/compiler/nir/nir_lower_clip_cull_distance_arrays.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/compiler/nir/nir_lower_clip_cull_distance_arr
GL exposes separate queries for each pipeline statistics counter.
For some reason, Gallium chose to map them all to a single target,
PIPE_QUERY_PIPELINE_STATISTICS. Radeon hardware appears to query
them all as a group. pipe->get_query_result_resource() takes an
index, indicating which to write to
On Thursday, October 11, 2018 11:58:40 AM PDT Kenneth Graunke wrote:
> On Tuesday, October 2, 2018 9:16:01 AM PDT asimiklit.w...@gmail.com wrote:
> > From: Andrii Simiklit
> >
> > I guess that when we calculating the width0, height0, depth0
> > to use for function &#x
On Thursday, October 11, 2018 11:58:40 AM PDT Kenneth Graunke wrote:
> On Tuesday, October 2, 2018 9:16:01 AM PDT asimiklit.w...@gmail.com wrote:
> > From: Andrii Simiklit
> >
> > I guess that when we calculating the width0, height0, depth0
> > to use for function &#x
s only good
up until the new base...and have to re-assemble it the next time they
change the base. It would save memory potentially. But more copies.
I don't have a strong preference which is better.
Please do make a Piglit or dEQP test for this.
Reviewed-by: Kenneth Graunke
> diff -
| 38 +++-
> 12 files changed, 579 insertions(+), 108 deletions(-)
> create mode 100644 src/mesa/drivers/dri/i965/intel_tiled_memcpy_normal.c
> create mode 100644 src/mesa/drivers/dri/i965/intel_tiled_memcpy_sse41.c
> create mode 100644 src/mesa/drivers/dri/i965/intel_tiled_mem
On Tuesday, October 2, 2018 11:06:23 AM PDT Chris Wilson wrote:
> Reuse the same query object buffer for multiple queries within the same
> batch.
>
> A task for the future is propagating the GL_NO_MEMORY errors.
>
> Signed-off-by: Chris Wilson
> Cc: Kenneth Graun
h void * though, so it
ends up working for now...
Acked-by: Kenneth Graunke
On Tuesday, October 2, 2018 7:30:09 AM PDT Eric Engestrom wrote:
> Ping?
> I'm just adding `const` to make it easier to read and understand the
> code, and allow the compiler to tell us if we make a mistake
On Monday, September 24, 2018 8:18:37 PM CEST Nicholas Kazlauskas wrote:
> Applications that don't present at a predictable rate (ie. not games)
> shouldn't have adaptive sync enabled. This list covers some of the
> common desktop compositors, web browsers and video players.
>
> Signed-off-by: Nic
On Wednesday, September 26, 2018 12:48:13 AM CEST Kenneth Graunke wrote:
> On Tuesday, September 25, 2018 4:20:04 PM CEST Ilia Mirkin wrote:
> > I haven't double-checked yet, but doesn't this result in a reduction
> > of functionality for pre-independent-blend GPUs (like t
On Tuesday, September 25, 2018 4:20:04 PM CEST Ilia Mirkin wrote:
> I haven't double-checked yet, but doesn't this result in a reduction
> of functionality for pre-independent-blend GPUs (like the early NVIDIA
> Tesla series)? Configuring blending for an integer RT does nothing on
> NVIDIA hardware
On Monday, September 17, 2018 3:24:56 PM PDT Dylan Baker wrote:
> Quoting Marek Olšák (2018-09-17 15:14:11)
> > How do I build 32-bit Mesa with meson?
> >
> > Thanks,
> > Marek
> >
>
> Some people get away with just adding CFLAGs=-m32, but using a cross file and
> doing a cross build is a better
GEN11_URB_MIN_MAX_ENTRIES,
> + },
> .simulator_id = 19,
> };
>
> static const struct gen_device_info gen_device_info_icl_1x8 = {
> GEN11_FEATURES(1, 1, subslices(1), 6),
> + .urb = {
> + .size = 768,
> + GEN11_URB_MIN_MAX_ENTRIES,
> + },
> .simulator
On Tuesday, August 28, 2018 10:54:57 AM PDT Anuj Phogat wrote:
> h/w specification requires this bit to be always set.
>
> Suggested-by: Kenneth Graunke
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen11.xml| 5 +
> src/intel/vulkan/genX_state.c | 14
On Tuesday, August 28, 2018 3:31:18 PM PDT Anuj Phogat wrote:
> h/w specification requires this bit to be always set.
>
> V2: Fix bit mask (Chris Wilson)
>
> Suggested-by: Kenneth Graunke
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_defines.h
/ Argument: VF Invalidate
*
* "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
* 'Write PS Depth Count' or 'Write Timestamp'."
*/
With those two parts updated for the appropriate gen, this would be
R
tion shaders are
> + * likely generating and processing far more geometry than the
> vertex
> + * stage.
> + */
> + vs.VertexCacheDisable = true;
> + }
>
>vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
>v
vb_emit |= pipeline->vb_used;
>
> assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
>
>
This patch is:
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
ndle the case where they don't.
>
> Fixes: fb2a5ceb3264 "anv: Emit DRAWING_RECTANGLE once at driver..."
> ---
> src/intel/vulkan/gen7_cmd_buffer.c | 5 +++--
> src/intel/vulkan/genX_cmd_buffer.c | 3 ++-
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
This patch is:
Rev
On Friday, September 7, 2018 6:34:45 AM PDT Chris Wilson wrote:
> As a prelude to handling large address spaces, first allow ourselves the
> luxury of handling the full 4G.
>
> Reported-by: Andrey Simiklit
> Cc: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/br
On Thursday, September 6, 2018 3:30:58 AM PDT Lionel Landwerlin wrote:
> On 05/09/2018 18:01, Kenneth Graunke wrote:
> > On Tuesday, September 4, 2018 3:30:42 AM PDT Lionel Landwerlin wrote:
> >> Both brw_bo_map_cpu() & brw_bo_map_wc() assert if mapping the
> >> un
On Tuesday, September 4, 2018 3:30:42 AM PDT Lionel Landwerlin wrote:
> Both brw_bo_map_cpu() & brw_bo_map_wc() assert if mapping the
> underlying BO fails. Failing back to brw_bo_map_gtt() doesn't seem to
> make any sense for that reason.
>
> We also only call brw_bo_map_gtt() for tiled buffers w
On Tuesday, September 4, 2018 5:22:31 AM PDT Lionel Landwerlin wrote:
> On 04/09/2018 11:46, Sergii Romantsov wrote:
> > Seems in case of 32-bit library, usage of msse2 makes
> > some stack corruption or incorrect instructions.
> > Usage with mstackrealign fixes that case.
> >
> > Bugzilla: https:/
On Tuesday, September 4, 2018 2:57:29 AM PDT Lionel Landwerlin wrote:
> Both brw_bo_map_cpu() & brw_bo_map_wc() assert if mapping the
> underlying BO fails. Failing back to brw_bo_map_gtt() doesn't seem to
> make any sense for that reason.
>
> We also only call brw_bo_map_gtt() for tiled buffers w
On Saturday, September 1, 2018 9:24:53 AM PDT Jason Ekstrand wrote:
> This appears to hang broadwell; we should probably think twice before
> enabling it so broadly. I'll adjust it to be gen9 only or we can just can
> the patch entirely.
There a bunch of workarounds and they're tricky to get righ
On Saturday, September 1, 2018 12:14:38 AM PDT Marek Olšák wrote:
> From: Marek Olšák
>
> This reduces mutex overhead.
>
> +4.4% performance with piglit/drawoverhead, DrawElements, Ryzen X1700
+14% with piglit/drawoverhead and iris_dri.so, DrawArrays, i7 7700HQ.
Acked-by:
_CONSTANT_ALLOC_VS << 16 | (2 - 2));
> OUT_BATCH(vs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
> @@ -154,6 +181,7 @@ const struct brw_tracked_state gen7_push_constant_space =
> {
> .dirty = {
>.mesa = 0,
>.brw = BRW_NEW_CONTEXT |
> + BRW_NEW_BATCH | /* P
> emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
> - input_read_header, indirect_offset);
> + input_read_header, clamped_indirect_offset);
>} else {
> /* Arbitrarily only push up to 24 vec4 slots worth of data,
>* which is 12 reg
7;t have that much image_load_store happening in the
> shaders in shader-db
Looks like the untyped stride checks are back and the unnecessary typed
load checks (mistakenly copied from atomics) are gone. Nice.
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed messa
,
> +BRW_REGISTER_TYPE_UD);
> + image = bld.emit_uniformize(image);
> +
> + /* Since the image size is always uniform, we can just emit a SIMD8
> + * query instruction and splat the result out.
> + */
> + con
12 +++-
> 6 files changed, 9 insertions(+), 29 deletions(-)
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
ial to decouple the two and provide
> actual binding table indices.
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Wednesday, August 29, 2018 5:31:38 AM PDT Jason Ekstrand wrote:
> On Wed, Aug 29, 2018 at 12:49 AM Kenneth Graunke
> wrote:
>
> > On Friday, August 17, 2018 1:06:20 PM PDT Jason Ekstrand wrote:
> > [snip]
> > > +# Intel-specific query for loading from the brw
On Wednesday, August 29, 2018 5:38:59 AM PDT Jason Ekstrand wrote:
> On Wed, Aug 29, 2018 at 1:36 AM Kenneth Graunke
> wrote:
>
> > On Friday, August 17, 2018 1:06:24 PM PDT Jason Ekstrand wrote:
> > > ---
> > > src/intel/compiler/brw_eu_defines.h |
On Friday, August 17, 2018 1:06:24 PM PDT Jason Ekstrand wrote:
> ---
> src/intel/compiler/brw_eu_defines.h | 3 +++
> src/intel/compiler/brw_fs.cpp | 8 ++
> src/intel/compiler/brw_fs_generator.cpp | 26 ---
> src/intel/compiler/brw_fs_nir.cpp
: RELOC_WRITE);
> + written ? RELOC_WRITE : 0);
> }
>
> isl_surf_fill_image_param(&brw->isl_dev, param, &mt->surf, &view);
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> i
quot;)
> +unop_convert("unpack_half_2x16_split_y", tfloat32, tuint32,
> + "unpack_half_1x16((uint16_t)(src0 >> 16))")
>
> unop_convert("unpack_32_2x16_split_x", tuint16, tuint32, "src0")
> unop_convert("unpack_32_2x16_split_y&q
On Friday, August 17, 2018 1:06:20 PM PDT Jason Ekstrand wrote:
[snip]
> +# Intel-specific query for loading from the brw_image_param struct passed
> +# into the shader as a uniform. The variable is a deref to the image
> +# variable. The const index specifies which of the six parameters to load.
On Monday, August 27, 2018 6:18:21 PM PDT Marek Olšák wrote:
> On Mon, Aug 27, 2018 at 5:55 PM, Kenneth Graunke
> wrote:
> > On Monday, August 27, 2018 11:05:19 AM PDT Marek Olšák wrote:
> >> Yeah, this will be more complicated because it's per RT.
> >>
>
On Monday, August 27, 2018 11:03:33 AM PDT Nanley Chery wrote:
> On Fri, Aug 24, 2018 at 05:46:44PM -0700, Nanley Chery wrote:
> > According to internal docs, some gen9 platforms have a pixel shader push
> > constant synchronization issue. Although not listed among said
> > platforms, this issue se
On Monday, August 27, 2018 11:05:19 AM PDT Marek Olšák wrote:
> Yeah, this will be more complicated because it's per RT.
>
> I suggest adding a PIPE_CAP for the hw capability to force DST_ALPHA
> to 0, and applying this workaround only if the PIPE_CAP is 0.
>
> Marek
I was thinking of applying t
On Saturday, August 25, 2018 6:05:57 AM PDT Jason Ekstrand wrote:
> On Fri, Aug 24, 2018 at 8:24 PM Kenneth Graunke
> wrote:
>
> > This is needed for nir_gather_info to actually count the textures,
> > since it operates solely on variables.
> > ---
> > sr
When faking an RGB format with an RGBA format, there may be a channel
of data containing garbage. st/mesa already overrides texture swizzles
to replace the A channel with ONE. This patch makes it override blend
factors to achieve a similar effect.
It appears that st_update_blend is already calle
Blending isn't valid for integer formats. Rather than having drivers
worry about this, just disable blending in this case. This hopefully
will increase hits in the CSO cache as well, by eliminating most of the
meaningless fields in this case.
---
src/mesa/state_tracker/st_atom_blend.c | 1 +
1 f
This is needed for nir_gather_info to actually count the new textures,
since it operates solely on variables.
---
src/compiler/nir/nir_lower_bitmap.c | 7 +++
src/compiler/nir/nir_lower_drawpixels.c | 17 -
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/src
Several of the passes change varyings. This is necessary for
inputs_read and outputs_written to be accurate.
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
i
This is needed for nir_gather_info to actually count the textures,
since it operates solely on variables.
---
src/mesa/program/prog_to_nir.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 14
This lets us example SAMPLER_STATE's LOD Bias field, among other things.
---
src/intel/common/gen_decoder.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index ec0a486b101..a276f37835b 100644
--- a/src
On Monday, August 20, 2018 10:26:29 AM PDT Anuj Phogat wrote:
> On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke wrote:
[snip]
> > I don't know if people are trying to enable pre-emption during GPGPU
> > work on pre-Gen11. If so, that probably will not work, and we'd
t; - for (unsigned i = 0; i < num_components; i++) {
This used to operate on the num_components parameter to
nir_format_pack_uint, but now it operates on color->num_components
instead. That's probably OK...do we even need the parameter?
Nothing actually uses this function in ma
; be able to shrink them for i965.
> ---
> src/compiler/glsl/glsl_to_nir.cpp | 9 +++--
> src/compiler/nir/nir_intrinsics.py | 4 ++--
> src/compiler/spirv/spirv_to_nir.c | 2 ++
> 3 files changed, 11 insertions(+), 4 deletions(-)
Patches 10-13 are:
Reviewed-by: Kenne
;
> +
> + /* Clamp to the range [0, 1] */
Should be [-1, 1] here.
Could always move nir_fclamp from nir_builtin_builder.h to nir_builder.h
and then use that here, too. Would be ever so slightly simpler.
With the comment fixed,
Reviewed-by: Kenneth Graunke
> + f = nir_fmin(b,
R MODE register is set to 0, which means
> + * headerless sampler messages are not allowed for pre-emptable
> + * contexts. Set the bit 5 to 1 to allow them.
Bonus space after the stars. Can we also change this to:
* contexts. Set bit 5 to allow them.
Same for the anv p
and eventually use it with the radv driver.
Patches 1-8 are
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
, -17);
>
> for (unsigned i = 0; i < 3; i++)
>
Patches 9-10 are:
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
igned-off-by: Anuj Phogat
> ---
> src/intel/vulkan/genX_pipeline.c | 21 +++--
> 1 file changed, 15 insertions(+), 6 deletions(-)
Looks reasonable, we can always revert it later.
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a di
This new function takes separate Z24 depth and S8 stencil sources,
and packs them into a single combined Z24S8 buffer.
---
src/gallium/auxiliary/util/u_format_zs.c | 20
src/gallium/auxiliary/util/u_format_zs.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/src/galli
This will be used by u_transfer_helper.c shortly, in order to split
packed depth-stencil into separate resources.
---
src/gallium/auxiliary/util/u_format.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_format.h
b/src/gallium/auxiliary/util
u_transfer_helper already had code to handle treating packed Z32_S8
as separate Z32_FLOAT and S8_UINT resources, since some drivers can't
handle that interleaved format natively.
Other hardware needs depth and stencil as separate resources for all
formats. For example, V3D3 needs this for 24-bit
Hi Sergii,
This patch causes 2,384 failures in CI. The issue is that we're
apparently trying to allocate 0 size BOs in some places, which are
getting rounded up to 4096 with the current code...but with your patch,
we get ALIGN(0, 4096) == 0, and assert(bo_size) triggers.
We might want to continu
101 - 200 of 8758 matches
Mail list logo
