Re: [Mesa-dev] [PATCH] intel/fs: Use a pure vertical stride for large register strides

> only works > + * for sources since destinations require hstride == 1. > + */ > +brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, > 0); > +brw_reg = stride(brw_reg, reg->stride, 1, 0); I think it is a good idea

Re: [Mesa-dev] [PATCH 4/4] intel/fs/nir: Return Q types from brw_reg_type_for_bit_size

Patch series is, Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam On Thu, 2017-11-02 at 21:53 -0700, Jason Ekstrand wrote: > Now that we're returning a sane type, we can drop the retyping to Q > in > nir_emit_load_const. > > Cc: Jose Maria Cas

Re: [Mesa-dev] [PATCH 1/2] i965: Be more clever about setting up our viewport clip

Both patches are, Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam On Fri, 2017-11-03 at 15:31 -0700, Jason Ekstrand wrote: > Before, we were trusting in the hardware to take the intersection > of the viewport clip with the drawing rectangle. U

[Mesa-dev] [PATCH] anv: fix bug when using component qualifier in FS outputs

.linkage.varying.component.frag_out.* Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/shader_enums.h | 1 + src/intel/vulkan/anv_pipeline.c | 10 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_enums.h

Re: [Mesa-dev] [PATCH v3 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

On Wednesday, October 18, 2017 8:11:01 AM CEST Jason Ekstrand wrote: > On October 18, 2017 12:54:48 AM Samuel Iglesias Gonsálvez > > <sigles...@igalia.com> wrote: > > v2: > > - Use helper to add a new source to the texture instruction. > > > > Signed-of

[Mesa-dev] [PATCH v3 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

v2: - Use helper to add a new source to the texture instruction. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir_lower_tex.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compil

[Mesa-dev] [PATCH v3 3/4] i965/vec4: remove setting default LOD in the backend

It is already done in NIR. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> --- src/intel/compiler/brw_vec4_nir.cpp | 9 - src/intel/compiler/brw_vec4_visitor.cpp | 12 2 files

[Mesa-dev] [PATCH v3 2/4] i965/fs: remove setting default LOD in the backend

It is already done in NIR. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 9 - 1 file changed, 9 deletions(-) diff --git a/src/intel/compiler/brw_fs_ni

[Mesa-dev] [PATCH v3 4/4] spirv: add support for images and samplers as function arguments

Fixes: dEQP-VK.spirv_assembly.instruction.*.image_sampler.* Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_cfg.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c

Re: [Mesa-dev] [PATCH v2 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

On Wed, 2017-10-11 at 09:12 +0100, Lionel Landwerlin wrote: > On 11/10/17 09:00, Samuel Iglesias Gonsálvez wrote: > > On Tuesday, October 10, 2017 4:40:47 PM CEST Lionel Landwerlin > > wrote: > > > On 10/10/17 14:35, Samuel Iglesias Gonsálvez wrote: > > > > Sign

Re: [Mesa-dev] [PATCH v2 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

On Wednesday, October 11, 2017 10:12:16 AM CEST Samuel Iglesias Gonsálvez wrote: > On Tuesday, October 10, 2017 11:53:27 AM CEST Eric Anholt wrote: > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > Signed-off-by: Samuel Iglesias Gonsálv

Re: [Mesa-dev] [PATCH v2 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

On Tuesday, October 10, 2017 11:53:27 AM CEST Eric Anholt wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > --- > > > > src/compiler/nir/nir_lower_tex.c | 68 > >

Re: [Mesa-dev] [PATCH v2 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

On Tuesday, October 10, 2017 4:40:47 PM CEST Lionel Landwerlin wrote: > On 10/10/17 14:35, Samuel Iglesias Gonsálvez wrote: > > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > --- > > > > src/compiler/nir/nir_lower_tex.c | 68 > > +++

[Mesa-dev] [PATCH v2 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir_lower_tex.c | 68 1 file changed, 68 insertions(+) diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index 65681decb1c..d3380

[Mesa-dev] [PATCH v2 2/4] i965/fs: remove setting default LOD in the backend

It is already done in NIR. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_fs_nir.cpp | 9 - 1 file changed, 9 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5b8ccd50bff..5c2f0

[Mesa-dev] [PATCH v2 3/4] i965/vec4: remove setting default LOD in the backend

It is already done in NIR. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4_nir.cpp | 9 - src/intel/compiler/brw_vec4_visitor.cpp | 12 2 files changed, 21 deletions(-) diff --git a/src/intel/compiler/brw_vec4_nir.

[Mesa-dev] [PATCH v2 4/4] spirv: add support for images and samplers as function arguments

Fixes: dEQP-VK.spirv_assembly.instruction.*.image_sampler.* Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_cfg.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c

Re: [Mesa-dev] [PATCH 1/4] i965/fs: some TXF don't provide LOD

On Fri, 2017-10-06 at 08:28 -0700, Jason Ekstrand wrote: > On Fri, Oct 6, 2017 at 6:36 AM, Samuel Iglesias Gonsálvez <siglesias@ > igalia.com> wrote: > > > > > > On Fri, 2017-10-06 at 14:23 +0100, Lionel Landwerlin wrote: > > > I fixed a simi

Re: [Mesa-dev] [PATCH 1/4] i965/fs: some TXF don't provide LOD

tion. Sam > On 06/10/17 14:07, Jason Ekstrand wrote: > > > > > > > > Is there a test case for this? > > > > > > > > > > Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> > > > &

Re: [Mesa-dev] [PATCH 2/4] spirv: Add support for fuction arguments of type image and sampler

On Fri, 2017-10-06 at 06:22 -0700, Jason Ekstrand wrote: > On Fri, Oct 6, 2017 at 2:36 AM, Samuel Iglesias Gonsálvez <siglesias@ > igalia.com> wrote: > > These arguments are actually variables, not pointers. This is > > allowed > > by SPIR-V spec but the support was

Re: [Mesa-dev] [PATCH 3/4] spirv: add sampler and image variable support when handling texture opcodes

On Fri, 2017-10-06 at 11:36 +0200, Samuel Iglesias Gonsálvez wrote: > From: Samuel Iglesias Gonsalvez <cor...@samuelig.es> > > Signed-off-by: Samuel Iglesias Gonsalvez <cor...@samuelig.es> This patch and the following should be signed off by my Igalia email. Fixed locall

[Mesa-dev] [PATCH 2/4] spirv: Add support for fuction arguments of type image and sampler

These arguments are actually variables, not pointers. This is allowed by SPIR-V spec but the support was missing. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_cfg.c | 13 + src/compiler/spirv/vtn_private.h | 5 + 2 files c

[Mesa-dev] [PATCH 1/4] i965/fs: some TXF don't provide LOD

SpvOpImageFetch doesn't provide it, so set it to zero. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_fs_nir.cpp | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/co

[Mesa-dev] [PATCH 3/4] spirv: add sampler and image variable support when handling texture opcodes

From: Samuel Iglesias Gonsalvez Signed-off-by: Samuel Iglesias Gonsalvez --- src/compiler/spirv/spirv_to_nir.c | 58 +++ 1 file changed, 47 insertions(+), 11 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c

[Mesa-dev] [PATCH 4/4] spirv: add support for image variables for image opcodes

From: Samuel Iglesias Gonsalvez Signed-off-by: Samuel Iglesias Gonsalvez --- src/compiler/spirv/spirv_to_nir.c | 27 ++- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c

Re: [Mesa-dev] [Mesa-stable] [PATCH] vulkan/wsi/wayland: Stop printing out the DRM device

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Friday, September 22, 2017 12:45:27 PM CEST Jason Ekstrand wrote: > Cc: mesa-sta...@lists.freedesktop.org > --- > src/vulkan/wsi/wsi_common_wayland.c | 1 - > 1 file changed, 1 deletion(-) > > dif

Re: [Mesa-dev] [PATCH] anv: fix viewport transformation for z component

gt; zf = pz × zd + oz > > Being zd, the third component in vertex's normalized device coordinates. > > Fixes: dEQP-VK.draw.inverted_depth_ranges.* > > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > --- > src/intel/vulkan/gen8_cmd_buffer.c | 4 +

[Mesa-dev] [PATCH] anv: fix viewport transformation for z component

-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/vulkan/gen8_cmd_buffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c index 064b8e930e..7bea231ea7 100644 --- a/src/intel/

[Mesa-dev] [PATCH v2] nir/spirv: handle if's with same label in both branches

From: "Juan A. Suarez Romero" When a conditional branch has the same labels in the "if" part and in the "else" part, then we have the same cfg block, and it must be handled once. v2: handle it the same way as OpBranch (Jason). Fixes:

Re: [Mesa-dev] [PATCH] nir/spirv: handle if's with same label in both branches

On 09/07/2017 07:03 PM, Jason Ekstrand wrote: > On Thu, Aug 24, 2017 at 8:16 AM, Juan A. Suarez Romero > > wrote: > > When a conditional branch has the same labels in the "if" part and > in the > "else" part, then we have the same cfg

Re: [Mesa-dev] [PATCH] nir/spirv: fix crashes when dereferencing a pointer for an OpVariable

On 09/07/2017 07:15 PM, Jason Ekstrand wrote: > On Tue, Aug 29, 2017 at 3:04 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com <mailto:sigles...@igalia.com>> wrote: > > When creating a vtn_pointer for an OpVariable, the block_index and > offs

Re: [Mesa-dev] [PATCH v2] nir/spirv: fix chain access with different index bit sizes

This patch is unreviewed. On Tue, 2017-08-29 at 08:42 +0200, Samuel Iglesias Gonsálvez wrote: > Currently we support 32-bit indexes/offsets all over the driver, so > we > convert them to that bit size. > > Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.* > > Signed-of

Re: [Mesa-dev] [PATCH] nir/spirv: fix crashes when dereferencing a pointer for an OpVariable

This patch is unreviewed. On Tue, 2017-08-29 at 12:04 +0200, Samuel Iglesias Gonsálvez wrote: > When creating a vtn_pointer for an OpVariable, the block_index and > offsets fields are null because there is not ssa to take the data > from. > > However, we can dereference th

Re: [Mesa-dev] [PATCH] mesa/main: Fix GetTransformFeedbacki64 for glTransformFeedbackBufferBase

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Tue, 2017-09-05 at 14:41 +0200, Iago Toral Quiroga wrote: > The spec has special rules for querying buffer offsets and sizes > when BindBufferBase is used, described  in the OpenGL 4.6 spec, > section 6.8 Buff

Re: [Mesa-dev] [Mesa-stable] [PATCH] anv/formats: Fix an off-by-one in the format array range check

I have just see Eric's patch. Forget this R-b. Sam On Mon, 2017-09-04 at 06:59 +0200, Samuel Iglesias Gonsálvez wrote: > Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > On Sun, 2017-09-03 at 17:10 -0700, Jason Ekstrand wrote: > > Found with static code

Re: [Mesa-dev] [PATCH mesa] anv: fix off by one in array check

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Sun, 2017-09-03 at 21:54 -0700, Jason Ekstrand wrote: > I sent the same patch a few hours later.  I don't care which one we > land.  You have a more descriptive commit message. > > Reviewed-by: Jason Ekstrand <

Re: [Mesa-dev] [Mesa-stable] [PATCH] anv/formats: Fix an off-by-one in the format array range check

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Sun, 2017-09-03 at 17:10 -0700, Jason Ekstrand wrote: > Found with static code analysis > > Cc: mesa-sta...@lists.freedesktop.org > --- >  src/intel/vulkan/anv_formats.c | 2 +- >  1 file changed, 1

Re: [Mesa-dev] [PATCH] anv: fix build errors on android

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Thu, 2017-08-31 at 08:52 +0300, Tapani Pälli wrote: > error: incompatible pointer to integer conversion initializing > 'VkFence' >    (aka 'unsigned long long') with an expression of type 'void *' [- > Werro

Re: [Mesa-dev] [PATCH 00/16] anv/i965: Cleanup copies of devinfo fields in brw_context

ntel CI, series is: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam > On 30/08/17 11:07, Lionel Landwerlin wrote: > > Hi all, > > > > Following a quick discussion on IRC, Matt reminded me we still had > > some duplicated fields on brw_context which just

[Mesa-dev] [PATCH] nir/spirv: fix crashes when dereferencing a pointer for an OpVariable

-VK.spirv_assembly.instruction.*.indexing.* Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_variables.c | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_varia

[Mesa-dev] [PATCH v2] nir/spirv: fix chain access with different index bit sizes

Currently we support 32-bit indexes/offsets all over the driver, so we convert them to that bit size. Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.* Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_variables.c | 11 --- 1 file chan

Re: [Mesa-dev] [PATCH] nir/spirv: add support for chain access with different index bit sizes

On Mon, 2017-08-28 at 07:08 -0700, Jason Ekstrand wrote: > On August 28, 2017 1:18:33 AM Samuel Iglesias Gonsálvez  > <sigles...@igalia.com> wrote: > > > Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.* > > > > Signed-off-by: Samuel Iglesias Gonsálvez <si

[Mesa-dev] [PATCH] nir/spirv: add support for chain access with different index bit sizes

Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.* Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_variables.c | 31 +-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_variable

Re: [Mesa-dev] [PATCH] spirv: Add support for the HelperInvocation builtin

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-08-21 at 22:11 -0700, Jason Ekstrand wrote: > I have no idea how this got missed but it's been missing since > forever. > > Cc: mesa-sta...@lists.freedesktop.org > --- >  src/compiler/spirv/vtn_va

[Mesa-dev] [PATCH v2 3/5] i965/vec4: add support for doing DF register spilling on IVB+

ing on emit_scratch_write(). - Simplify emit_scratch_read() changes. - Simplify emit_scratch_write() changes. - Merge reladdr changes. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4.cpp | 2 + src/intel/compiler/brw_vec4.h

[Mesa-dev] [PATCH v2 2/5] i965/vec4/generator: use 1-Oword Block Write messages for DF scratch write

when emitting 1-Oword Block Write messages, so we don't need to shuffle data. - Remove DF_IVB_SCRATCH_READ() and emit_1grf_df_ivb_scratch_read() - Remove VEC4_OPCODE_GEN4_SCRATCH_READ_1OWORD_{LOW,HIGH} opcodes. - Add support for Haswell. Signed-off-by: Samuel Iglesias Gonsálvez <sig

[Mesa-dev] [PATCH v2 1/5] i965/eu: add support for 1-OWord Block Read/Write messages

v2: - Use nibctrl and the number of written/read owords to detect each case of a 1-OWord Block Read/Write (Curro) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_eu.h | 14 +- src/intel/compiler/brw_eu_emit.c

[Mesa-dev] [PATCH v2 5/5] i965/vec4: allow partial DF register spilling

v2: - Enable spilling for partial DF reads/writes on HSW+ Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4_reg_allocate.cpp | 54 1 file changed, 40 insertions(+), 14 deletions(-) diff --git a/src/intel/co

[Mesa-dev] [PATCH v2 4/5] i965/vec4: fix can_use_scratch_for_source() to support partial DFs

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4_reg_allocate.cpp | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_vec4_reg_allocate.cpp b/src/intel/compiler/brw_vec4_reg_allocate.cpp

Re: [Mesa-dev] [PATCH v2 2/2] anv: ensure device name contains terminating character

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-07-17 at 00:29 +0100, Lionel Landwerlin wrote: > v2: Use sizeof() (Chris) > > CID: 1415113 > Reported-by: Grazvydas Ignotas <nota...@gmail.com> > Signed-off-by: Lionel Landwerlin <

Re: [Mesa-dev] [PATCH 1/2] i965: miptree: silence coverity warning

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Sun, 2017-07-16 at 15:31 +0100, Lionel Landwerlin wrote: > This probably can't happen, but we're better off with initialized > variables. > > CID: 1415114 > Signed-off-by: Lionel Landwerlin <lione

Re: [Mesa-dev] [PATCH 0/8] vulkan: Update to 1.0.54

On Fri, 2017-07-14 at 09:42 +0200, Samuel Iglesias Gonsálvez wrote: > On Thu, 2017-07-13 at 12:32 -0700, Jason Ekstrand wrote: > > This little series updates us to the 1.0.54 headers and XML.  The > > major > > change here is that 1.0.54 dropped the VK_KHX_external* extensions

Re: [Mesa-dev] [PATCH 0/8] vulkan: Update to 1.0.54

drop > support > for the KHX versions from anv and radv and the last 3 implement the > KHR > version of external memory and the related dependent extensions. Patches 1, 2 and 4-8 are: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> BTW, you removed VK_KHX_external_semaphore

[Mesa-dev] [PATCH] anv: check support for enabled features in vkCreateDevice()

From Vulkan spec, 4.2.1. "Device Creation": "vkCreateDevice verifies that extensions and features requested in the ppEnabledExtensionNames and pEnabledFeatures members of pCreateInfo, respectively, are supported by the implementation." Signed-off-by: Samuel Iglesi

[Mesa-dev] [PATCH] anv: merge tessellation's primitive mode in merge_tess_info()

SPIR-V tessellation shaders that were created from HSLS will have the primitive generation domain set in tessellation control shader (hull shader in HLSL) instead of the tessellation evaluation shader. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/

Re: [Mesa-dev] [PATCH 2/6] i965/vec4/generator: use 1-Oword Block Read/Write messages for DF scratch writes/reads

On Mon, 2017-06-26 at 10:38 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Fri, 2017-06-23 at 11:06 -0700, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > >

Re: [Mesa-dev] [PATCH 2/6] i965/vec4/generator: use 1-Oword Block Read/Write messages for DF scratch writes/reads

On Fri, 2017-06-23 at 11:06 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Thu, 2017-06-22 at 16:25 -0700, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > &g

Re: [Mesa-dev] [PATCH 2/6] i965/vec4/generator: use 1-Oword Block Read/Write messages for DF scratch writes/reads

On Thu, 2017-06-22 at 16:25 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > --- > >  src/intel/compiler/brw_eu_defines.h  |   2 + &g

Re: [Mesa-dev] [PATCH 5/6] i965/vec4: fix resolve reladdr case on DF scratch read/write on IVB

Please ignore this patch, I have a better solution that will be included in the v2 of the patch series. Sam On Thu, 2017-06-15 at 13:15 +0200, Samuel Iglesias Gonsálvez wrote: > We emit scratch read/write to resolve reladdr and when moving > varyings to scratch memory, however these instru

Re: [Mesa-dev] [PATCH 0/6] i965/vec4: Implement partial DF register spilling

On Thu, 2017-06-22 at 17:02 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > Hello, > > > > As mentioned in the patch series that implemented Ivybridge support > > ARB_gpu_shader_fp64 [0], the only missing feature

Re: [Mesa-dev] [PATCH 0/6] i965/vec4: Implement partial DF register spilling

On Thu, 2017-06-15 at 13:15 +0200, Samuel Iglesias Gonsálvez wrote: > Hello, > > As mentioned in the patch series that implemented Ivybridge support > ARB_gpu_shader_fp64 [0], the only missing feature in that series was > register spilling of 64-bit data and, because of that,

[Mesa-dev] [PATCH 5/6] i965/vec4: fix resolve reladdr case on DF scratch read/write on IVB

to fallback to old behavior. Fixes {vs,gs}-array-copy tests on piglit. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4.h| 9 + src/intel/compiler/brw_vec4_reg_allocate.cpp | 4 ++-- src/intel/compiler/brw_vec4_visit

[Mesa-dev] [PATCH 6/6] i965/vec4: allow partial DF register spilling

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4_reg_allocate.cpp | 32 +++- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_vec4_reg_allocate.cpp b/src/intel/co

[Mesa-dev] [PATCH 4/6] i965/vec4: add support for doing DF register spilling on IVB

ing instructions. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4.cpp | 3 ++ src/intel/compiler/brw_vec4_visitor.cpp | 69 + 2 files changed, 65 insertions(+), 7 deletions(-) diff --git a/src/intel/compiler/brw_v

[Mesa-dev] [PATCH 0/6] i965/vec4: Implement partial DF register spilling

/mesa-dev/2017-March/148646.html Samuel Iglesias Gonsálvez (6): i965/eu: add support for 1-OWord Block Read/Write messages i965/vec4/generator: use 1-Oword Block Read/Write messages for DF scratch writes/reads i965/generator: use MRF when sending 1-OWord read messages for DF scratch

[Mesa-dev] [PATCH 3/6] i965/generator: use MRF when sending 1-OWord read messages for DF scratch reads on IVB

Use MRF for 1-Oword read messages again to avoid problems when sending scratch read messages. We cannot reuse the destination as the DF scratch reads on IVB are splitted in several instructions and that could end up having invalid data. Signed-off-by: Samuel Iglesias Gonsálvez <sig

[Mesa-dev] [PATCH 2/6] i965/vec4/generator: use 1-Oword Block Read/Write messages for DF scratch writes/reads

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_eu_defines.h | 2 + src/intel/compiler/brw_shader.cpp| 5 + src/intel/compiler/brw_vec4.cpp | 7 ++ src/intel/compiler/brw_vec4.h| 8 ++ src

[Mesa-dev] [PATCH 1/6] i965/eu: add support for 1-OWord Block Read/Write messages

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_eu.h | 18 ++-- src/intel/compiler/brw_eu_emit.c| 38 + src/intel/compiler/brw_fs_generator.cpp | 5 +++-- 3 files changed, 43 inse

Re: [Mesa-dev] [PATCH] intel/blorp: Work around Sandy Bridge occlusion query issue

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Thu, 2017-06-08 at 10:45 -0700, Jason Ekstrand wrote: > --- >  src/intel/blorp/blorp_clear.c | 10 ++ >  1 file changed, 10 insertions(+) > > diff --git a/src/intel/blorp/blorp_clear.c > b/src/i

Re: [Mesa-dev] [PATCH 00/11] i965: Use BLORP for depth/stencil clears

On Mon, 2017-06-12 at 13:52 +0200, Samuel Iglesias Gonsálvez wrote: > On Tue, 2017-06-06 at 21:59 -0700, Jason Ekstrand wrote: > > This little series switches the GL driver to use BLORP for depth > > and > > stencil clears.  BLORP has had depth/stencil clear support

Re: [Mesa-dev] [PATCH 05/11] i965: Remove some of the remnants of meta

El Lunes, 12 de junio de 2017 07:57:23 Jason Ekstrand escribió: > On Mon, Jun 12, 2017 at 4:54 AM, Samuel Iglesias Gonsálvez < > > sigles...@igalia.com> wrote: > > On Tue, 2017-06-06 at 22:00 -0700, Jason Ekstrand wrote: > > > --- > > > > > > s

Re: [Mesa-dev] [PATCH 05/11] i965: Remove some of the remnants of meta

On Tue, 2017-06-06 at 22:00 -0700, Jason Ekstrand wrote: > --- >  src/mesa/drivers/dri/i965/brw_context.h   | 1 - >  src/mesa/drivers/dri/i965/brw_wm.c| 2 +- >  src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- >  3 files changed, 2 insertions(+), 3 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 00/11] i965: Use BLORP for depth/stencil clears

leaved vertex buffers >   i965: Use blorp for depth/stencil clears on gen6+ > Patches 2, 3, 6-10 are: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam >  src/intel/isl/isl_emit_depth_stencil.c|  13 ++- >  src/mesa/drivers/dri/i965/brw_blorp.c

Re: [Mesa-dev] [PATCH 1/3] i965/vec4/gs: restore the uniform values which was overwritten by failed vec4_gs_visitor execution

Kind reminder that patches 1 and 3 are still unreviewed. Sam On Fri, 2017-05-05 at 12:38 +0200, Samuel Iglesias Gonsálvez wrote: > We are going to add a packing feature to reduce the usage of the push > constant buffer. One of the consequences is that 'nr_params' would be >

Re: [Mesa-dev] [PATCH 3/6] vulkan/wsi: Ad get_capabilities2 and get_formats2d interface pointers

s/Ad/Add Series is, Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam On Mon, 2017-05-15 at 08:07 -0700, Jason Ekstrand wrote: > --- >  src/vulkan/wsi/wsi_common.h | 8 >  1 file changed, 8 insertions(+) > > diff --git a/src/vulkan/wsi/wsi_common

Re: [Mesa-dev] [PATCH 2/2] i965: Drop INTEL_DEBUG=stats.

Series is: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Tue, 2017-05-09 at 01:48 -0700, Kenneth Graunke wrote: > For whatever reason, we had an INTEL_DEBUG=stats option that enabled > various statistics counters on Gen4-5 systems.  It's been around > forever,

[Mesa-dev] [PATCH 3/3] i965/vec4: load dvec3/4 uniforms first in the push constant buffer

usage optimization. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> --- src/intel/compiler/brw_vec4.cpp | 107 ++-- 1 file changed, 80 insertions(+), 27 deletions(-) diff --gi

[Mesa-dev] [PATCH 2/3] i965/vec4: fix swizzle and writemask when loading an uniform with constant offset

) for the indirect case. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> Reviewed-by: Francisco Jerez <curroje...@riseup.net> --- src/intel/compiler/brw_vec4_nir.cpp | 15 +++ 1 file changed, 11 inserti

[Mesa-dev] [PATCH 1/3] i965/vec4/gs: restore the uniform values which was overwritten by failed vec4_gs_visitor execution

values that would be reordered afterwards. Fixes GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2 when the dvec4 alignment and packing patch is applied. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> -

Re: [Mesa-dev] [PATCH 2/2] anv: document that anv_gem_mmap returns MAP_FAILED on error

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Thu, 2017-05-04 at 15:55 +0100, Emil Velikov wrote: > From: Emil Velikov <emil.veli...@collabora.com> > > Signed-off-by: Emil Velikov <emil.veli...@collabora.com> > --- >  src/intel/vulkan/anv_

Re: [Mesa-dev] [PATCH 1/2] anv: fix anv_gem_mmap comment to not mention NULL

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Thu, 2017-05-04 at 15:55 +0100, Emil Velikov wrote: > From: Emil Velikov <emil.veli...@collabora.com> > > The function cannot return NULL, update the comment accordingly. > > Fixes: b546c9d ("anv: a

Re: [Mesa-dev] [PATCH] anv: vkBindImageMemory() should return VK_ERROR_OUT_OF_{HOST, DEVICE}_MEMORY on error

On Thu, 2017-05-04 at 14:03 +0100, Emil Velikov wrote: > On 4 May 2017 at 11:01, Samuel Iglesias Gonsálvez <siglesias@igalia.c > om> wrote: > > Fixes returned value changed by b546c9d. > > > > According to the spec we get VK_ERROR_OUT_OF_HOST_MEMORY or &

[Mesa-dev] [PATCH] anv: vkBindImageMemory() should return VK_ERROR_OUT_OF_{HOST, DEVICE}_MEMORY on error

Fixes returned value changed by b546c9d. Fixes: b546c9d ("anv: anv_gem_mmap() returns MAP_FAILED as mapping error") Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.0 17.1" <mesa-sta...@lists.freedesktop.org> --- src/intel/vulkan/anv_i

Re: [Mesa-dev] [PATCH v3 2/2] i965/vec4: load dvec3/4 uniforms first in the push constant buffer

On Wed, 2017-05-03 at 16:47 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > Reorder the uniforms to load first the dvec4-aligned variables > > in the push constant buffer and then push the vec4-aligned ones. > > > &g

Re: [Mesa-dev] [PATCH] anv: anv_gem_mmap() returns MAP_FAILED as mapping error

On Wed, 2017-05-03 at 14:37 +0100, Emil Velikov wrote: > On 3 May 2017 at 14:26, Samuel Iglesias Gonsálvez <siglesias@igalia.c > om> wrote: > > On Wed, 2017-05-03 at 14:15 +0100, Emil Velikov wrote: > > > On 3 May 2017 at 12:33, Samuel Iglesias Gonsálvez <siglesias@i

Re: [Mesa-dev] [PATCH] anv: anv_gem_mmap() returns MAP_FAILED as mapping error

On Wed, 2017-05-03 at 14:15 +0100, Emil Velikov wrote: > On 3 May 2017 at 12:33, Samuel Iglesias Gonsálvez <siglesias@igalia.c > om> wrote: > > On Wed, 2017-05-03 at 11:50 +0100, Emil Velikov wrote: > > > Hi Samuel, > > > > > > On 3 May 2017 at 08:

[Mesa-dev] [PATCH v3 2/2] i965/vec4: load dvec3/4 uniforms first in the push constant buffer

broken logic. - Add a comment to explain what should be needed to optimise the usage of the push constant buffer slots, as this patch does not pack the uniforms. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> -

Re: [Mesa-dev] [PATCH v2 1/2] i965/vec4: fix swizzle and writemask when loading an uniform with constant offset

On Tue, 2017-05-02 at 12:23 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > El Viernes, 28 de abril de 2017 16:08:35 Francisco Jerez escribió: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: &g

Re: [Mesa-dev] [PATCH] anv: anv_gem_mmap() returns MAP_FAILED as mapping error

On Wed, 2017-05-03 at 11:50 +0100, Emil Velikov wrote: > Hi Samuel, > > On 3 May 2017 at 08:57, Samuel Iglesias Gonsálvez <siglesias@igalia.c > om> wrote: > > Take it into account when checking if the mapping failed. > > > > Signed-off-by: Samuel Igle

[Mesa-dev] [PATCH] anv: anv_gem_mmap() returns MAP_FAILED as mapping error

Take it into account when checking if the mapping failed. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/vulkan/anv_allocator.c | 2 +- src/intel/vulkan/anv_image.c | 4 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] i965/vec4: fix register width for DF VGRF and UNIFORM

On Mon, 2017-05-01 at 14:55 +0200, Samuel Iglesias Gonsálvez wrote: > El Viernes, 28 de abril de 2017 16:27:56 Francisco Jerez escribió: > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On gen7, the swizzles used in DF align16 instructions works for > &

Re: [Mesa-dev] [PATCH] anv/query: handle more cases of 'out of host memory'

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Wed, 2017-04-26 at 09:03 +0200, Iago Toral Quiroga wrote: > --- >  src/intel/vulkan/genX_query.c | 10 ++ >  1 file changed, 10 insertions(+) > > diff --git a/src/intel/vulkan/genX_query.c > b/src/i

Re: [Mesa-dev] [PATCH v2 1/2] i965/vec4: fix swizzle and writemask when loading an uniform with constant offset

El Viernes, 28 de abril de 2017 16:08:35 Francisco Jerez escribió: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > It was setting XYWZ swizzle and writemask to all uniforms, no matter if > > they were a vector or scalar, so this can lead to problems when loading

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] i965/vec4: fix register width for DF VGRF and UNIFORM

El Viernes, 28 de abril de 2017 16:27:56 Francisco Jerez escribió: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > On gen7, the swizzles used in DF align16 instructions works for element > > size of 32 bits, so we can address only 2 consecuti

[Mesa-dev] [PATCH 3/3] i965/vec4: don't modify regioning parameters to the sources of DF align1 instructions

The regioning parameters are now properly set by convert_to_hw_regs() and we don't need to fix them in the generator. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> --- src/intel/compiler/brw_vec4_generator.cpp

[Mesa-dev] [PATCH 2/3] i965/vec4: fix register width for DF VGRF and UNIFORM

ources when we translate the logical swizzle to the physical one. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> --- src/intel/compiler/brw_vec4.cpp | 13 - 1 file changed, 8 insertions(+), 5 deletion

[Mesa-dev] [PATCH 1/3] i965/vec4: fix vertical stride to avoid breaking region parameter rule

oundary with that execsize and parameters (not even with the exploit), we just fix the vstride here. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> --- src/intel/compiler/brw_reg.h| 15 +++ src/intel/c

[Mesa-dev] [PATCH v2 2/2] i965/vec4: load dvec3/4 uniforms first in the push constant buffer

-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> --- src/intel/compiler/brw_vec4.cpp | 86 +++-- 1 file changed, 65 insertions(+), 21 deletions(-) diff --git a/src/intel/compiler/br

[Mesa-dev] [PATCH v2 1/2] i965/vec4: fix swizzle and writemask when loading an uniform with constant offset

) for the indirect case. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.1" <mesa-sta...@lists.freedesktop.org> --- src/intel/compiler/brw_vec4_nir.cpp | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/b

Re: [Mesa-dev] [PATCH 1/2] i965/vec4: set swizzle when loading an uniform

On Mon, 2017-04-24 at 11:22 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Fri, 2017-04-21 at 10:23 -0700, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > >

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