This was hiding bugs as it retyped the source to destination's type.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: "17.0"
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/m
s and the emitted machine code.
v2:
- Improve commit log (Curro)
- Fix read_size (Curro)
- Fix DF uniform array detection in assign_constant_locations() when
it is acceded with 32-bit MOV_INDIRECTs in BSW/BXT.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: "17.0"
---
src/mesa/d
On Thu, 2017-02-16 at 08:11 +0100, Samuel Iglesias Gonsálvez wrote:
> On Wed, 2017-02-15 at 12:08 -0800, Francisco Jerez wrote:
> > Samuel Iglesias Gonsálvez writes:
> >
> > > From: "Juan A. Suarez Romero"
> > >
> > > When converting a DF
On Wed, 2017-02-15 at 12:08 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: "Juan A. Suarez Romero"
> >
> > When converting a DF to 32-bit conversions, we set dst stride to 2,
> > to fulfill alignment restrictions because th
On Wed, 2017-02-15 at 11:45 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: Matt Turner
> >
> > On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
> > region, but on IVB and BYT DF regions must be programmed
On Wed, 2017-02-15 at 11:41 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: "Juan A. Suarez Romero"
> >
> > In IVB and BYT, both regioning parameters and execution sizes are
> > measured as
> > 32-bits element
On Tue, 2017-02-14 at 11:11 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > Previously we were emitting two MOV_INDIRECT instructions by
> > calculating
> > source's indirect offsets for each 32-bit half of a DF source.
> > However,
&g
; - assert(dst == nir_type_float64);
> - return nir_op_i2d;
> + if (dst == nir_type_float64)
> + return nir_op_i2d;
> + else if (dst == nir_type_uint64)
> + return nir_op_i2i64;
> + break;
> case nir_type_bool:
> assert(dst == nir_
Reviewed-by: Samuel Iglesias Gonsálvez
On Wed, 2017-02-15 at 18:43 +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> Signed-off-by: Dave Airlie
> ---
> src/compiler/nir/nir.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/src/compiler/nir/nir.h
Signed-off-by: Samuel Iglesias Gonsálvez
---
docs/features.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index 5905dba9b39..bb2bf884626 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -107,7 +107,7 @@ GL 3.3, GLSL 3.30
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index f1290bf7b49..9d4b109ac3f 100644
--- a
>.xyxyDF-g9<2>DF{ align16 2N };
ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed
v2:
- Add spec quote (Curro).
- Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro)
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_eu_emit.c
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++
src/mesa/drivers/dri/i965/intel_screen.c | 6 --
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965
From: "Juan A. Suarez Romero"
Take into account offset values less than a full register (32 bytes)
when getting the var from register.
This is required when dealing with an operation that writes half of the
register (like one d2x in IVB/BYT, which uses exec_size == 4).
- v2: take in account thi
Add a new setup_imm_df() that allows the insertion of the instructions
before another one. This will be used in the lowering passes for DF
instructions.
v2:
- Adapt emission of DIM instruction too.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_vec4.h | 2
ce registers must be the same
The intention was to emit mov(4)s for the instructions that have ERROR
annotations.
See tests/spec/arb_gpu_shader_fp64/execution/vs-isinf-dvec.shader_test
for example.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 2 ++
From: Francisco Jerez
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 27 --
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965
From: "Juan A. Suarez Romero"
In the generator we must generate slightly different code for
Ivybridge/Baytrail, because of the way the stride works in
this hardware.
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff
v2:
- Fix typo (Matt)
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Juan A. Suarez Romero dst.is_null() && get_exec_type_size(inst) == 8 &&
+ inst->conditional_mod != BRW_CONDITIONAL_NONE;
+
+ if (inst_df_dst_null) {
+ /* If there are other DF
We need to split DF instructions in two on IVB/BYT as it needs an
execsize 8 to process 4 DF values (one GRF in total).
v2:
- Rename helper and make it static inline function (Matt).
- Fix indention and add braces (Matt).
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965
From: "Juan A. Suarez Romero"
When splitting VEC4_OPCODE_FROM_DOUBLE in Ivybridge/Baytrail, the second
part should use a temporal register, and then move the values to the
second half of the original destination, so we get all the results in the
same register.
v2:
- Fix typos (Matt).
---
src/me
From: Matt Turner
On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
region, but on IVB and BYT DF regions must be programmed in terms of
floats. A <0,2,1> region accomplishes this.
v2:
- Apply region <0,2,1> in brw_reg_from_fs_reg() (Curro).
Signed-off-b
From: Matt Turner
Doing so allows us to use a single MOV in VEC4_OPCODE_TO_DOUBLE instead
of two.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 +++-
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13 +--
2
From: "Juan A. Suarez Romero"
Keep the original type when dealing with null registers. Specially
because we do no want to introduce an implicit conversion between
types that could affect the conditional flags.
This affects specially when the original type is DF, and we are working
on Ivybridge/B
Add support to SEL instruction and add an assert to detect unsupported
instructions than do d2x conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
Curro, this patch legalizes SEL instruction too. If other optimizations
modify later any SEL's (or any other instruction's) destin
f-by: Juan A. Suarez Romero
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 76 +++---
1 file changed, 45 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs
s registers that are available, but by the EU decompression
logic not handling VxH indirect addressing correctly.
This patch limits the SIMD width to 4 in this case.
v2:
- Fix typo (Matt).
- Fix condition (Curro)
v3:
- Add spec quote (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: J
The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.
Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
---
src/mesa
Then the SIMD lowering pass will get rid of any compressed instructions with
scalar
source (whether force_writemask_all or not) and we avoid hitting the Gen7 region
decompression bug.
Signed-off-by: Samuel Iglesias Gonsálvez
Suggested-by: Francisco Jerez
Reviewed-by: Francisco Jerez
---
src
From: Iago Toral Quiroga
4-wide DF operations where NibCtrl applies require and execsize of 8
in IvyBridge/BayTrail.
v2:
- Refactor NibCtrl printing (Matt)
Reviewed-by: Matt Turner
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i965/brw_disasm.c | 6 +++---
1 file changed, 3 insertion
From: Matt Turner
On IVB/BYT, region parameters and execution size for DF are in terms of
32-bit elements, so they are doubled. For evaluating the validity of an
instruction, we halve them.
v2 (Sam):
- Add comments.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965
tly (Matt).
- Use Baytrail instead of Valleview (Matt).
- Use IvyBridge instead of Ivy (Matt)
- Double the exec_size in code emission (Curro)
v3:
- Change hstride doubling by an assert and fix commit log (Curro).
- Substitute remaining compiler->devinfo by devinfo (Curro).
Signed-off-by: Samuel I
ect VertStride on align16 instructions.
Samuel Iglesias Gonsálvez (8):
i965/fs: clamp exec_size when an instruction has a scalar DF source
i965/fs: generalize the legalization d2x pass
i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on
IVB/BYT
i965/vec4: split DF instr
Use static inline function instead of fs_inst's method (Curro).
- Define the result as a constant (Curro).
- Fix indentation (Matt).
- Add braces to nested control flow (Matt).
Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +
This was hiding bugs as it retyped the source to destination's type.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: "17.0"
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_gener
Previously we were emitting two MOV_INDIRECT instructions by calculating
source's indirect offsets for each 32-bit half of a DF source. However,
this is not needed as we can just emit two 32-bit MOV INDIRECT without
doing that calculation.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc:
On Fri, 2017-02-10 at 10:44 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Thu, 2017-02-09 at 18:28 -0800, Francisco Jerez wrote:
> > > Francisco Jerez writes:
> > >
> > > > ---
> > > > This replaces "
On Fri, 2017-02-10 at 10:10 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Thu, 2017-02-09 at 12:18 -0800, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > It is tested empirically that IVB/BYT
The 32-bit to 64-bit conversions need to have the 32-bit
data source elements aligned to 64-bit but only with doubles as
destination type.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
Signed-off-by: Samuel Iglesias Gonsálvez
Tested-by: Mark Janes
---
src/mesa/drivers/dri/i965
On Thu, 2017-02-09 at 12:18 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > It is tested empirically that IVB/BYT don't support indirect
> > addressing
> > with doubles but it is not documented in the PRM.
> >
> > This patch appl
lear(devinfo, brw_last_inst, true);
> +
> + brw_ADD(p, spread(suboffset(addr, 1), 2),
> indirect_byte_offset,
> + brw_imm_uw(imm_byte_offset + 4));
> + brw_inst_set_no_dd_check(devinfo, brw_last_inst, true);
> +
> + brw_pop_insn_state(p);
> +
On Thu, 2017-02-09 at 18:28 -0800, Francisco Jerez wrote:
> Francisco Jerez writes:
>
> > ---
> > This replaces "[PATCH v2 09/20] i965/fs: indirect addressing with
> > doubles is not supported in IVB/BYT".
> >
>
> Note that some of the fp64 indirect addressing test-cases still fail
> on
> IVB e
It will return the current variable ('var') or the earlier declaration
('earlier') in
case of redeclaration of that variable.
In order to distinguish between both, 'is_redeclaration' boolean will indicate
in which
case we are.
Signed-off-by: Samuel Iglesias Gons
e 'var' is referenced later in ast_declarator_list::hir().
This patch fixes it by picking the ir_variable_mode from the proper
ir_variable.
This error was detected by Address Sanitizer.
Signed-off-by: Samuel Iglesias Gonsálvez
Suggested-by: Ian Romanick
Bugzilla: https://bugs.freedesktop.org/sh
r
> and
> several simplifications to the first caller. Thoughts?
>
Yeah, that could improve things.
I am going to send two patches, one is the aforementioned fix (with Cc
to mesa-stable@) and another with the refactor.
Sam
> On 02/07/2017 01:47 PM, Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index
Signed-off-by: Samuel Iglesias Gonsálvez
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri
Signed-off-by: Samuel Iglesias Gonsálvez
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
---
src/compiler/glsl/glsl_to_nir.cpp | 1 +
src/compiler/nir/nir_opcodes.py | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/glsl/glsl_to_nir.cpp
b/src/compiler/glsl
From: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index e0c2fa01ce3..a0636596318 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/
Signed-off-by: Samuel Iglesias Gonsálvez
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
---
src/mesa/drivers/dri/i965/brw_fs_lower_d2x.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_lower_d2x.cpp
b/src/mesa/drivers/dri
Signed-off-by: Samuel Iglesias Gonsálvez
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index
From: Jason Ekstrand
This fixes 143 of the new piglit tests added by Nicolai
Cc: Ian Romanick
---
.../dri/i965/brw_fs_channel_expressions.cpp| 48 +++---
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions
e 'var' is referenced later in ast_declarator_list::hir().
This patch fixes it by assign the pointer 'var' to the pointer 'earlier'.
This error was detected by Address Sanitizer.
v2:
* Pointer-to-pointer assignment (Bartosz Tomczyk)
Bugzilla: https://bugs.freedesktop.org/sh
nd a v2.
Thanks!
> On Tue, Feb 7, 2017 at 11:45 AM, Samuel Iglesias Gonsálvez @igalia.com> wrote:
> > The get_variable_being_redeclared() function can free 'var' because
> >
> > a re-declaration of an unsized array variable can establish the
> > size, so
&g
e_being_redeclared() signature:
static ir_variable *
get_variable_being_redeclared(ir_variable *var, YYLTYPE loc,
struct _mesa_glsl_parse_state *state,
bool allow_all_redeclarations)
Sam
> On Tue, Feb 7, 2017 at 11:45 AM, Samuel Iglesi
r' is referenced later in ast_declarator_list::hir().
This patch fixes it by assigning 'earlier' to var, as this variable is
the one we keep.
This error was detected by Address Sanitizer.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99677
Signed-off-by: Samuel Iglesias Gonsálvez
---
sr
Reviewed-by: Samuel Iglesias Gonsálvez
On Mon, 2017-02-06 at 21:20 -0800, Jason Ekstrand wrote:
> On Mon, Feb 6, 2017 at 9:18 PM, Jason Ekstrand
> wrote:
> > These are currently getting hit by the Skia Vulkan back-end
>
> Bugzilla: https://bugs.freedesktop.org/sho
Gentle reminder :)
Sam
On Wed, 2017-01-25 at 11:20 +0100, Samuel Iglesias Gonsálvez wrote:
> Don't lower a type conversion between different type sizes
> because SEL does't support them, SEL without conditional modifier
> just do a raw move.
>
> Signed-off-by:
Reviewed-by: Samuel Iglesias Gonsálvez
On Thu, 2017-02-02 at 13:14 -0800, Kenneth Graunke wrote:
> dEQP-EGL.functional.create_context.no_config tries to create a
> context
> with no config, then immediately destroys it. The drawbuffer is
> never
> set up, so we can't dere
Reviewed-by: Samuel Iglesias Gonsálvez
On Wed, 2017-02-01 at 17:21 -0800, Nanley Chery wrote:
> Commit 968ffd6c868af7226e8f889573eef709888151cb stored the last
> subpass
> index of all the attachments but that of the depth-stencil
> attachment.
> This could cause depth buffers u
Patch series is
Reviewed-by: Samuel Iglesias Gonsálvez
Just one minor comment on patch 3.
Sam
On Wed, 2017-02-01 at 14:40 -0800, Jason Ekstrand wrote:
> The term "lossless compression" could potentially mean multisample
> color compression, single-sample color compressio
enum isl_format format1,
> + enum isl_format format2)
> +{
> + /* They must support CCS_E */
> + if (!isl_format_supports_ccs_e(devinfo, format1) ||
> + !isl_format_supports_ccs_e(devinfo, format1))
s/format1/format2
With that c
On Mon, 2017-01-23 at 15:52 +0100, Samuel Iglesias Gonsálvez wrote:
> On Fri, 2017-01-20 at 13:41 -0800, Matt Turner wrote:
> > On Tue, Jan 17, 2017 at 1:49 AM, Samuel Iglesias Gonsálvez
> > wrote:
> > > It is tested empirically that IVB/BYT don't support indirec
Don't lower a type conversion between different type sizes
because SEL does't support them, SEL without conditional modifier
just do a raw move.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp | 2 ++
1 file changed, 2 insertions(+)
di
On Fri, 2017-01-20 at 13:41 -0800, Matt Turner wrote:
> On Tue, Jan 17, 2017 at 1:49 AM, Samuel Iglesias Gonsálvez
> wrote:
> > It is tested empirically that IVB/BYT don't support indirect
> > addressing
> > with doubles but it is not documented in the PRM.
> &g
On Fri, 2017-01-20 at 14:25 -0800, Francisco Jerez wrote:
> Matt Turner writes:
>
> > In commit c35fa7a, we changed the "width" of DF source registers to
> > 2,
> > which is conceptually fine. Unfortunately a VertStride of 2 is not
> > allowed by align16 instructions on IVB/BYT, and the regular
>
On Fri, 2017-01-20 at 13:35 -0800, Matt Turner wrote:
> I committed my EU validator earlier today. It's caught three bugs in
> the IVB
> fp64 series. Patches 2 and 3 fix two of them. I'll respond directly
> to the
> patch in Igalia's series that introduces the other bug.
>
OK, while waiting for C
On Thu, 2017-01-19 at 15:00 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Wed, 2017-01-18 at 12:44 -0800, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > On Tue, 2017-01-17 at 13:26 -080
On Thu, 2017-01-19 at 11:06 -0800, Matt Turner wrote:
> On Thu, Jan 19, 2017 at 4:50 AM, Samuel Iglesias Gonsálvez
> wrote:
> > As we are blocking the release and there more patches for review,
> > another possibility is to land this patch [2] (replacing this
> > patch)
&
On Wed, 2017-01-18 at 12:44 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Tue, 2017-01-17 at 13:26 -0800, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > From: "Juan A. Suarez Romero"
On Wed, 2017-01-18 at 11:39 -0800, Matt Turner wrote:
> On Wed, Jan 18, 2017 at 2:45 AM, Samuel Iglesias Gonsálvez
> wrote:
> > On Tue, 2017-01-17 at 13:33 -0800, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > From: Matt T
On Tue, 2017-01-17 at 13:26 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: "Juan A. Suarez Romero"
> >
> > When converting a DF to F, we set dst stride to 2, to fulfil
> > alignment
> > restrictions.
> >
&
On Tue, 2017-01-17 at 14:04 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: "Juan A. Suarez Romero"
> >
> > In IVB and BYT, both regioning parameters and execution sizes are
> > measured as
> > floats.
> >
>
On Tue, 2017-01-17 at 14:15 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: "Juan A. Suarez Romero"
> >
> > Previous to Broadwell, we have 8 registers for MOV_INDIRECT.
> >
> > According to the IVB and HSW PRMs:
On Tue, 2017-01-17 at 13:33 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: Matt Turner
> >
> > On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
> > region, but on IVB and BYT DF regions must be programmed
On Tue, 2017-01-17 at 12:26 -0800, Francisco Jerez wrote:
> Typo in the subject line "an scalar".
>
> Samuel Iglesias Gonsálvez writes:
>
> > Then the SIMD lowering pass will get rid of any compressed
> > instructions with scalar
> > source (whether
v2:
- Fix typo (Matt)
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Juan A. Suarez Romero dst.is_null() && get_exec_type_size(inst) == 8 &&
+ inst->conditional_mod != BRW_CONDITIONAL_NONE;
+
+ if (inst_df_dst_null) {
+ /* If there are other DF
Add a new setup_imm_df() that allows the insertion of the instructions
before another one. This will be used in the lowering passes for DF
instructions.
v2:
- Adapt emission of DIM instruction too.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_vec4.h | 2
From: "Juan A. Suarez Romero"
Take in account the offset value when getting the var from register.
This is required when dealing with an operation that writes half of the
register (like one d2x in IVB/BYT, which uses exec_size == 4).
Note that for live analysis variables we need to stick to per
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index b674b2f494c..69fb09813ee 100644
--- a
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++
src/mesa/drivers/dri/i965/intel_screen.c | 6 --
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965
Signed-off-by: Samuel Iglesias Gonsálvez
---
docs/features.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index aff00167dc9..c746277678c 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -107,7 +107,7 @@ GL 3.3, GLSL 3.30
From: "Juan A. Suarez Romero"
In the generator we must generate slightly different code for
Ivybridge/Baytrail, because of the way the stride works in
this hardware.
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff
We need to split DF instructions in two on IVB/BYT as it needs an
execsize 8 to process 4 DF values (one GRF in total).
v2:
- Rename helper and make it static inline function (Matt).
- Fix indention and add braces (Matt).
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965
From: "Juan A. Suarez Romero"
When splitting VEC4_OPCODE_FROM_DOUBLE in Ivybridge/Baytrail, the second
part should use a temporal register, and then move the values to the
second half of the original destination, so we get all the results in the
same register.
v2:
- Fix typos (Matt).
---
src/me
- Fix assert to take into account Indirect DF MOVs in IVB and HSW.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 27 ++
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ++-
2 files changed, 25 insertions(+
The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9
From: "Juan A. Suarez Romero"
Keep the original type when dealing with null registers. Specially
because we do no want to introduce an implicit conversion between
types that could affect the conditional flags.
This affects specially when the original type is DF, and we are working
on Ivybridge/B
Use static inline function instead of fs_inst's method (Curro).
- Define the result as a constant (Curro).
- Fix indentation (Matt).
- Add braces to nested control flow (Matt).
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +-
src/mesa/drivers/dr
Then the SIMD lowering pass will get rid of any compressed instructions with
scalar
source (whether force_writemask_all or not) and we avoid hitting the Gen7 region
decompression bug.
Signed-off-by: Samuel Iglesias Gonsálvez
Suggested-by: Francisco Jerez
---
src/mesa/drivers/dri/i965
arameters to cope with this issue.
v2:
- Use devinfo directly (Matt).
- Use Baytrail instead of Valleview (Matt).
- Use IvyBridge instead of Ivy (Matt)
- Double the exec_size in code emission (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw
From: "Juan A. Suarez Romero"
When converting a DF to F, we set dst stride to 2, to fulfil alignment
restrictions.
But in IVB/BYT, this is not necessary, as each DF conversion already
writes 2 F, the first one the real value, and the second one a 0. That
is, IVB/BYT already set stride = 2 implic
From: Matt Turner
On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
region, but on IVB and BYT DF regions must be programmed in terms of
floats. A <0,2,1> region accomplishes this.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 26 --
1 file changed, 20 i
From: Iago Toral Quiroga
4-wide DF operations where NibCtrl applies require and execsize of 8
in IvyBridge/BayTrail.
v2:
- Refactor NibCtrl printing (Matt)
Reviewed-by: Matt Turner
---
src/mesa/drivers/dri/i965/brw_disasm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --g
his patch limits the SIMD width to 4 in this case.
v2:
- Fix typo (Matt).
- Fix condition (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Juan A. Suarez Romero
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --gi
From: Matt Turner
Doing so allows us to use a single MOV in VEC4_OPCODE_TO_DOUBLE instead
of two.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 +++-
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13 +--
2 files changed, 28 insertions(+), 13 deletions
Reviewed-by: Samuel Iglesias Gonsálvez
On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_pixel_read.c | 16 ++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git
Reviewed-by: Samuel Iglesias Gonsálvez
On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote:
> There exact same check earlier in brw_miptree_layout() which
> intel_miptree_create_layout() in turn calls unconditionally.
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mes
Reviewed-by: Samuel Iglesias Gonsálvez
On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote:
> Only caller, brw_workaround_depthstencil_alignment(), returns
> early for gen6+.
>
> While at it, reduce scope for brw_get_depthstencil_tile_masks() as
> well.
>
>
Reviewed-by: Samuel Iglesias Gonsálvez
On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_meta_util.c | 44 ---
>
> src/mesa/drivers/dri/i965/brw_meta_util.h | 5
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