[Mesa-dev] [PATCH] intel/compiler/fs/icl: Use dummy masked urb write for tess eval

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_visitor.cpp | 51 ++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index af9f803fb68..6509868f1c3 100644 --- a/src

[Mesa-dev] [PATCH] intel/isl: Align clear color buffer to full cacheline

From: Rafael Antognolli Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI. CC: Anuj Phogat CC: Kenneth Graunke Tested-by: Topi Pohjolainen Signed-off-by: Rafael Antognolli --- src/intel/isl/isl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/isl

[Mesa-dev] [PATCH] intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27

Similarly to 1cc17fb731466c68586915acbb916586457b19bc Fixes gpu hangs with dEQP-VK.tessellation.shader_input_output.barrier CC: Anuj Phogat CC: Clayton Craft Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 21 +++-- 1 file changed, 15 insertions(+), 6

[Mesa-dev] [PATCH 61/61] nir: Document precision lowering pass

--- src/compiler/nir/nir_lower_precision.cpp | 106 ++- 1 file changed, 104 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_lower_precision.cpp b/src/compiler/nir/nir_lower_precision.cpp index 3d05fa2b3c9..9647fb4d6a9 100644 ---

[Mesa-dev] intel: WIP: Support for using 16-bits for mediump

/disasm: Show half-precision data_format on rt_writes Topi Pohjolainen (58): intel/compiler/fs: Set 16-bit sampler return format intel/compiler/disasm: Show half-precision for sampler messages intel/compiler/fs: Skip tex-inst early in conversion lowering intel/compiler/fs: Support

[Mesa-dev] intel/icl: RFC: Two hardware workarounds

These don't seem to fix anything (hence RFC). Moreover, vertex combining is not documented to harm anything. I thought better having them in the list anyway. CC: Anuj Phogat Topi Pohjolainen (2): intel/icl: Disable combining of vertices from separate instances intel/isl/icl: Use halign == 8

[Mesa-dev] [PATCH 2/2] intel/isl/icl: Use halign == 8 instead 4 hw workaround

CC: Jason Ekstrand CC: Nanley Chery CC: Anuj Phogat Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl_gen8.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c index 2199b8d22d..f9a424dd48 100644

[Mesa-dev] [PATCH 1/2] intel/icl: Disable combining of vertices from separate instances

Ekstrand CC: Kenneth Graunke CC: Anuj Phogat Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp_genX_exec.h | 6 ++ src/intel/vulkan/genX_pipeline.c | 6 ++ src/mesa/drivers/dri/i965/genX_state_upload.c | 6 ++ 3 files changed, 18 insertions(+) diff --git

[Mesa-dev] [PATCH] intel/compiler/icl: Use invocation id bits 22:16 instead of 23:17

CC: Mark Janes Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 23a25fedca5..757147b01ec 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b

[Mesa-dev] [PATCH] intel/compiler/icl: Use barrier id bits 24:30 instead of 24:27, 31

Fixes gpu hangs with Carchase and Manhattan. Cc: Anuj Phogat Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_visitor.cpp | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler

[Mesa-dev] [PATCH] intel/decoder: Use gen_group::dw_length when available

ViewPort: 0.00 CC: Lionel Landwerlin <lionel.g.landwer...@intel.com> CC: Kenneth Graunke <kenn...@whitecape.org> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/common/gen_decoder.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/common/g

[Mesa-dev] [PATCH] i965/urb/cnl: Apply gen7 CS stall

This didn't actually help the failing tests I'm looking at but hopefully has teeth elsewhere. CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Jordan Justen <jordan.l.jus...@intel.com> CC: Anuj Phogat <anuj.pho...@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@int

[Mesa-dev] [PATCH] i965/miptree: Initialize mcs buffer only until clear color

com> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH] mesa: Assert base format before truncating to unsigned short

CID: 1433709 Fixes: ca721b3d8: mesa: use GLenum16 in a few more places CC: Marek Olšák <marek.ol...@amd.com> CC: Brian Paul <bri...@vmware.com> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/main/teximage.c | 5 +++-- 1 file changed, 3 insertio

[Mesa-dev] [PATCH] intel/dev: Assert the number of slices is not zero

Fixes: c1900f5b intel: devinfo: add helper functions to fill... CID: 1433511 CC: Lionel Landwerlin <lionel.g.landwer...@intel.com> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/dev/gen_device_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Mesa-dev] [PATCH] nir: Check if u_vector_init() succeeds

. Coverity complains but I can mark it as ignored the same. CID: 1433512 Fixes: edb18564c7 nir: Initial implementation of a nir_instr_worklist CC: Thomas Helland <thomashellan...@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/nir/nir_wor

[Mesa-dev] [PATCH] intel/blorp/hiz: Emit CC viewport

Otherwise simulator for ICL complains that: B-spec CC_ViewPort Minimum Depth cannot be greater than Maximum Depth CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Kenneth Graunke <kenn...@whitecape.org> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --

[Mesa-dev] [PATCH 1/2] intel/isl: Add support for enabling clear color conversion

CC: Rafael Antognolli <rafael.antogno...@intel.com> CC: Jordan Justen <jordan.l.jus...@intel.com> CC: Jason Ekstrand <ja...@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/isl/isl.h | 6 ++ src/intel/isl/

[Mesa-dev] [PATCH 2/2] intel/blorp/icl: Enable clear color conversion when fast clearing

CC: Rafael Antognolli <rafael.antogno...@intel.com> CC: Jordan Justen <jordan.l.jus...@intel.com> CC: Jason Ekstrand <ja...@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/blorp/blorp_genX_exec.h | 2 ++ 1 file changed, 2 inserti

[Mesa-dev] [PATCH] i965: Don't try to disable render buffers for compute

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104546 CC: xinghua@intel.com Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_draw.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dr

[Mesa-dev] [v3 01/11] framework: Check for vulkan availability

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4259ec832..c90109907 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -173,6 +173,8 @@ ELSEIF(${CMAKE_SYSTEM_NAME} M

[Mesa-dev] v3: ext_memory_object: Test sampling memory exported from Vulkan

Here is a revision taking into account feedback from Andres and Fredrik. Many thanks for both, I hope I didn't miss anything. CC: Andres Rodriguez <andre...@gmail.com> CC: Fredrik Hoeglund <fred...@kde.org> CC: Jason Ekstrand <ja...@jlekstrand.net> Topi Pohjolainen (11):

[Mesa-dev] [v3 03/11] ext_memory_object: Add script for turning glsl into spirv c-array

This stripped down version of glsl_scraper.py found in crucible. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- .../compile_and_dump_glsl_as_spirv.py | 139 + 1 file changed, 139 insertions(+) create mode 100644 tests/spec/ext_memory_

[Mesa-dev] [v3 02/11] framework: HACK: Read glslc path from env

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index c90109907..767b90add 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -174,6 +174,7 @@ ELSEIF(${CMAKE_SYSTEM_NAME} M

[Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

This is just drafting some thoughts and only compile tested. CC: "Rogovin, Kevin" --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 + src/mesa/drivers/dri/i965/brw_context.h | 10 ++ src/mesa/drivers/dri/i965/brw_draw.c| 54 -

[Mesa-dev] [PATCH 44/51] glsl: WIP: Add lowering pass for treating mediump as float16

, coordinates are always converted into 32-bits due to logic missing in the Intel compiler backend. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/Makefile.sources | 1 + src/compiler/glsl/ir_optimization.h | 1 + src/compiler/glsl/lower_mediu

[Mesa-dev] [PATCH 29/51] intel/compiler/fs: Add register padding support

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.cpp | 3 ++- src/intel/compiler/brw_fs.h| 3 ++- src/intel/compiler/brw_fs_builder.h| 25 ++--- src/intel/co

[Mesa-dev] [PATCH 45/51] glsl: Use 16-bit constants if operation is otherwise 16-bit

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/lower_mediump.cpp | 43 - 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp

[Mesa-dev] [PATCH 41/51] intel/compiler/eu: Take stride into account in 16-bit ops

This is needed when converting from F -> HF. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_eu_validate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 6

[Mesa-dev] [PATCH 15/51] intel/compiler: Add support for loading 16-bit constants

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index a973c18203..65a5bfa49a 100644 --- a/src/intel/co

[Mesa-dev] [PATCH 51/51] i965/fs: Lower gles mediump floats into 16-bits

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_link.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index d18521e792..89ccbb06b5 100644 --- a/sr

[Mesa-dev] [PATCH 48/51] glsl: HACK: Treat input varyings as 16-bits by conversion

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/lower_mediump.cpp | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 094a

[Mesa-dev] [PATCH 33/51] intel/compiler/fs: Pad 16-bit nir intrinsic dest into full reg

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index cbb1c118d2..64243312b9 100644 --- a/src

[Mesa-dev] [PATCH 13/51] intel/compiler/disasm: Print fp16 also for sampler messages

This is what render target write does. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_disasm.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index da2a5d78dd..fbb18b0f26

[Mesa-dev] [PATCH 37/51] intel/compiler/fs: Consider original sizes when retyping alu ops

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 30 -- 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index baa8

[Mesa-dev] [PATCH 30/51] intel/compiler/fs: Pad 16-bit texture return payloads

This is to tell offset and read/write calculators enough to work correctly with 16-bit texture payloads. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff

[Mesa-dev] [PATCH 39/51] intel/compiler/fs: Consider logic ops on 16-bit booleans

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 70 ++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 2a32

[Mesa-dev] [PATCH 35/51] intel/compiler/fs: Pad 16-bit payload lowering

Otherwise copy propagation fails when write sizes differ. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.cpp | 5 - src/intel/compiler/brw_ir_fs.h | 13 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src

[Mesa-dev] [PATCH 32/51] intel/compiler/fs: Pad 16-bit nir vec* components into full reg

of register allocator working with sub-registers. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.h | 1 + src/intel/compiler/brw_fs_nir.cpp | 19 ++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/br

[Mesa-dev] [PATCH 27/51] intel/compiler/fs: Set tex type for generator to flag fp16

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.cpp | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 5751bb0ad7..0d415e2393 100644 --- a/src/intel/co

[Mesa-dev] [PATCH 46/51] glsl: Lower float conversions to mediump

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/lower_mediump.cpp | 26 ++ 1 file changed, 26 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 0276e74d6e..07f1f1ba9d

[Mesa-dev] [PATCH 50/51] glsl: HACK: Lower all temporary float variables to 16-bits

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/lower_mediump.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index bae18c9bfb..73b8aa577c 100644 --- a/src/co

[Mesa-dev] [PATCH 43/51] intel/compiler/fs: WIP: Use 32-bit slots for 16-bit uniforms

--- src/intel/compiler/brw_fs_nir.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 2060a3139d..631bbf7f92 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp

[Mesa-dev] [PATCH 17/51] intel/compiler: Prepare for glsl mediump float uniforms

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_shader.cpp | 13 + src/mesa/drivers/dri/i965/brw_program.c | 10 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_shader.cpp b/src

[Mesa-dev] [PATCH 49/51] glsl: HACK: Lower builtin float outputs to 16-bits by default

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/lower_mediump.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 45cf75b53c..bae18c9bfb 100644 --- a/src/co

[Mesa-dev] [PATCH 38/51] intel/compiler/fs: Use original reg size when retyping nir src

In case of boolean typed the values maybe given in 16-bits whereas NIR unconditionally regards them as 32-bit. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 26/51] intel/compiler/fs: Set 16-bit sampler return format

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_generator.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 20d018e1fe..610a545cd8 100644 --- a/src

[Mesa-dev] [PATCH 14/51] intel/compiler/fs: Support for dumping 16-bit IMM values

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 694fcc1919..1b972972c1 100644 --- a/src/intel/compiler/brw_fs.cpp +++

[Mesa-dev] [PATCH 31/51] intel/compiler/fs: Pad 16-bit output (store/fb write) payloads

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 6d9b272a57..d3125d7dcd 100644 --- a/src

[Mesa-dev] [PATCH 42/51] i965: WIP: Support for uploading 16-bit uniforms from 32-bit store

At this point 16-bit uniforms still take full 32-bit slots in the pull/push constant buffers and in shader deployment payload. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_compiler.h | 9 + src/intel/compiler/brw_

[Mesa-dev] [PATCH 47/51] glsl: HACK: Force texture return into 16-bits

and convert coordinates unconditionally to 32-bits. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/lower_mediump.cpp | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compile

[Mesa-dev] [PATCH 34/51] intel/compiler/fs: Pad 16-bit const loads into full regs

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 64243312b9..c455fa4e27 100644 --- a/src

[Mesa-dev] [PATCH 28/51] intel/compiler/fs: Use component_size() instead of open coded

This prepares for following patch will add 16-bit tex/fb write payload padding support. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.cpp | 2 +- src/intel/compiler/brw_fs_copy_propagation.cpp | 4 ++-- 2 files changed, 3 inse

[Mesa-dev] [PATCH 24/51] intel/compiler: Add support for negating 16-bit floats

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_shader.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index cc9297772b..3a83f55f28 100644 --- a/src

[Mesa-dev] [PATCH 18/51] intel/compiler: Allow 16-bit math

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 1507968e6c..87b144e871 100644 --- a/src

[Mesa-dev] [PATCH 40/51] intel/compiler/fs: Prepare 16-bit and/or/xor for 32-bit src

bit logic operations to use 32-bit boolean types as sources. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 21 + 1 file changed, 21 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel

[Mesa-dev] [PATCH 21/51] intel/compiler/fs: Use 16-bit null dest with 16-bit math

Even though this doesn't seem to alter anything else than dumping it is more consistent. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_generator.cpp | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/co

[Mesa-dev] [PATCH 36/51] intel/compiler/fs: Prepare nir_emit_if() for 16-bit sources

Comparison operations using 16-bit sources produce 16-bit results (0x/0x) instead of (0xFFF/0x). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff

[Mesa-dev] [PATCH 12/51] intel/compiler/disasm: Print 16-bit IMM values

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_disasm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index c752e15331..da2a5d78dd 100644 --- a/src/intel/co

[Mesa-dev] [PATCH 22/51] intel/compiler/fs: Use 16-bit null dest with 16-bit compare

Otherwise EU-emitter will deduce wrong execution size when examining source types and finding 32-bit wide register. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_nir.cpp | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-)

[Mesa-dev] [PATCH 11/51] glsl: Enable 16-bit texturing in nir-conversion

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/glsl_to_nir.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index c0adf744e0..b16efa6555 100644 --- a/src/compile

[Mesa-dev] [PATCH 25/51] intel/compiler/fs: Support for combining 16-bit immediates

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_combine_constants.cpp | 84 + 1 file changed, 71 insertions(+), 13 deletions(-) diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/co

[Mesa-dev] [PATCH 23/51] intel/compiler: Prepare for 16-bit 3-src ops

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_eu_emit.c | 21 + src/intel/compiler/brw_inst.h | 4 src/intel/compiler/brw_reg_type.c | 2 ++ 3 files changed, 27 insertions(+) diff --git a/src/intel/compiler/brw_eu_em

[Mesa-dev] [PATCH 09/51] glsl: Allow 16-bit neg() and dot()

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/ir_validate.cpp | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/ir_validate.cpp b/src/compiler/glsl/ir_validate.cpp index a20f52e527..735e862141 100644 ---

[Mesa-dev] [PATCH 19/51] intel/compiler/fs: Add helpers for 16-bit null regs

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs_builder.h | 12 1 file changed, 12 insertions(+) diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 87394bc17b..633086c64b 100644 --- a/src

[Mesa-dev] [PATCH 20/51] intel/compiler/fs: Use two SIMD8 instructions for 16-bit math

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.cpp | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 3c70231be8..5751bb0ad7 100644 --- a/src/intel/co

[Mesa-dev] [PATCH 16/51] intel/compiler: Move type_size_scalar() into brw_shader.cpp

Next path will add another variant and in order not to make brw_fs.cpp any bigger it already is, add both in brw_shader.cpp instead. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_fs.cpp | 48 --- src/intel/co

[Mesa-dev] [PATCH 10/51] glsl: Allow 16-bit math

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/ir_validate.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl/ir_validate.cpp b/src/compiler/glsl/ir_validate.cpp index 735e862141..d246af866d 100644 ---

[Mesa-dev] [PATCH 03/51] nir: Add 16-bit float support into algebraic opts

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/nir/nir_search.c | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index dec56fee74..3b28da4a3f 100644 --- a/src/compiler/nir/nir_search.c +++

[Mesa-dev] [PATCH 07/51] glsl: Add conversion ops to/from 16-bit floats

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/glsl_to_nir.cpp| 2 ++ src/compiler/glsl/ir.cpp | 8 src/compiler/glsl/ir_expression_operation.py | 5 + src/compiler/glsl/ir_validate.cpp| 8 +++

[Mesa-dev] i965: Kicking off fp16 glsl support

.net> CC: Kenneth Graunke <kenn...@whitecape.org> CC: Matt Turner <matts...@gmail.com> CC: Ian Romanick <i...@freedesktop.org> CC: Francisco Jerez <curroje...@riseup.net> Topi Pohjolainen (51): nir: Prepare constant folding for 16-bits nir: Prepare constant lowe

[Mesa-dev] [PATCH 05/51] nir: Print 16-bit constants

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/nir/nir_print.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index fcc8025346..9ed23a74bb 100644 --- a/src/compiler/nir/nir_print.c +++

[Mesa-dev] [PATCH 06/51] glsl: Add support for 16-bit float constants in nir-conversion

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/glsl_to_nir.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 1e636225c1..289f8be031 100644 --- a/src/compile

[Mesa-dev] [PATCH 08/51] glsl: Add more conversion ops to/from 16-bit floats

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/glsl/glsl_to_nir.cpp| 6 ++ src/compiler/glsl/ir_expression_operation.py | 16 ++-- src/compiler/glsl/ir_validate.cpp| 24 src/mesa/p

[Mesa-dev] [PATCH 01/51] nir: Prepare constant folding for 16-bits

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/nir/nir_opt_constant_folding.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index d6be807b3d..b63660ea4d

[Mesa-dev] [PATCH 04/51] glsl: Print 16-bit constants

--- src/compiler/glsl/ir_print_visitor.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/glsl/ir_print_visitor.cpp b/src/compiler/glsl/ir_print_visitor.cpp index ea14cdeb6c..ab9a35d73f 100644 --- a/src/compiler/glsl/ir_print_visitor.cpp +++

[Mesa-dev] [PATCH 02/51] nir: Prepare constant lowering for 16-bits constants

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/compiler/nir/nir_lower_load_const_to_scalar.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_lower_load_const_to_scalar.c b/src/compiler/nir/nir_lower_load_const_to_scalar.c

[Mesa-dev] [PATCH] intel/compiler/gen9: Pixel shader header only workaround

of the inputs (PSIZ). v3 (Ken, Jason): Use LAYER instead making vulkan emit_3dstate_sbe() happy. CC: Kenneth Graunke <kenn...@whitecape.org> CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Eero Tamminen <eero.t.tammi...@intel.com> Signed-off-by: Topi Pohjolai

[Mesa-dev] [PATCH] intel/compiler/gen9: Pixel shader header only workaround

about this corner case. CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Eero Tamminen <eero.t.tammi...@intel.com> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_compiler.h | 7 src/intel/compiler/brw_fs.cp

[Mesa-dev] [PATCH] i965/screen: Check that given format is valid

CID: 1418110 Fixes: 939b53d3325 "i965/screen: Implement queryDmaBufFormatModifierAttirbs" CC: Jason Ekstrand <ja...@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_screen.c | 2 ++ 1 file changed, 2 insertion

[Mesa-dev] i965: Two possible bug fixes

While debugging one internal workload I've been trying various things. Here are two of those. I'm not aware of them actually fixing anything but... CC: Mark Janes <mark.a.ja...@intel.com> Topi Pohjolainen (3): i965/gen8: Remove unused gen8_emit_3dstate_multisample() intel/blorp/hiz:

[Mesa-dev] [PATCH 1/3] i965/gen8: Remove unused gen8_emit_3dstate_multisample()

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h| 1 - src/mesa/drivers/dri/i965/gen8_multisample_state.c | 16 2 files changed, 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/sr

[Mesa-dev] [PATCH 3/3] i965: Disable stencil cache optimization combining two 4x2 blocks

be done at boot and all save/restore paths. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_defines.h | 5 - src/mesa/drivers/dri/i965/brw_state_upload.c | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/d

[Mesa-dev] [PATCH 2/3] intel/blorp/hiz: Always set sample number

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/blorp/blorp_genX_exec.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 5f9a8ab4a5..5389262098 100644 --- a/src/intel

[Mesa-dev] [PATCH] intel/compiler: Cast reg types explicitly

Makes coverity happier. CC: Matt Turner <matts...@gmail.com> CID: 1416799 Fixes: c1ac1a3d25 (i965: Add a brw_hw_type_to_reg_type() function) Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/compiler/brw_reg_type.c | 4 ++-- 1 file changed, 2 insertions(+),

[Mesa-dev] [v2] intel/blorp: Adjust intra-tile x when faking rgb with red-only

v2 (Jason): Adjust directly in surf_fake_rgb_with_red() Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910 CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Mark Janes <mark.a.ja...@intel.com> CC: mesa-sta...@lists.freedesktop.org Signed-off-by: Topi Pohjolainen &l

[Mesa-dev] [PATCH] intel/blorp: Adjust intra-tile x when faking rgb with red-only

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910 CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Mark Janes <mark.a.ja...@intel.com> CC: mesa-sta...@lists.freedesktop.org Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/blorp/blorp_blit.c

[Mesa-dev] [PATCH 6/6] i965/miptree: Use isl_image_offset

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c| 2 +- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 13 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 1/6] i965/miptree: Take import tile offset along with intra-tile x, y

intel_miptree_get_tile_offsets(). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 13 ++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 17 + 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/sr

[Mesa-dev] [PATCH 3/6] i965/miptree: Use isl_image_offset in get_tile_offsets()

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 54 ++-- src/mesa/drivers/dri/i965/intel_fbo.h| 14 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 28 ++-- src/mesa/drive

[Mesa-dev] [PATCH 5/6] i965/blit: Let _intratile_offset_el() resolve image offset

: get_blit_intratile_offset_el(). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_blit.c | 106 ++--- 1 file changed, 71 insertions(+), 35 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 4/6] i965/miptree: Use isl instead of local offset calculator

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_misc_state.c| 20 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 38 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 --- 3 files chang

[Mesa-dev] [PATCH 2/6] intel/isl: Introduce tiled image offset

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/blorp/blorp_blit.c | 19 -- src/intel/isl/isl.c| 44 +++ src/intel/isl/isl.h| 29 +++-- src/mesa/drivers/dr

[Mesa-dev] i965/miptree: Rework import offsets

the intra tile coordinates. Moreover, logic in various places had been split in similar fashion. This patch set brings the two parts closer each other. CC: Jason Ekstrand <ja...@jlekstrand.net> Topi Pohjolainen (6): i965/miptree: Take import tile offset along with intra-tile x,y int

[Mesa-dev] [PATCH 16/17] squash: i965/gen4: Force x-tiling for color surfaces

met the alignment constraints. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 11/17] i965/miptree: Check tex image allocation failures

mpling of over 64-bit formats. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_tex.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c index 82e25fc5ea..7ce2c

[Mesa-dev] [PATCH 10/17] main/teximage: Even on failure use valid format for init()

Otherwise init_teximage_fields_ms() (called by _mesa_init_teximage_fields()) will always assert as it can't find valid base format. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/main/teximage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 07/17] intel/isl/gen7: Allow msaa with 128-bit formats

all tests with all sample numbers and even with 128-bit formats. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/isl/isl_format.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c

[Mesa-dev] [PATCH 14/17] i965/miptree: Drop miptree_array_layout in get_isl_dim_layout()

brw_emit_surface_state(). Hence dropping the unneeded argument separately. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 11 --- src/mesa/drivers/dr

[Mesa-dev] [PATCH 17/17] i965/miptree: Clean-up unused

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources | 1 - src/mesa/drivers/dri/i965/brw_blorp.c| 8 +- src/mesa/drivers/dri/i965/brw_tex_layout.c | 735 --- src/mesa/drivers/dr

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