[Mesa-dev] [PATCH] R600/SI: Add processor types for each CIK variant

From: Alex Deucher alexander.deuc...@amd.com Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- lib/Target/R600/Processors.td |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td index 81f407e..a0735d4

[Mesa-dev] [PATCH] winsys/radeon: add env var to disable VM on Cayman/Trinity

From: Alex Deucher alexander.deuc...@amd.com Set env var RADEON_VA=0 to disable VM on Cayman/Trinity. Useful for debugging. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |2 ++ 1

[Mesa-dev] [PATCH 1/3] radeonsi: add support for hainan chips

From: Alex Deucher alexander.deuc...@amd.com Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/radeonsi_pipe.c |1 + src/gallium/drivers/radeonsi/si_state.c |3 +++

[Mesa-dev] [PATCH 2/3] radeonsi: update r600_get_llvm_processor_name for hainan

From: Alex Deucher alexander.deuc...@amd.com Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/radeonsi_pipe.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c

[Mesa-dev] [PATCH 3/3] radeonsi: add Hainan pci ids

From: Alex Deucher alexander.deuc...@amd.com Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- include/pci_ids/radeonsi_pci_ids.h |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git

[Mesa-dev] [PATCH] r600g: don't emit surface_sync after FLUSH_AND_INV_EVENT

From: Alex Deucher alexander.deuc...@amd.com It shouldn't be needed since the FLUSH_AND_INV_EVENT has already made sure the destination caches are flushed. Additionally, we didn't previously emit the surface_sync until this commit:

[Mesa-dev] [PATCH] r600g: use CP DMA for buffer clears on evergreen+

From: Alex Deucher alexander.deuc...@amd.com Lighter weight then using streamout. Only evergreen and newer asics support embedded data as src with CP DMA. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/evergreen_hw_context.c | 66 +++

[Mesa-dev] [PATCH] r600g: disable hyperz by default on 9.1

From: Alex Deucher alexander.deuc...@amd.com There are too many cases were we end up with lockups. Once we sort out the remaining issues on master, they can be backported and hyperz can be re-enabled on 9.1 Signed-off-by: Alex Deucher alexander.deuc...@amd.com ---

[Mesa-dev] [PATCH 1/2] r600g: fall back to blitter for compressed textures

From: Alex Deucher alexander.deuc...@amd.com The hw can only access compressed textures as tiled not linear so we need to do format tricks to handle them properly. The blitter code already handles this so just fallback to the blitter for compressed textures. Fixes:

[Mesa-dev] [PATCH 2/2] r600g: properly set non_disp tiling mode for DMA

From: Alex Deucher alexander.deuc...@amd.com Needs to be set just like other blocks. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/evergreen_state.c | 11 +-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 1/2] r600g: fall back to blitter for compressed textures on cayman (v2)

From: Alex Deucher alexander.deuc...@amd.com The DMA block seems to have alignment issues with large block sizes. Use the blitter for these surfaces. v2: cayman/TN only Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60802 Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex

[Mesa-dev] [PATCH 2/2] r600g: properly set non_disp tiling mode for DMA (v2)

From: Alex Deucher alexander.deuc...@amd.com Needs to be set for depth, stencil, and fmask just like other blocks. v2: drop additional cayman bits for now Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/evergreen_state.c |8 ++-- 1 files changed, 6

[Mesa-dev] [PATCH] r600g: r6xx deadlock workaround (v2)

From: Alex Deucher alexander.deuc...@amd.com Write to a CB register between draws. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=50655 https://bugs.freedesktop.org/show_bug.cgi?id=47116 v2: flush along with workaround. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex

[Mesa-dev] [PATCH 0/4] r6xx flushing rework and enable CP DMA

From: Alex Deucher alexander.deuc...@amd.com This patch set cleans up the flushing on r6xx in what seems to be a logical manner. The last patch enables CP DMA on r6xx. No piglit regressions on RS780 which I was testing on. Alex Deucher (4): r600g: add missing emit_flush for

[Mesa-dev] [PATCH 1/4] r600g: add missing emit_flush for R600_CONTEXT_FLUSH_AND_INV case

From: Alex Deucher alexander.deuc...@amd.com We set the cp_coher_cntl bits but never emit them. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600_hw_context.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git

[Mesa-dev] [PATCH 3/4] r600g: set additional cp_coher_cntl bits for 6xx/7xx flush (v2)

From: Alex Deucher alexander.deuc...@amd.com I don't see why we shouldn't be setting these bits on 6xx/7xx as well. They shouldn't hurt anything and we may be missing synchronizations with certain blocks by not setting them. The ddx already sets cp_coher_cntl in a similar manner. v2: adjust

[Mesa-dev] [PATCH 1/6] r600g: add PS_PARTIAL_FLUSH flag

From: Alex Deucher alexander.deuc...@amd.com PS_PARTIAL flushes seems to be required in certain cases to prevent hangs, especially on r6xx. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600.h|1

[Mesa-dev] [PATCH 2/6] r600g: r6xx deadlock workaround (v6)

From: Alex Deucher alexander.deuc...@amd.com Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=50655 https://bugs.freedesktop.org/show_bug.cgi?id=47116 v2: flush along with workaround. v3: just need a flush v4: try WAIT_UNTIL v5: switch to PS partial flush v6: rework patch Note: this is a

[Mesa-dev] [PATCH 3/6] r600g: emit a ps partial flush after CP DMA

From: Alex Deucher alexander.deuc...@amd.com May fix: https://bugs.freedesktop.org/show_bug.cgi?id=58042 Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600_hw_context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git

[Mesa-dev] [PATCH 4/6] r600g: synchronize streamout buffers on r6xx too (v3)

From: Alex Deucher alexander.deuc...@amd.com Streamout buffers need to be synchronized on r6xx as well. v2: Add DEST flush as well. v3: drop DEST flush Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600_hw_context.c |2 +- 1 files changed, 1

[Mesa-dev] [PATCH 5/6] r600g: add missing emit_flush for R600_CONTEXT_FLUSH_AND_INV case

From: Alex Deucher alexander.deuc...@amd.com We set the cp_coher_cntl bits but never emit them. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600_hw_context.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git

[Mesa-dev] [PATCH 6/6] r600g: enable CP DMA on r6xx (v3)

From: Alex Deucher alexander.deuc...@amd.com With the previous flushing changes this seems to work reliably now. v2: add R600_CONTEXT_FLUSH_AND_INV v3: just enable CP DMA Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600_blit.c |3 +--

[Mesa-dev] [PATCH] r600g: don't enable ReZ mode on evergreen

From: Alex Deucher alexander.deuc...@amd.com Can cause lockups in certain cases when zfunc/zenable/zwrite change without a flush in between. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60969 This is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher alexander.deuc...@amd.com

[Mesa-dev] [PATCH] r600g: don't emit WAIT_UNTIL on cayman/TN (v2)

From: Alex Deucher alexander.deuc...@amd.com It shouldn't be needed and older kernels don't support it. v2: Replace with PS partial flush as before. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59945 Signed-off-by: Alex Deucher alexander.deuc...@amd.com ---

[Mesa-dev] [PATCH] r600g: don't emit WAIT_UNTIL on cayman/TN

From: Alex Deucher alexander.deuc...@amd.com It shouldn't be needed and older kernels don't support it. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59945 Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600_hw_context.c |6 -- 1 files changed,

[Mesa-dev] [PATCH] r600g: fix up CP DMA for VM on cayman and TN

From: Alex Deucher alexander.deuc...@amd.com Need to add the virtual address. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600.h|4 ++-- src/gallium/drivers/r600/r600_hw_context.c | 11 +++ 2 files changed, 9 insertions(+), 6

[Mesa-dev] [PATCH 1/2] radeonsi: emit PA_SC_RASTER_CONFIG

From: Alex Deucher alexander.deuc...@amd.com Use per asic golden values. Programming this register doesn't seem to be strictly necessary on SI, but programming it wrong leads to rendering issues or reduced performance so just go ahead and program the golden values explicitly to avoid any

[Mesa-dev] [PATCH 2/2] radeonsi: clean up some magic numbers

From: Alex Deucher alexander.deuc...@amd.com Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c

[Mesa-dev] [PATCH 1/3] radeonsi: assert that the DB format is valid

From: Alex Deucher alexander.deuc...@amd.com Rather than disabling the depth buffer. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c |9 +++-- 1 files changed, 3 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 2/3] radeonsi: assert the CB format is valid

From: Alex Deucher alexander.deuc...@amd.com Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c

[Mesa-dev] [PATCH 3/3] radeonsi: cleanup si_db()

From: Alex Deucher alexander.deuc...@amd.com Clean up a few magic numbers and rework the code a bit. Signed-off-by: Alex Deucher alexander.deuc...@amd.com Reviewed-by: Christian König christian.koe...@amd.com Reviewed-by: Michel Dänzer michel.daen...@amd.com ---

[Mesa-dev] [PATCH 1/3] radeonsi: assert that the DB format is valid (v2)

From: Alex Deucher alexander.deuc...@amd.com Rather than disabling the depth buffer. v2: use INVALID hw format rather than ~0U Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c | 13 + 1 files changed, 5 insertions(+), 8

[Mesa-dev] [PATCH 2/3] radeonsi: assert the CB format is valid (v2)

From: Alex Deucher alexander.deuc...@amd.com v2: use INVALID hw format rather than ~0U Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 3/3] radeonsi: cleanup si_db()

From: Alex Deucher alexander.deuc...@amd.com Clean up a few magic numbers and rework the code a bit. Signed-off-by: Alex Deucher alexander.deuc...@amd.com Reviewed-by: Christian König christian.koe...@amd.com Reviewed-by: Michel Dänzer michel.daen...@amd.com ---

[Mesa-dev] [PATCH 1/3] radeonsi: return Z_INVALID if the Z buffer is invalid

From: Alex Deucher alexander.deuc...@amd.com setting the DB format to Z_INVALID disables the depth buffer. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c | 10 +++--- 1 files changed, 3 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 2/3] radeonsi: return_INVALID if the color buffer is invalid

From: Alex Deucher alexander.deuc...@amd.com setting the CB format to Z_INVALID disables the color buffer. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 3/3] radeonsi: cleanup si_db()

From: Alex Deucher alexander.deuc...@amd.com Clean up a few magic numbers and rework the code a bit. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/si_state.c | 22 ++ src/gallium/drivers/radeonsi/sid.h |2 ++ 2 files

[Mesa-dev] [PATCH 0/5] r600g: Fix common state for cayman compute

From: Alex Deucher alexander.deuc...@amd.com This patch set cleans up and unifies the common state and CS init set up between evergreen and cayman and gfx and compute. No piglit regressions on the gfx side here. This also allows compute to run on cayman without causing a CS error in the kernel

[Mesa-dev] [PATCH 1/5] r600g/compute: always CONTEXT_CONTROL packet at start of CS

From: Alex Deucher alexander.deuc...@amd.com It's required. The CP uses this to properly allocate new contexts. Also do a CS partial flush since we are updating CONFIG regs which are single state. Signed-off-by: Alex Deucher alexander.deuc...@amd.com ---

[Mesa-dev] [PATCH 2/5] r600g: rework evergreen_init_common_regs()

From: Alex Deucher alexander.deuc...@amd.com Move gfx specific bits out as the code is shared with compute. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/evergreen_state.c | 73 +--- 1 files changed, 33 insertions(+), 40

[Mesa-dev] [PATCH 3/5] r600g: there are 16 const buffer size regs for each shader stage

From: Alex Deucher alexander.deuc...@amd.com we were previously only setting 8 of them. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/evergreen_state.c | 21 +++-- 1 files changed, 19 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 4/5] r600g: emit some additional regs on cayman

From: Alex Deucher alexander.deuc...@amd.com These are common to both evergreen and cayman, but were not emitted on cayman. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/evergreen_state.c | 54 1 files changed, 54

[Mesa-dev] [PATCH 5/5] r600g: split cayman common state out into a shared function

From: Alex Deucher alexander.deuc...@amd.com And use it for compute. This should improve compute support on cayman. Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/evergreen_compute.c |8 - src/gallium/drivers/r600/evergreen_state.c | 39